efficient packet pattern matching for gigabit network intrusion detection using gpus
DESCRIPTION
Efficient Packet Pattern Matching for Gigabit Network Intrusion Detection using GPUs . Date:102/1/9 Publisher:IEEE HPCC 2012 Author: Che-Lun Hung, Hsiao- hsi Wang, Chin-Yuan Chang, Chun-Yuan Lin Presenter : Shi- qu Yu. GPGPU PROGRAMMING. Global Memory - PowerPoint PPT PresentationTRANSCRIPT
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Efficient Packet Pattern Matching for Gigabit Network Intrusion Detection using GPUs
Date:102/1/9Publisher:IEEE HPCC 2012Author:Che-Lun Hung, Hsiao-hsi Wang, Chin-Yuan Chang, Chun-Yuan LinPresenter : Shi-qu Yu
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GPGPU PROGRAMMING
• Global MemoryGlobal memory is the biggest memory region available
on CUDA devices and is capable of storing hundreds of megabytes of data. In the CUDA Fermi architecture [17], theL1 cache per SM multiprocessor is configurable to support the global memory operations. Therefore, the access latency of global memory is comparable to other GPU memory architectures.
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GPGPU PROGRAMMING
• Constant MemoryConstant memory is a small read-only memory regionthat resides in DRAM on CUDA devices. It is globallyaccessible memory for all threads. Since Constant memoryhas on-chip cache, the access latency is short. The cost of acache-hit is as a local register access, but the cost of a cache miss is as a global memory access on devices. The constantmemory is limited to its size.
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GPGPU PROGRAMMING
• Texture memoryEach multi-processor on the CUDA device equips a 64KB texture cache which can be bound to one or more arbitrarily sized region of global memory. Texture memory is read only as constant memory.
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GPGPU PROGRAMMING
• Shared memoryShared memory is block-local that facilitates cooperationbetween multiple threads in a thread block. Shared memoryis limited to 64KB per multi-processor on CUDA Fermi devices. The access latency of shared memory is equivalent to that of register.
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GPGPU PROGRAMMING
• RegistersEach block on CUDA device equips a register file thatcontains registers. The register provides fast thread-localstorage during kernel execution. In the Fermi architecture,each multi-processor contains the amount of 32-bit registers(32,000) that are shared for all threads in the executingthread block.
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Method
A. InitializationB. Pattern Matching processing on GPUC. Data Output
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Method
A. Initialization1. ZeroCopy2. Page-locked memory3. Each thread searches in n bytes where n is the maximum
pattern length. Therefore, the total size of combined packets isL = n X T
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Method
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EXPERIMENTCPU Intel i3 540 3.07GHz
Host memory 8GB DDRIII-1333
GPU GeForceGTS 450
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EXPERIMENT
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EXPERIMENT
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EXPERIMENT