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Copyright © 2011 American Scientific PublishersAll rights reservedPrinted in the United States of America

Journal ofNanoscience and Nanotechnology

Vol. 11, 1–4, 2011

Effects of Device and Peripheral Parameters onTransconductance of Silicon Nanowire Transistors

Mahmoud Zangeneh1�∗, Hossein Aghababa2, and Behjat Forouzandeh21Department of Electrical and Computer Engineering, Boston University, Boston, MA 02215

2School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran

This paper presents a general analysis over the transconductance function in silicon nanowiretransistors (SNWTs). The transconductance function in SNWTs has been well-discussed and therelation between this function and the physical and peripheral parameters of the SNWT has beenprecisely investigated. The transconductance expression has been derived as a function of deviceparameters (e.g., oxide capacitor, electron effective-mass) and applied voltage biases, which helpsto understand the essential physics of one-dimensional (1D) nanowire FETs and to interpret numer-ical simulation results. These simulations demonstrate the transconductance formulation as a func-tion of environmental temperature, voltage biases and oxide layer thickness.

Keywords: Device Parameters, Transconductance, Silicon Nanowire Transistor, NumericalSimulation.

1. INTRODUCTION

One of the good candidates for next generation devicesamong various new-concept transistors is a gate-all-around(GAA) silicon (Si) nanowire transistor.1–4 This is dueto predicted good properties such as good conductance,5

short-channel effect (SCE) immunity, low leakage current,etc., while a transistor scales down. However, most Sinanowire transistors using the bottom–up process have notwell estimated their performance due to process limitationand reproducibility.6 Due to the 1-D channel geometry,the electrostatics of nanowire devices can be quite differ-ent from bulk silicon devices. Previous studies of carbonnanotube p/n junctions and metal/semiconductor junctionsdemonstrated unique properties of nanotube junctions. Forexample, the charge transfer into the nanowire channelfrom the metal contacts (or heavily doped semiconductorcontacts) can be significant.7

Among all promising post-CMOS structures, the sili-con nanowire transistor (SNWT in Fig. 1) has its uniqueadvantage—the SNWT is based on silicon, a material thatthe semiconductor industry has been working on for overthirty years; it would be really attractive to stay on siliconand also achieve good device metrics that nanoelectron-ics provides. As a result, the silicon nanowire transistorhas obtained broad attention from both the semiconductorindustry and academia.

∗Author to whom correspondence should be addressed.

Several proposed models have been used to clearlyinterpret the ballistic FET functionality. In Ref. [8], theauthors proposed a general ballistic FET model (named‘FETToy’) that correctly captures quantum confinement,two-dimensional (2D) electrostatics, and bias-charge self-consistency in ballistic FETs. It generalizes Natori’smodel9 by treating 2D electrostatics and by properly treat-ing the 1D electrostatics—even in the quantum capacitorlimit, where the gate insulator capacitor is much greaterthan the semiconductor (or quantum) capacitor.10

We will describe an analytical theory of ballistic siliconnanowire transistors. The model is derived by modifyingan analytical approach proposed by Rahman et al. for bal-listic planar MOSFETs11 and extended by Wang et al.12 forballistic high electron mobility transistors (HEMTs). Themain part of this paper will discuss the transconductancefunction of the ballistic nanowire transistors. The expres-sion for the transconductance function of a 1D SNWT hasbeen introduced and analyzed in different resources. How-ever, this expression has not been defined in terms of thephysical device parameters or applied voltage biases to thegate of drain of the transistor.Therefore, the effect of the applied voltages to the dif-

ferent terminals of the transistors will be precisely dis-cussed. These voltages enter the potential expression atthe top of the barrier as each potential affects the spe-cific value of capacitor which is derived from the phys-ical schematic of the transistor terminals such as oxide

J. Nanosci. Nanotechnol. 2011, Vol. 11, No. xx 1533-4880/2011/11/001/004 doi:10.1166/jnn.2011.3996 1

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GATE

SNW

SiO2

DRAINSOURCE

Si-substrate

Fig. 1. Schematic view of the SNWT device structure, SNW acts as aconducting channel.

thickness, diameter of the silicon body and oxide dielec-tric constant. Furthermore, these expressions enter the I–Vcharacteristic function of the transistor which can finallylet us reach the transconductance function and its relativederivations in ballistic silicon nanowire transistors.This paper is arranged in this way: The authors’ method-

ology about the behavior of nanowie transistor is presentedin Section 2. The formulation over transconductance func-tion of the nanowire transistor is described in Section 3. InSection 4, simulation results are presented. The conclusionis stated in Section 5.

2. METHODOLOGY

In this section, we will try to summarize the essentialaspects of our proposed model. Figure 2 illustrates the fea-tures of the analytical ballistic model. As it is clear inthis model, there exist three capacitors between the appliedvoltages and the input terminals of the transistor. Thesecapacitors describe the electrostatic couplings between thetop of the barrier and the gate, the source and the drain.The potential at the top of the barrier is obtained as:11

Uscf =(

CG

CG+CD+CS

)VG+

(CD

CG+CD+CS

)VD

+(

CS

CG+CD+CS

)VS+

QTOP

�CG+CD+CS�

(1)

where VG, VS, and VD are the applied biases at the gate, thesource and the drain, respectively, and QTop is the mobilecharge at the top of the barrier, which is determined byUscf , the source and drain Fermi levels (EFS and EFD� and

VG

CG

CD

VD

CS

Fig. 2. The 3 capacitor model to treat 2D (3D) electrostatics innanoscale FETs.

the E-k relation for the channel material. For a planardouble-gate MOSFET, the gate oxide capacitor, CG, is ana-lytically obtained as

CG = 2K�0

T0x(2)

For a nanowire FET, however, the gate oxide capacitordoes not have an analytical expression in general, so itshould be numerically computed by solving a 2D Poissonequation at the cross-section of the SNWT. In this section,we assume coaxial gate geometry, for which the gate oxidecapacitor, CG, can be analytically obtained as:13

CG = 2�K�0

ln��2Tox+TSi�/TSi�(3)

Where K is the oxide dielectric constant, �0 is the per-mittivity of vacuum and Tox is the oxide thickness and TSiis the diameter of the silicon body. Due to the 1D E-krelation for a nanowire FET, the equations for the SNWTcharge density and current are different from those for 2Dplanar MOSFETs. As it is clear in Figure 2, the source isgrounded, thus the third part in (1) is omitted. However,there almost exists no closed-form expression for drain andsource capacitor. Thus, to capture the 3D electrostatics inthe simulated nanowire FETs, we assume the followingtwo expressions:

�G = CG

CG+CD+CS

= 0�88 (4)

�D = CD

CG+CD+CS

= 0�035 (5)

What can be inferred from (4) and (5) is the dominanceof gate capacitor in comparison with the total capacitorof the transistor. Also the drain capacitor is assumed tobe negligible in front of the total capacitor of the transis-tor which is logically reasonable. Now that the physicalparameters of the nanowire transistor are determined, nextstep is to come up with the transconductance function ofthe SNWT.

3. FORMULATION

In this section, we will try to derive a closed-form expres-sion for the transconductance function of the SNWT andprecisely analyze the behavior of it, including the rela-tion between this function and the physical parameters ofthe device. This function may be derived by applying thepartial deviation to I–V characteristic function of the tran-sistor. The potential at the top of the barrier is used tospecify the following parameter of the transistor:13

�F = �s − ���0�−qUscf�

kBT(6)

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where �S is the source Fermi level, q is the electroncharge, kB is the Boltzmann constant, T is the ambienttemperature and �(0) represents the lowest subband level atthe top of the barrier when Uscf = 0. Also, the electron cur-rent for a nanowire FET can be analytically expressed as:11

I = MqkBT

���0��F �−�0��F −UD�

= MqkBT

��ln(

1+ e�F

1+ e�F −UD

)(7)

UD in (7) is defined by the following equation:

UD = VDS

kBT(8)

Where VDS = VD–VS and as far as the source is grounded,this value would be the applied drain bias. Also, thefunction �j ��� is so called Fermi integral,14 which isdefined as:

�j ���=1

��j+1�

�∫0

xjdx

1+ exp�x−��(9)

It is worth mentioning that we assumed coaxial gategeometry and neglect the quantum confinement so thatan analytical expression of the gate oxide capacitance isobtained. In general, to evaluate the gate oxide capacitancefor an arbitrary SNWT structure with the considerationof quantum confinement, which keeps the electron chargecentroid somehow away from the Si/SiO2 interfaces, a 2DPoisson equation, needs to be numerically solved togetherwith a 2D Schrödinger equation. Now, we will derive anexpression for the transconductance of nanowire transis-tor. As it is well-accepted, transconductance for a FET isdefined as:

gm = �I

�VGS

∣∣∣∣@high VDS (10)

Thus, the transconductance expression for a SNWT willbe:

gm = �I

�VGS

∣∣∣∣UD � 1 = MqkBT

��

��0��F�

�VGS

= Mq2

��

e�F

1+ e�F

�Uscf

�VGS

(11)

We recall that the source is assumed to be grounded.Also there assumed to be no mobile charge at the top ofthe barrier. Comparing Eqs. (1), (4) and (5) leads to thefollowing expression for the deviation of the deviation ofthe potential at the top of the barrier:

�Uscf

�VGS

= �G (12)

Thus, the expression for the transconductance of aSNWT can be written by inserting (12) in (11) as follows:

gm =Mq2

��

e�F

1+ e�F�G =M

2q2

h

�G

1+ e�F(13)

4. SIMULATION RESULTS

In this section, we will try to simulate the behavior of thetransconductance function of SNWT mentioned in (13).Figure 3 illustrates the transconductance expression of theSNWT as a function of gate-source applied voltage indifferent temperatures. As it is clear in this figure, whenVGS > 0�35 V in the ambient temperature, the device entersthe full-degenerate regime. However, there would be athreshold in saturation as lower temperature needs smallervoltage to start saturation. Moreover, the slope of satura-tion is more in higher temperature.Figure 4 illustrates the transconductance expression of

the SNWT as a function of drain-source voltage in dif-ferent gate-source applied voltages. As it is clear in thisfigure, the transconductance expression of the SNWT isan entirely increasing function of Vds. This is due to incre-ment of the potential at the top of the barrier by increas-ing the value of Vds as it is inferred from combinationof (1), (6) and (13). Moreover, with applying the greatervalue for gate-source voltage, the increment in transcon-ductance behavior is reasonable as this function is entirelyincreasing. However, a clear jump is observable in Figure 4when the gate-source voltage passes 0.4 V. This jump isdue to the entrance of the SNWT to the saturation region.The discussed jump is not noticeable when the gate-sourcevoltage reaches 0.5 V.Figure 5 illustrates the transconductance expression of

the SNWT as a function of oxide thickness. As it isclear in this figure, the function is entirely decreasing.This behavior is logically justifiable. As it is clear in

Fig. 3. Transconductance function of the SNWT in differenttemperatures.

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Fig. 4. Transconductance function of the SNWT as a function of Vds.

Fig. 5. Transconductance function of the SNWT as a function of Tox.

(2) and (3), increasing the oxide thickness of the SNWTleads to decrement in gate capacitor which directly leadsto the decrement of the potential at the top of the bar-rier. This decrement in Uscf will cause �F to be smallerthan the previous value (Eq. (6)). As �F appears in neg-ative form of exponential function in denominator of thetransconductance of the SNWT, decreasing the result isclear. The same scenario can be used to justify the jump

in transconductance function when the gate-source appliedvoltage reaches 0.45 V.

5. CONCLUSION

In this paper, we have used closed-form expressions for thetransconductance function in silicon nanowire transistors.This transconductance expression is a function of appliedvoltages to the terminals of the transistor, the environmen-tal temperature and the physical parameters of the SNWTsuch as oxide and silicon body thickness. We also verifiedthe expression by some simulation results. These simula-tions illustrate the transconductance function by sweepingthe gate-source and drain-source voltages, the environmen-tal temperature and the oxide thickness of the transis-tor. The proposed figures prove that the transconductancebehavior of the SNWT is a monotonically increasing func-tion of the gate-source and drain-source voltages and is amonotonically decreasing function of the oxide thickness.Moreover, temperature affects the saturation region of thetransconductance function.

References and Notes

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Received: 30 December 2009. Revised/Accepted: 30 August 2010.

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