eeweb pulse - issue 59, 2012

7/31/2019 EEWeb Pulse - Issue 59, 2012

1/19

PULSEEEWeb.com

Issue August 14, 2012

Alan GotcherCEO

Xtreme Power

Electrical Engineering Community

EEWeb


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3/19EE Web | Electrical Engineering Community Visit www.eeweb.com 3

TA B L E O F C O N T E N T S

Alan Gotcher 4XTREME POWER

Featured Products 9

BYDAVE LACEY

WITH XMOS

For Those About to Clock, We Salute YouBY BILLIE JOHNSON WITH ON SEMICONDUCTOR

RTZ - Return to Zero Comic

Interview with Alan Gotcher - CEO

The nasty end of programming made easier--a look at what debugging tools are most effectivefor your system.

A look into clock tree synthesis relating to hierarchal approaches, low power considerations andnew flow recommendations for smaller geometries.

The Other Halting Problem: Debuggingin a Real-time Environment 11

15

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I N T E RV I E W

Xtreme

A lanGotcher

Power How did you get into theelectrical engineering eld?I came out of the University of California systemI was at theIrvine campuswith a PhD inChemistry and I went to work for amaterial science company calledRaychem. I spent ten years thereand became the Chief TechnicalOfficer at Avery Dennison, which isa company based out of Pasadena,California, where I spent fifteen

years. After that, I went and startedmy own venture capital firm. Oneof the firms we invested in was ananomaterials company, which ledme into energy storage and productdevelopment in the energy space.I came to Xtreme Power last yearand became their Chief TechnicalOfficer; in January of this year, I

was promoted to the position of President and CEO.



I N T E RV I E W

Tell us a little bit about XtremePower. What kind of productsdo you sell and what marketsare you targeting?

Xtreme Power was founded backin 2004, so its a young, rapidly growing, venture capital-backedfirm that has doubled its sales in thelast two years. In terms of products,

Part of our growthstrategy is to expand

geographically; we seeterrific opportunity inAsiain particular,

China and India.The other part of ourstrategy is to develop

products that willtarget needs in the

marketplace that arenot very well-satisfied

by other solutions.

our largest product family is theDynamic Power Resource. Thisproduct is an integrated powermanagement and energy storagesystem that provides solutions to a

variety of market segments includingrenewable integration (wind powerand solar power) onto the grid. TheDynamic Power Resource provides

firming, smoothing and ramp ratecontrol. This removes the variability

you get from wind when it pulsesand from sun when its cloudy.

We also provide products that areintegrated onto micro-grids. Theseare typically in areas where the gridis really small, like on an island.

What we do there is offer a variety of services to strengthen the grid onthat islandwhether it is providingpower or for instance if they havea transformer go out, well quickly respond with however much powerthat transformer was providing tothe grid as well as provide power

quality management. This is a four-quadrant product, which providesthe ability to push real and reactivepower to the grid, andif needbepull it from the grid. Our systemsizes vary; our smallest is onemegawatt, and the largest product

we are fielding right now, which isfor Duke Energy, is 36 megawatts.

What other types of uses are

there for the Dynamic PowerResource?

As I said before, the Dynamic PowerResource is an integrated solutionconsisting of power electronics,and an energy storage device wemanufacture called PowerCells,and power management softwarethat we have developed internally.

We combine the power electronics, which control the power and quality

of that power with the energy storagedevice; thats where the electronsgo for the duration of when yourepushing or storing this energy. Weintegrate those components withour software, which allows us to doreal-time control. We have six sitesthat are fieldedfive of them wemonitor continuously and every few

seconds, we grab data from the siteand store it both locally and herein our Texas database. This allowsus to control that site remotely andmake sure that our customer isgetting exactly the service that weveoffered them. Whats unique aboutour real-time control is that we canprovide power quality managementand voltage regulation several timesa day.

How big are your plantstypically?Our plants are remarkably smalland compact. A plant that runs inthe size of 10 to 35 megawatts wouldtypically be 20,000 to maybe 50,000square feet, which is around half anacre to just over an acre.

What kind of technologydo you use for your storagemechanisms?The PowerCell is an advancedlead-acid battery. We picked thatintentionally because advancedlead-acid allows you to extractthousands of amps of current very rapidly and allows you to swing upto 30 megawatts of power and pushit to the grid. Or, in 30 milliseconds(0.03 seconds), we can go from full-power out to full-power storage.

We really like that storage deviceand over the next year, youll seeus introduce additional storagetechnologies.

What are some theadvantages of using this typeof system?For example, if you look at data-center services, you are worriedabout losing your connection tothe grid and experiencing theoccasional flutter where the voltage



I N T E RV I E W

or frequency varies a bit, which isntgood for servers. Most of the time,data-centers will have a large groupof diesel-powered generators todetect when theres a change inpower going into the data-centerand power the grid until regularpower is restored. Our system can

work hand-in-hand with the diesel-power generator; instead of 30, 40or 50 of these generators, we canreduce them by at least 50%. Thisreduces the fuel load to these data-centers and substantially reducesthe CO2 emissions caused by diesel-fired electric generators.

We are a nice complement to theseuninterruptable power supply (UPS)systems, and our technology givesthese customers more reliability and allows them to use two differenttypes of technologies to keep thesedata-centers running.

How would you describe theculture at Xtreme Power?Today, we are located at four sites

two sites in Texas, a manufacturingfacility in Oklahoma, and a recently opened office in Beijing, China.I would say the culture at all of our locations is fast-paced withhighly skilled employees that aresmart and hard-working and, mostimportantly, I think we are all havinga lot of fun. There is a feeling that

we may be able to positively impactthe power industry in a number of

different nations and islands, so itsa very exciting time.

What are some of thethings you look for in hiringengineers?

We hire a lot of engineers, but wealso hire a lot of people that areexperienced in manufacturing,

Figure 1: DRP SolarTAC Container

Figure 2: Xtreme Power System

business development, marketingand sales. The types of employees

we are looking for are intelligentpeople who can speak their mindclearly, and people who are very straightforward with a lot of energy.

We also value diversity, and withthat comes the ability to expressdifferent points of views on dataand to be issue-focused, so that thedecisions we make as a team are

well-grounded and well-articulated.



I N T E RV I E W

What kinds of patents do youand your company have?

At Xtreme Power we are alwayslooking for new, innovative solutions.Our engineers and even ourbusiness development people arecoming up with ideasthat are uniqueand create value for our customers.

We then look at our IP and decide whether we should patent it ornot. Our IP is generally focusedon our software and integration,so it allows us to have these fast-responding multi-services that wecan layer onto our products to solvecustomers problems.

What direction do you seeyour company headed in thenext 5-10 years?

Were a pretty small company rightnow, but we are rapidly growing. Partof our growth strategy is to expandgeographically; we see terrific

opportunity in Asiain particular,China and India. The other part of our strategy is to develop productsthat will target needs in the

I would say the cultureat all of our locations isfast-paced with highly

skilled employeesthat are smart andhard-working and,most importantly,I think we are all

having a lot of fun.

marketplace that are not very well-satisfied by other solutions. Onearea that is in our sight is whatscalled a digital peaker. Today, when

you have a peak load coming off the grid, operators who generateelectricity will turn on peaking powerplants, which are typically basedon natural gas. These plants arelarge, ranging from 50 megawattsto several hundred megawatts, andthey come on for a short period of time, for a few days a year. We seethis as an opportunity to bring in ourDynamic Power Resource and sizeit around 25 to 50 megawatts. So,

rather than having one large plant inone spot, what we could do is havemultiple plants that are small, quietand compact with zero emissionsin areas that are typically moredifficult to develop. We see this as apotentially large market opportunity for Xtreme Power.

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Avago Technologies, an industry leaderin IGBT Gate Drive technology solutionsintroduces our Next Generation series!

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F E AT U R E D P R O D U C T S

6-Bit Digital Step AttenuatorsRFMDs new RFSA2644/2654 6-bit digital step attenuators (DSAs) featurehigh linearity over their entire 31.5dB gain control range with excellentstep accuracy in 0.5dB steps. They are programmed via a serial mode

control interface that is both 3V and 5V compatible. They also offer arugged Class 1C HBM ESD rating via on-chip ESD circuitry. The MCMpackage is footprint-compatible with most 24-pin, 4mm x 4mm, QFNpackages. For more information, please click here .

Automotive Power MOSFETsInternational Rectifier, announced the introduction of the AUIRFR4292and AUIRFS6535 automotive-qualified power MOSFETs featuring low on-state resistance (Rds(on)) for Piezo injection systems for both gasolineand diesel engines. Utilizing IRs latest generation of proven automotive

power MOSFET technology, the AUIRFR4292 and AUIRFS6535 extendthe range of IRs automotive-qualified MOSFET portfolio to breakdown voltage up to 300V. The new devices are qualified according to AEC-Q101 standards, feature an environmentally friendly, lead-free and RoHScompliant bill of materials. For more information, please click here .

Radial Lead Super CapacitorsThe new DCN series of super capacitors from Illinois Capacitoroffers capacitance values up to an astonishing 3,500 Farads, whilemaintaining small case sizes. Custom modules are also available tocombine multiple capacitors for combinations of higher voltage ratingsor capacitance. The DCN Series now includes an expanded range of

values and voltages, from 1 F (Farad) to 3,500 F with voltage ratings fromto 5.5WVDC. Operating temperature ranges from -40C to +60C forextended life performance in countless applications. The new additionsextend the capabilities of the series into applications where capacitorsmay not have been previously considered. For more information, pleaseclick here .

Micro-Sized 3-Axis GyroscopeSTMicroelectronics unveiled its smallest, lowest-power and highest-performance chip-scale gyroscope for advanced motion-sensingapplications. This gyroscope measures only 3 3mm and 1mmhigh the smallest available while the Companys proven MEMSmanufacturing processes deliver outstanding quality, at the industryshighest production volumes. Occupying little over half the volume of itspredecessor, yet offering better resolution, higher accuracy, superiorstability and faster response time, the new device enables smallersensing mechanisms in smart consumer electronics, including mobilephones and tablets, game consoles, digital cameras and industrial tools.For more information, please click here .

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10/19

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Dave Baarman DirectorOf

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JOINTODAY
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L ets talk about the nasty end of programming:debugging. The cause of many sleepless nights and losthair. Everyone has to go through it and the easier it canbe made the better.

The majority of time debugging is not spent removingbugs but understanding code behavior. Once youunderstand why undesirable behavior is happening it isusually relatively easy to fix this behavior.

There are many tools around to help with debugginga system and each helps in a different way. However,across the different tools we can categorize how they help us understand a system.

Tools may vary in scope i.e. what part of the system thetools looks at, and they may also vary in function i.e. whatthe tool actually does. With regards to scope, there aretools that look at the internal state of our code i.e. the

The Other

HaltingProblem

: Debugging in a Real-Time Environment

1 10 Dave Lacey

XMOS - Software ToolsTechnical Director



T E C H N I C A L A RT I C L E

state of the processor running the software. Other toolslook at the external state of the system e.g. the state of connected hardware or the microprocessor ports.

In terms of function, inspection tools let us inspect thestate of the system at a particular point in its execution.Instrumentation tools add extra output and tracing to

your application to give us more information about whatis going on at runtime. Finally, analysis tools try andanalyze part of the system as it is running.

The table in Figure 1 shows some of the popular tools atour disposal categorized into their scope and function.

It may be a large generalization but if we asked a generalpurpose software engineer what the main debuggingtools are, they are likely to say print statements (orlogging) and step-by-step debuggers. However, if weasked an embedded engineer they are more likely to say

scopes, debug LEDs and logic analyzers.To understand this difference of viewpoint it is worthunderstanding what happens in an embeddedenvironment when a step-by-step debugger (like GNUGDB) is used.

The embedded system will usually be connected to thePC via a hardware connector. Nowadays this is often aconnector that implements a JTAG connection (thoughthis is not necessarily the case). This connection controlsexecution of the program. When we want to examinethe state (by either breaking into the program or hittinga predefined breakpoint) the connection will stop theexecution of the program and allow us to look at the stateof the software: memory, registers etc.

Now we have hit the problem for embedded, real-timedevelopment: the execution of the program has stopped,

which can be a big problem for a real-time program. All inputs during this suspended state will be missedresulting in, for example, missed packets on incomingbus interfaces. Also, any timers in the code risk gettingout of sync with the external world. The upshot is thatsuspending the processor for many real-time systemsmeans that the system is broken from then on so weonly get one shot at stopping and having a look around.This is not ideal. We are in the same position as thehapless bank robber in the quote at the top of this article we cannot get the system to freeze and do what we

want.

Figure 1: Debugging tools

Figure 2

Internal

State Inspection

Instrumentation

Analysis

Step-by-step debuggers

Logging, Tracing, Debug LEDs, Print, Statements

Memory analyzer

Logic Analyzer

Scope, Logic Analyzer

External




So if using a debugger to stop execution and inspect thestate is no good then we are left with instrumentation andanalysis as available methods for debugging a runningsystem. In terms of instrumentation it often seems thecase that embedded programmers prefer LEDs to printstatements (as a recent EEWEB blog article shows fora case in point). The reasons for this are probably thatcode to flash LEDs takes up less memory than printstatements, they are probably easier to setup and themost important point may be that a flashing LED is easy for the developer to relate to the timing of other parts of the system. A print statement will go through a bufferinglayer before getting to the user so the relationshipbetween the information we are seeing and real-timesystem events is lost.

When it comes to analysis tools, scopes and logicanalyzers leave the developer well served in terms of functionality. They provide tools to monitor, relate andanalyze signals in the system to really understand whatis going on. They also let us analyze events in the timedomain.

At XMOS we felt there was a gap though: we havesophisticated analysis tools for external parts of thesystem but only quite crude instrumentation for internalparts (print statements, LEDs). So we developed XScope. This is a system inspired by scopes for the analysis

of real-time behavior of external properties but lets usanalysis internal state values. The way it works is by thedeveloper adding instrumentation calls to the programto trace the values of variables. At run-time, these callsexecute a very low overhead routine to send the valuesover the high speed interconnect built into our chip.These values get picked up from the interconnect by thedebug adapter and sent over USB to a PC. Additionally,

when each value is taken, a timestamp is also takenso the values can be related to each other in the timedomain.

Once the values reach the PC, they are displayed on

screen using a GUI that mimics a scope:

This way the user gets all the analysis and time visualization of a scope but for values within the software.

We think that XScope is a great addition to the debuggersarmoury. It is part of our free tools offering and you cancheck it out at http://www.xmos.com .

References1. http://en.wikipedia.org/wiki/Joint_Test_Action_Group

2. http://www.eeweb.com/blog/paul_clarke/the-most-powerfully-debugging-tool-ever-the-led

3. http://www.xmos.com/published/xscope-application-note

About the AuthorDr David Lacey works as Technical Director of SoftwareTools at XMOS Ltd. With over ten years of research anddevelopment in programming tools and compilationtechnology he now works on the development tools for

XMOS devices. As well as tools development he has worked on application development for parallel andembedded microprocessors including work in areassuch as math libraries, networking, financial simulationand audio processing.
http://www.xmos.com/http://en.wikipedia.org/wiki/Joint_Test_Action_Grouphttp://www.eeweb.com/blog/paul_clarke/the-most-powerfully-debugging-tool-ever-the-ledhttp://www.eeweb.com/blog/paul_clarke/the-most-powerfully-debugging-tool-ever-the-ledhttp://www.xmos.com/published/xscope-application-notehttp://www.xmos.com/published/xscope-application-notehttp://www.xmos.com/published/xscope-application-notehttp://www.xmos.com/published/xscope-application-notehttp://www.eeweb.com/blog/paul_clarke/the-most-powerfully-debugging-tool-ever-the-ledhttp://www.eeweb.com/blog/paul_clarke/the-most-powerfully-debugging-tool-ever-the-ledhttp://en.wikipedia.org/wiki/Joint_Test_Action_Grouphttp://www.xmos.com/


14/19

1.8V to 3.3V, Micr o -Pow er, 15kV ESD, +1 25C, SlewRat e Limit e d, RS -4 85/RS-4 22 T ransc eiv ersISL32600E, ISL32601E, ISL32602E , ISL32603EThe Intersil ISL32600E, ISL32601E, ISL32602E andISL32603E are 15kV IEC61000 ESD protected, micro power,wide supply range transceivers for differential communication.The ISL32600E and ISL32601E operate with V CC 2.7V andhave maximum supply currents as low as 100A with both thetransmitter (Tx) and receiver (Rx) enabled. The ISL32602E andISL32603E operate with supply voltages as low as 1.8V. Thesetransceivers have very low bus currents, so they present lessthan a 1/8 unit load to the bus. This allows more than 256transmitters on the network, without violating the RS-485specifications 32 unit load maximum.

Rx inputs feature symmetrical switching thresholds, and up to65mV of hysteresis, to improve noise immunity and to reduce

duty cycle distortion in the presence of slow moving inputsignals. The Rx input common mode range is the full -7V to+12V RS-485 range for supply voltages 3V.

Hot Plug circuitry ensures that the Tx and Rx outputs remain ina high impedance state while the power supply stabilizes.

This transceiver family utilizes slew rate limited drivers, whichreduce EMI, and minimize reflections from improperly terminatedtransmission lines, or unterminated stubs in multidrop andmultipoint applications.

The ISL32600E and ISL32602E are configured for full duplex(separate Rx input and Tx output pins) applications. The halfduplex versions multiplex the Rx inputs and Tx outputs to allow

transceivers with output disable functions in 8 Ld packages.

Features Single 1.8V, 3V, or 3.3V Supply

Low Supply Currents . . . . . . . ISL32601E, 100A (Max) @ 3V. . . . . . ISL32603E, 150A (Max) @ 1.8V

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IEC61000 ESD Protection on RS-485 I/O Pins . . . . . . 15kV

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Symmetrical Switching Thre sholds for Less Duty CycleDistortion

Up to 65mV Hysteresis for Improved Noise Immunity

Data Rates from 128kbps to 460kbps

Specified for +125C Operation

1/8 Unit Load Allows up to 256 Devices on the Bus

-7V to +12V Common Mode Input/Output Voltage Range(VCC 3V)

Half and Full Duplex Pinouts; Three State Rx and Tx Outputs

5V Tolerant Logic Inputs

Tiny MSOP Packages Consume 50% Less Board Space

Applications Differential Sensor Interfaces

Process Control Networks Security Camera Networks

Building Environmental Control/Lighting Systems

FIGURE 1. ISL32600E AND ISL32601E HAVE A 9.6kbpsOPERATING I CC LOWER THAN THE STATIC I CC OFMANY EXISTING 3V TRANSCEIVERS

SUPPLY VOLTAGE (V)

I C C

( A )

2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.610

100

1m

25C, R D = , C D = 50pFDE = V CC , RE = GND

ISL3260XE STATIC

ISL3260XE DYNAMIC (9.6kbps)

ISL3172E STATIC

ISL3172E DYNAMIC (9.6kbps)

FIGURE 2. ISL32602E AND ISL32603E WITH V CC = 1.8V REDUCEOPERATING I CC BY A FACTOR OF 25 TO 40,COMPARED WITH I CC AT V CC = 3.3V

SUPPLY VOLTAGE (V)

I C C

( A )

100

1m

10m

1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6

DE = V CC , RE = GND

STATIC

DYNAMIC (128kbps)

DYNAMIC (256kbps)

25C, R D = , C D = 50pF

June 22, 2012

FN7967.0

Get the Datasheet and Order Samples

http://www.intersil.com

Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012All Rights Reserved. All other trademarks mentioned ar e the property of their respective owners.
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For Those About

to Clock,We

SaluteYou Billie Johnson Physical Design Engineer

Introduction As a quick review, clock signals direct a circuits performancein digital design. As they alternate between high and low states, logic will switch on the rising edge, falling edge or bothedges in an application. With thousands of instances running off of a given clock domain, it is necessary to insert a tree of buffering toadequately drive the logic. Clock trees have delay, skew, maximum power,and signal integrity requirements that the layout engineer must meet.

Before layout, ideal clocks are used for synthesis and timing constraints. Theconstraints clock definitions may appear on top-level pads or pins of a block; on theoutput of a macro such as a DLL (Delay-locked loop) or PLL (Phase-locked loop); oras a generated clock on a dividing register. These clock definitions may or may notbe where the layout engineer needs to define clock roots to attain optimal latencies,balancing skew across various modes of operation.

ON Semiconductor




Hierarchical ApproachesConventional CTS is executed at the top-level with a top-down methodology that attempts to balance all the flopsat one pass. A bottom-up approach or hierarchicalCTS is becoming increasingly popular due to inherenthierarchy in designs as well as better results attainable

with this methodology. Clock trees are inserted atlower levels first and then in subsequent steps movingup toward the top level. The hierarchical descriptionencompasses both soft and firm modules within a

design.

A firm or hardened block, including its clock trees, isbuilt independently from the top-level design and theninstantiated at a point later in the top-level implementation.Space is often set aside for it and termed a black boxregion. Engineers may employ this approach to facilitateparallel efforts among different portions of a design,to improve software runtimes, to ensure completereplication for identical logic used more than once, andto better allow for last minute design changes in specificpieces of a design without wreaking havoc on the entirechip. Top level clocks are connected to the individualblocks without being able to see the circuitry inside.

Within the Cadence digital layout tool set, a macromodel can be defined for the clock trees of each blockrepresenting the min and max trees along with the inputcapacitance. When the top level is built, the tool knowsexactly what lies downstream and will take into accountlatencies and skews at each block boundary.

There are cases where a design my not contain a firmblock but rather lower-level logic where clocks havebeen inserted. A macro model can be generated anddefined so those trees will remain undisturbed and CTS

will go right up to a defined port or pin, again accountingfor the delay data downstream to help with its balancingor other directives for synthesis.

Accurate macro models are great for clock balancing butengineers can also use them to implement useful skew to meet power requirements, allow for time borrowing or

force a desired phase offset for high speed interfaces.

Low Power Considerations As design sizes continue to increase, addressing powerdissipation is paramount. There are a host of tacticsto tackle a chips power during clock insertion andeveryone including the front end designer, the layoutengineer and library developers should have a hand in it.

Previous best practices include applying overly pessimistic timing constraints to build in margin,implementing fast trees with high-drive buffers andensuring clocks have as little skew as possible. Thesecan all increase the chips power dissipation, soindustry is doing almost an about face when includingpower as a CTS variable. Realistic constraints and anassortment of buffer drive strengths in less balancedtrees are recommended for lower power. Fortunately,layout software has become more power-aware toaccommodate this change in methodology, so clock tree

Conventional CTS Hierarchical CTS

A

CLK

B

C




insertion can be aptly directed. The front end designercan also address potential power issues with the clockarchitecture.

Clock gating is a design technique which reducesdynamic power by disabling the clocks to registersintended to be inactive. Gating logic is added intotrees so the sheer magnitude of registers switchingstates can be reduced thus reducing power dissipation.This isnt a new concept, but gating is becoming moreprevalent across blocks in a given chip. Part of the CTSmethodology may now also involve focused handling of the enable signals to specific branches of trees.

When gating does not help achieve quite enough powersavings, designers are now stitching blocks together

with their own separate power domainseither at thesame or lower voltages than the heart of the design.Many libraries now include three types of cells to handleseparate power domains: an isolation cell, a level shifter,and a level shifting isolation cell.

These cells can function as a regular buffer cell so thatclocks can be inserted and purposefully balanced orskewed across domains. A separate enable input can

control the isolation cells so entire domains can be off oron depending on desired operation. A level shifter celldoes exactly as its name implies shifting signal voltagesup or down appropriately, and the third in that list canperform both functions.

Smaller Geometries Another spectacle in the layout flow that has emergedin sub-90nm technologies is centered acutely on CTS.

Weve been driven by the idea of balancing clocks in aneffort to ensure that real or propagated clocks will matchthe ideal clock values used in pre-layout synthesis. Theintroduction of Multi-Corner Multi-Mode (MCMM) CTStechnology helped minimize intra- and inter-cornerskew and insertion delays in a single run by addressingprocess variations across corners, but many chipsended up with excessive switching power or the pre-and post-layout timing diverged drastically after clocks

were inserted

Power handling strategies were discussed above, buthow can the pre- and post-CTS timing discrepanciesbe addressed? The diagram below illustrates a typicalphysical design flow for 180nm technologies and larger.Many iterations of CTS have become necessary dueto gating, muxing, clock generating registers, complex scan chains, and OCV (on-chip variation).

The Cadence suite of layout tools offers a new technology called Clock Concurrent Optimization (ccopt). I admit. Ilove a good push-button flow, but like many tools ccopt

ClkClk

Enable

Enable

In

In

PropagatedClocks

IdealClocks

Post-routeOptimization

Routing

Post-CTSOptimization

CTS

Optimization

Floorplanning/Placement

Synthesis

Build balanced clocktrees to match ideal

and propagated clocks

Many iterations due togating, generators, OCV,multi-corner, multi-mode

PropagatedClocks

IdealClocks

Post-routeOptimization

Routing

ClockConcurrent

Optimization

Floorplanning/Placement

Synthesis

Build clocks ANDoptimize simultaneously




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requires a foundation of knowledge about the designsclock structure, modes of operation, power requirementsand how the ccopt engine will incorporate all of them. Thefollowing diagram illustrates the advanced layout flow

which combines CTS and the subsequent optimizationinto one step.

The ccopt software handles clock gating on top of whatthe design may already contain, cloning, decloning, andintelligently moving gates. It also adheres to multiplecorners and operation modes and can implement on-the-fly useful skew for timing and power goals. Its becomingeasier to break two things while fixing one in the deepersub-micron design world, so the key word concurrentin this tool is notable and necessary.

Conclusion Any engineering endeavor is a juggling act. Clock treesynthesis juggles timing across modes and corners,chip architecture, power, signal integrity, and on-chip

variation. Manufacturability and time-to-market alsoforce designers to shoot for more than just effective clocktrees but ones that will rock.

ReferencesTeng, Chin-Chi and Wei-Jin Dai. Clock Tree SynthesisFor a Hierarchically Partitioned IC Layout. U.S. Patent6,751,786, issued June 15, 2004.

Paul Cunningham and Steev Wilcox, Clock ConcurrentOptimization: Rethinking Timing Optimization to TargetClocks an Logic at the Same Time

About the AuthorBillie Johnson is a Physical Design Engineer at ONSemiconductor. Her work experience spans test, design,technical marketing and layout, and she holds a B.S. inEngineering and an MBA from Idaho State University inPocatello, Idaho. She has participated in numerous K-12

math and engineering outreach programs throughout hercareer including MATHCOUNTS ,FIRSTLEGOLeague (FLL) , Wind for Schools and Introduce a Girlto Engineering Day.
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