1

Problem 10.1

This problem explores in more detail the characteristics of the constant-gm reference. Refer to Figure 10.3.

Rather than choosing m=4, consider simply making m very large. In the limit, the transconductance approaches a value that is twice what is obtain when m=4. Show this formally by deriving an expression for the transconductance of M1 if the M2 is S times wide as M1. To simply the derivation, neglect body effect and assume that the PMOS mirror is an ideal 1:1 mirror.

IREFN

Start-upNetwork

M1 M2

R2

IREFP

VDD

Figure 10.13 Basic constant-gm reference

Solution:

M4 M3

M2M1

IREF Iout

(W/L)P(W/L)P

(W/L)N S(W/L)N

RS

(a) From current mirror M1-M2, we have VGS1=VGS2+IoutRS and assume Vth1=Vth2,

where 21112

1thGSoxnREF VVL

WCI

and 22 21

12out n ox GS th

S WI C V VL

1 1 2 2

1 1

22 outREFGS th GS out S th out S

n ox n ox

IIV V V I R V I RW WC CL L

S

2

1 2

1 1

22 outREFth th out S

n ox n ox

IIV V I RWC

LSW C

L

1 1

22 outREFout S

n ox n ox

II I RW WC CL L

S

(1)

(b) From current mirror M3-M4, we have VGS3=VGS4 and assume Vth3=Vth4, where

23332

1thGSoxpout VVL

WCI

and 24412

1thGSoxpREF VVL

WCI

3

22

3

3322

LWC

IVV

LWC

IVVoxp

REFthGS

oxp

outthGS

33

22

LWC

I

LWC

I

oxp

REF

oxp

out

REFout II (2) Substitution of Eq.(2) into Eq.(1), we have

1 1

2 2out outout S

n ox n ox

I I I RW WC CL L

S

1

2 11out out Sn ox

I I RW SCL

1

2 11 out Sn ox

SI R

WCL

3

2

2

1

2 1 11outS

n oxS

IW RCL

As expected, the current is independent of the supply voltage (but still a function

of process and temperature)

21

2

21

2

21

2 11

4 12 1

m

n ox outS

n ox outS

g

WC IL R

WC IL SR

S

2

21 2

14 1

mS

Sg

R

1

12 1

mS

Sg

R

Case 1: S=4, we have

1

1 12 1 2 14 12m

S S S

gR R R

Case 2: S, we have

1

12 12lim mS

S S

Sg

R R

The assumption Vth1=Vth2 introduces some error in the foregoing calculation because of the sources of M1 and M2 are at difference voltage.

The transconductance of M1 is determined geometric ratio only, independent of power-supply voltage, process parameter, temperature, or any other parameters with large variability.

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The constant gm-circuit exhibits little supply dependence if channel-length

modulation is negligible. For this reason, relatively long channels are used for all of the transistors in the circuit.

Problem 10.2 In the improved constant-gm reference of Figure 10.14, investigate the effect of

PMOS mirror error caused nonzero output conduction. Model the PMOS devices as square law; assume that they are ideal except for a channel-length modulation of 0.1V-1. Derive a general expression for the transconductance of M1, no longer assuming that M3s Vg, precisely equals the V1 of M1.

M2

R2

IREFP

+_

IREFN

Start-upNetwork

M1 M3

Ibias3

Figure 10.14 Improved constant-gm reference Solution:

M2

R2

IREFP

+_

IREFN

Start-upNetwork

M1 M3

Ibias3

Figure 10.14 Improved constant-gm reference

VGS1VGS3(W/L)1

S(W/L)1

Solution: Let Ibias3=IREFN=IREFP

5

1 3 2GS GSV V I R

1 3 2 2

1 3

2 2GS th GS th

n ox n ox

I IV V V I R V I RW WC CL L

2

1 1

2 2th th

n ox n ox

I IVS

V I RW WC CL L

2

1 1

2 2

n ox n ox

I I I RW WC CL

SL

(1)

2

1

2 11n ox

I I RW SCL

2

1

2 11n ox

I RW SCL

2

22

1

2 1 11n ox

IW R SCL

As expected, the current is independent of the supply voltage (but still a function

of process and temperature)

21

2

21 2

2

21 2

2 11

4 12 1

m

n ox

n ox

g

WC IL R S

WC IL R S

2

21 2

2

14 1

m

Sg

R

6

12

12 1

m

Sg

R

The assumption Vth1=Vth2 introduces some error in the foregoing calculation

because of the sources of M1 and M2 are at difference voltage.

The transconductance of M1 is determined geometric ratio only, independent of power-supply voltage, process parameter, temperature, or any other parameters with large variability.

The constant gm-circuit exhibits little supply dependence if channel-length

modulation is negligible. For this reason, relatively long channels are used for all of the transistors in the circuit.

7

Problem 10.3 Using the simple circuit of the first problem, select device sizes and resistor

value to produce an output current sink of 250uA and a transconductance of 1mS at 300K. Use the level-3 device parameters from Chapter 5 and simulate with SPICE to verify that the design works as desired.

Problem 10.4 The equations for the CMOS-compatible bandgap reference do not take finite

p-n-p into account. Unfortunately, typical values for of such transistors are often below 10. Re-derive the expression for the output voltage including .

Problem 10.5 In this problem, we consider the settling behavior of a nonideal voltage

reference in response to a transient disturbance. Consider the popular circuit shown in Figure 10.15. Assume that each transistor is 10um wide and that VDD is 3V. Use the level-3 device model given in Chapter 5.

(a) Choose Iref to make the output voltage 1V. (b) What is the low-frequency incremental output resistance (c) Now consider what happen if the reference voltage must drive a total load of

3 pF and if a disturbance happens to bump the output voltage to 1.5V in 1ns (e.g. with a fast-acting current source). Calculate the settling time to 1% of the original value of 1V (you may neglect body effect in your hand calculations) and verify your answer with SPICE. Explain discrepancy quantitatively.

M2

M1

VDD

VREF

Figure 10.15 Vgs-based voltage reference

Solution: Problem 10.6

8

In low-voltage circuits, it becomes difficult or impractical to use ordinary cascade structures to increase the output resistance of current sources. Alternative cascading techniques can be used to reduce the voltage required, however. An example is sketched in Figure 10.16.

M1 M4

M2

M5

M3

Iout

Figure 10.16 Low-headroom cascode

VBIAS

In this circuit, M1 establishes a bias voltage for the gates of M4 and M5. A

typical rule thumb is to make M1 about 1/4 the width of all the other transistors. However, one can place the design of this circuit on a more rational basis. If we call S the ratio W/L, assume that S2=S3=n2S4=n2S5=S, where n>1.

Assume zero output conductance in saturation and neglect body effect. Derive explicitly the condition on S1 in terms of S and n so that M2 and M3 are biased on edge of saturation. You may assume square-law behavior.

Solution:

Ibias

W/[Ln2]W[/L(n+1)2]

W/L W/L

M5M4

M3M2

M1

Iout=Iin Ibias

W/L

Iout=Iin

W/L

Ibias

M5M4

M3M2

M1

Ibias

W[/L(n+1)2]W/[Ln2] W/[Ln2] W/[Ln2]

The reason for including M4 is to lower the drain-source voltage (Vds2) of

M2 so that it is matched to the drain-source voltage (Vds3) of M3.

1 5 2

2 21 22

1 2

1 12 21

1 1

D D D

n ox GS th n ox GS th

GS th GS th eff

I I I

W WLC V V C V VLn

V V n V V n V

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The voltage at the gate of M5

5 1G GSV V The minimum drain voltage of M5 must satisfies VD5VG5-Vth

5 5 1 1D G th GS th effV V V V V n V In the ideal circuit design in the above Figure, the transistors M2 and M4 are

biased exactly at the transition point between the saturation and non-saturation regions. The analysis has neglected the body effect, so threshold voltages will not be exactly equal. In an actual circuit design, therefore, the size of M1 will be made slightly smaller to ensure transistors are biased in the saturation region. (Perhaps, the size of M2 is W/5L).

Problem 10.7 Repeat the previous problem for short-channel devices, expressing your answer

in part in terms of Esat. Note in particular that short-channel effects are helpful here because the saturation voltage diminishes, allowing operation at lower supply voltage.

Solution: Problem 10.8 Another low-headroom current source is shown in Figure 10.17. Assume for

simplicity that all widths are equal. Determine an expression for R that guarantees that both M1 and M2 are in saturation. Assume long-channel behavior, and neglect body effect and channel-length modulation.

10

R

IREF

M2

M1

M4

M3

Iout

Figure 10.17 Alternative low-headroom cascode current source

Solution: Question: How to get a High-Swing current mirror?

Answer: Let the gate voltage of M4 is Vth+2Veff Add a dc level shift Vth between the gates of M3 and M4.

M2M1

IREF IOUTROUT

VOUT

M4M3

+Vth+Veff-

+Veff-

+Vth+Veff-

+Veff-

IOUT

VOUT

VMIN

2Veff

2Vth+2VeffVth

Importance: The gate voltae of M4 is Vth+2Veff

Find VG3 VG3=VGS1+VGS3=2(Vth+Veff) Find VG4 VG4=VG3-Vth=2(Vth+Veff)-Vth=Vth+2Veff Find VDS2 VDS2=VG4-VGS4= (Vth+2Veff)-(Vth+Veff)=Veff Find minimumVDS4 The minimum drain-source VDS voltage that keeps M4 at the active region is Veff

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VDS4 V eff Find minimum VOUT

VDS4=VDS2+VDS4 (V eff)+Veff=2Veff If the gate voltage of M4 is Vth+2Veff , then you can get the high-swing current mirror.

Self-Biased high-swing cascode current source

M2M 4

M 3 M 1

R

IREF

VOUT

+VT+VON-

VT+VON

+VON-

VT+2VONiOUT

Problem 10.9 A variation on the constant-gm bias cell avoids error due to back-gate bias (body

effect) by forcing the source terminals of both NMOS devices to be at the same potential; see Figure 10.18. Show that the output current is determined only by transistor geometry and resistor value. As before, ignore body effect and assume zero output conductance and identical transistors (except for M4), which is S times as wide as the others). Show that the transconductance of M5 depends only on geometry and the reference resistor R.

M1 M2

M3 M4

M5

Iout

Figure 10.18. Alternative constant-gm reference

R

W/L S(W/L)

12

Solution: Case 1: Assume the gain of opamp is infinite and M3 and M4 are operated in the

sub-threshold region, we have V+=V-

exp 1 exp

exp

GS th DSD t

T T

GS thD t

T

V V VWI IL nV V

V VWI IL nV

Paul Gray pp.67 Eq.(1.252)

4 lnGS th Tt

IV V nVWS IL

4 lnGS th Tt

IV V nVW IL

4 3GS GSI R V V

ln lnth T th Tt t

I II R V nV V nVW WS I IL L

ln ln lnT T Tt t t

I I II R nV nV nVW W WS I I S IL L L

lnt

T

t

IW ILI R nV IWS IL

lnTnV SIR

,where VT is the thermal voltage Warning: n is dependent of process and VT also is dependent on

temperature. Case 2: Assume the gain of opamp is infinite and M3 and M4 are operated in the

saturation region, we have V+=V-

13

4 3GS GSI R V V

2 2th th

n ox n ox

I II R V VW WC CL L

S

2 2

n ox n ox

I II RW W

LSC C

L

2 2

n ox n ox

I II RW WC CL L

S

2 11n ox

II RW SCL

2 11n ox

I RW SCL

2

2 2 11n ox

I RW SCL

22 2 11

n ox

I RW SCL

2

2

2 11n ox

W SCLIR

2

2

12 1

n ox

SIWC RL

Warning: n oxC is dependent on process. Problem 10.10

(a) In the circuit of the previous problem, does the polarity of the op-amp matter? Explain qualitatively why it most certainly does, and how it behaves if the

14

polarity is incorrect. (b) To answer (a) most quantitatively, derive an explicit expression for the

loop transmission of the circuit by breaking the loop at the output of the op-amp, driving the common-gate connection of M1 and M2, and observing what comes back from the op-amp output. Watch your signs?

Problem 10.11 Self-biased circuits abound in this chapter, and we have alluded to the necessity

of start-up circuits without actually showing any specific example. Consider the bandgap reference circuit of Figure 10.19 as an example. Assume that the core of the bandgap has 100uA of current flowing in each branch.

Q1

R1=6.07K

Q2

R2=6.7K

M1

Iout

M4M3

M2M9

M6M7

M8 M5

unCox=100uA/V2

upCox=40uA/V2VtN=0.6VVtp=0.9VVBE1=0.713VVBE2=0.650V

Figure 10.19 CMOS bandgap reference with start-up circuit example

Solution:

15

Q1

R1=6.07K

Q2

R2=6.7K

M1

Iout

M4M3

M2M9

M6M7

M8 M5

Step 1

Q1

R1=6.07K

Q2

R2=6.7K

M1

Iout

M4M3

M2M9

M6M7

M8 M5

Step 2

Q1

R1=6.07K

Q2

R2=6.7K

M1

Iout

M4M3

M2M9

M6M7

M8 M5

Step 3

Q1

R1=6.07K

Q2

R2=6.7K

M1

Iout

M4M3

M2M9

M6M7

M8 M5

Step 4

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Problem 10.12 please visit the following website http://www.eetop.cn/bbs/thread-189326-1-1.html