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EEM 334 Digital Systems II

Outline

•  Finite State Machine (FSM) Overview •  Algorithmic State Machine (ASM) •  FSMs in VHDL •  State Assignment •  FSM Design Examples

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Finite State Machine (FSM) Overview

Synchronous FSM

•  An FSM is specified by five entities: – Symbolic states –  Input signals – Output signals – Next state function – Output function

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Synchronous FSM

•  FSM transits from one state to another •  Transition is controlled by the triggering

edge of a global clock signal •  FSM can have both Meally and Moore

outputs

State Diagram

•  State diagram: A set of nodes •  Node

– A unique state of the FSM – A unique symbolic name (S0)

•  Arc – Transition from one state to another – Transition condition (logic expression)

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State Diagram

•  Moore output •  Mealy output •  List only the output signals that are

activated/asserted –  signal_name <= asserted value – Asserted signal is assumed to be logic ‘1’

•  Unlisted signal: Default/unasserted value

State Diagram Example

•  Controller between a processor and a memory chip

•  Processor commands –  mem (memory access) –  rw (read/write’) –  burst (4 consecutive read)

•  Memory chip control signals –  oe (output enable for read) –  we (write enable for write)

•  Artificial mealy output signal –  we_me

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State Diagram Example

•  mem’:no memory operation is required

•  mem.rw: a memory read operation is required

•  mem.rw’: a memory write operation is required

Algorithmic State Machine (ASM)

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ASM Chart

•  An alternative method for representing an FSM

•  ASM ≡ State diagram (information content) – ASMs are more descriptive – ASMs are for complex algorithms – ASMs can be easily converted to VHDL code

•  ASM can be converted to a state diagram and vice versa

•  A network of ASM blocks

ASM Block

•  One state box •  Optional network of decision boxes •  Optional conditional output boxes

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ASM Example - 1

ASM Example - 2

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ASM Example - 3

ASM Example - 4

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ASM Example - 5

ASM Errors

•  One unique exit path from the block per input combination

•  If a=1 and b=1, two exit paths exist

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ASM Errors

•  One unique exit path from the block per input combination

•  If a=0, there is no exit path

ASM Errors

•  Exit path of an ASM block must always lead to a state box

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FSMs in VHDL

Memory Controller FSM

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Multi-segment Coding

Memory Controller FSM

•  VHDL enumeration data type:

type type_name is (list of all possible values);

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State Register

Next State Logic

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Next State Logic

Moore Output Logic

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Mealy Output Logic

Two-segment Memory Controller FSM

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Next State Logic

Next State Logic

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Synchronous FSM Initialization

State Assignment

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Overview •  Binary assignment

– Assign states wrt a binary sequence – Minimal number of bits,

•  Gray assignment – Assign states wrt a Gray code sequence – Minimal number of bits

•  One-hot assignment – Assign one bit for each state – FSM with n states, n-bit register

•  Almost one-hot assignment – One-hot except that all zero is also included

Overview

•  One-hot and almost one-hot need more register bits

•  They reduce the circuit size of next state and output logic

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Manual State Assignment

•  Implicit assignment –  IEEE 1076.6 RTL synthesis standard defines an

attribute named enum_encoding – Encoding the values of enumaration data type – No effect on the semantics of VHDL code – Mapping performed during the synthesis – Preferred method for its ease of maintanence

Manual State Assignment

•  Explicit assignment – Alias for binary representation

•  Need to modify the next state and output logic (state_reg is of type std_logic_vector)

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Unused States •  Memory controller example (Six states)

– Binary assignment: 3 bits, 2 unused states – One-hot: 6 bits, 2^6-6= 58 unused states

•  What if an FSM reaches an unused state –  Ignore the case since the error will never hapen – The system can never recover since there is

nothing we can do with the error •  Fault-tolerant/Fault-safe FSM

– Can recover from the unused state – Easy to include into explicit state assignment

FSM Design Examples

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Edge Detection Circuit

Edge Detection Circuit

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Edge Detection Circuit - Moore

Edge Detection Circuit - Moore

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Fixed Priority Arbiter

Fixed Priority Arbiter

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Manchester Encoding

•  0: 0-to-1 transition •  1: 1-to-0 transition

Manchester Encoding

•  v: valid input (data on the line is valid) •  d: data input

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Manchester Encoding

Manchester Encoding