eecs 498/598: nanocircuits and nanoarchitecturesweb.eecs.umich.edu/~mazum/eecs 498-a.pdf · eecs...

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Fall 2006 Prof. P. Mazumder

EECS 498/598: Nanocircuits and Nanoarchitectures

Instructor: Prof. Pinaki Mazumder

Tuesday and Thursday @ 3:00 – 4:30 p.m.

Lecture 1: Introduction to Nanoelectronics



Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5)

Lectures 2: ITRS Nanoelectronics Road Map (Sept 7)

Lecture 3: Nanodevices; Guest Lecture by Prof. Lu (Sept. 12)

Lecture 4: Overview of Photonics Device; Guest Lecture by Prof. Ku (Sept. 14)

Lectures 5: Quantum Device Modeling for Nano-CAD (Sept 19)

Lectures 6-8: RTD-Based Digital Circuit Design (Sept 21, 26, 28)

Lectures 9-12: Class Presentations (ITRS) (Sept. 30, Oct. 3, Oct. 5, Oct. 10)

Lecture 13: Cellular Nonlinear Network Nanoarchitectures (Oct 12)

Lecture 14: Quantum-Dot Based Logic and Local Computational Models (Oct 19)

Lectures 15 & 16: Molecular Electronics Circuits (Oct 24, Oct 26)

Lectures 17-21: Class Presentations (Oct. 31, Nov 2, Nov 7, Nov 9, Nov 14)

Lecture 22: Nano Tube/Nano Wire Based Digital Logic Design (Nov 16)Lectures 23 & 24: Quantum Cellular Array Based Logic Circuits (Nov 21, Nov 28)Lectures 25: Miscellaneous Topics like Photonics, Plasmonics, Quantum Computing, etc. (Nov 28)Lectures 26-29: Project Presentations (Dec 1, Dec 5, Dec 7, Dec 12)


Lecture #1

How small is Nano? (A movie)What is Nanotechnology?What is Nanoelectronics?

What are Emerging Devices?About the Course


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X1

x1 X0.1

x.01

x.001

Power of 10

A sense ofnanoscale

Fall 2006 Prof. P. Mazumder Courtesy Mark Rattner

Fall 2006 Prof. P. Mazumder Fall 2006 Prof. P. Mazumder

Definition of Nanotechnology“Working at the atomic, molecular, super-molecular levels, in the length scale approximately 1-10 nm range, in order to understand and create materials, devices and systems with fundamentally new properties and functions because of their small structure” --- Mike Roco, National Nanotechnology Initiative (NNI).

However, Intel prefers the range from 1-100 nm sothat conventional CMOS devices (< 90 nm) are part of Nanoelectronics Evolution.

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Multiple Perspectives of Roadmap for Nanoelectronics

• Intel Perspective (shrinking driven) Nano-scale CMOS, Nanowire FET, Carbon Nano Tube (CNT) FET

• Brick Wall Perspective Post CMOS Devices in post-shrinking era

• Concurrent Advancements (ITRS Roadmap)

• Evolutionary v. Revolutionary DevicesFall 2006 Prof. P. Mazumder

Intel Device Roadmap


Intel keeps startling the Nano world by inventingyet smaller CMOS FET’s


10,000 times fasterthan CMOS

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2501997

1801999

1302003

1502001

902006

602009

402012

1

1000

100

10

1

1000

100

10

Cu

Low kSOI

QMOS

Silicide, Local

interconnect

Feature SizeProduction Yr.

Del

ay x

Pow

er (

fJ/d

evic

e)

Cos

t (u

c/d

evic

e)

“No known solutions” -SIA ‘97

1 2 3

Vgs = 5

Vgs = 4

Vgs = 3

Vgs = 2

Vgs = 1

Change of Electronic Transport Mode

DARPA Si Nanoelectronics Research Vision


INTEL Model


Single Electronics

Today 2020 2040

Molecular Switch

Nanotubes

RTD

RTD

RTD

BulkCMOS

SOI

Vertical GateStructure

Source: TI, Denny Buss, ICECS2001

Brick Wall Perspective

1/Size

Brick-wall Model


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CONCURRENT ADVANCEMENTSEvolution of CMOS andRevolutionary Devices

Intel Tri-gate FET

Fall 2006 Prof. P. MazumderITRS

Concurrent Model of the Roadmap


IBM researchers use a single carbon nanotube bundle (blue) to fashion a logic circuit on a substrate patterned with three gold electrodes (yellow). By selectively removing part of a protective polymer coat (PMMA), the group is able to form the needed p-type and n-type transistors within the single nanotube bundle.

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Each cell is occupied by two electrons. There are two ground-state configurations,

corresponding to “polarizations” of +1 and –1.

P= -1 Logic 0

P= +1 Logic 1

Quantum Cellular Array (QCA)

Cell (Square) and Quantum Dot (Circle)

Outer Barriers

Inter-dot Barriers


cell 1

cell 2

cell 3

cell 5

cell 4

Majority logic of QCA is used

Quantum Cellular Array (QCA)

Quantum Dots can be configured into various types of logic blocksLike the majority gate, full adder, memory, registers, etc.

Diagram by P. Wu

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Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5)

Lectures 2: ITRS Nanoelectronics Road Map (Sept 7)

Lecture 3: Nanodevices; Guest Lecture by Prof. Lu (Sept. 12)

Lecture 4: Overview of Photonics Device; Guest Lecture by Prof. Ku (Sept. 14)

Lectures 5: Quantum Device Modeling for Nano-CAD (Sept 19)

Lectures 6-8: RTD-Based Digital Circuit Design (Sept 21, 26, 28)

Lectures 9-12: Class Presentations (ITRS) (Sept. 30, Oct. 3, Oct. 5, Oct. 10)

Lecture 13: Cellular Nonlinear Network Nanoarchitectures (Oct 12)

Lecture 14: Quantum-Dot Based Logic and Local Computational Models (Oct 19)

Lectures 15 & 16: Molecular Electronics Circuits (Oct 24, Oct 26)

Lectures 17-21: Class Presentations (Oct. 31, Nov 2, Nov 7, Nov 9, Nov 14)

Lecture 22: Nano Tube/Nano Wire Based Digital Logic Design (Nov 16)Lectures 23 & 24: Quantum Cellular Array Based Logic Circuits (Nov 21, Nov 28)Lectures 25: Miscellaneous Topics like Photonics, Plasmonics, Quantum Computing, etc. (Nov 28)Lectures 26-29: Project Presentations (Dec 1, Dec 5, Dec 7, Dec 12)


Evaluation Criteria:

1. In-class presentation (2)2. Written assignment related to presentation3. Final project To be discussed

Final ReportPresentation

Grading: Average grade: A- (undergrad)Average grade: A A- (grad)

Points Allocation: Two presentations (30%)Two assignments (20%)Final Project (50%)

(distribution is subject to change)


END OF LECTURE 1



Instructor: Prof. Pinaki Mazumder

Tuesday and Thursday @ 3:00 – 4:30 p.m.

Lecture 2: ITRS Roadmap & Nano Devices

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Nanotechnology Industry Segmentation

Nano MEMS11%

Medical/Healthcare8%

Other10%

Semiconductor17%

Information Technology20%

Hybrid Materials34%

Fall 2006 Prof. P. MazumderITRS 2005 Road Map

ITRS ROADMAP FOR EMERGINE MODELS & TECHNOLOGIES

• MEMORY ARRAYS• LOGIC CIRCUITS• ARCHITECTURES

RISK & PAYOFF; CHALLENGES & OPPORTUNITIES


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Fall 2006 Prof. P. Mazumder Fall 2006 Prof. P. MazumderPerformance Criterion (PC): 3 better, 2 comparable, 1 worse than CMOSRisk Criterion (RC): 3 Low Risk, 2 Moderate Risk, 1 High Risk

< 30 = (PC*RC)< 40<50>50

Fall 2006 Prof. P. MazumderPerformance Criteria: 3 superior to, 2 comparable with, 1 inferior to CMOSRisk Criteria: 3 Low Risk, 2 Moderate Risk, 1 High Risk

< 30 = (PC*RC)< 40<50>50


Evaluation Criteria for an Emergent Technology

Room TemperatureOperation

CMOS ArchitectureCompatibility

Performance

RTD& QD

CMOS Compatibility

Scalability

Energy Efficiency

Operational Reliability

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Performance

CNT

RTD& QD

CMOS Compatibility

Scalability

Spin FET Molecular

SET

Energy Efficiency

Operational Reliability Fall 2006 Prof. P. Mazumder


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State 0

State 1Fall 2006 Prof. P. Mazumder


Silicon Story

1825355070

100130180250350500800

1 TB(2023)

1

10

100

1000

10000

1989 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020 2023 20261.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

1.E+15DRAM1.4 Times/Year

64GB(2015)

Increasing Technology difficulty

year

1015

1014

1013

1012

1011

1010

109

108

107

106

105

(nm)

Gat

e L

en

gth

1TB(2023)

Tran

sis

tor N

um

be

r pe

r ch

ip

Neuron Number in Brain

Source: IEEE C&D Mag. 2001

Silicon Nanoelectronics — Nano-CMOS


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Number of transistors on a chip in thousands

1

1b

100,000

10,000

1,000

100

10

'70 '75 '80 '85 '90 '95 '00 '05 '15'10

processors

‘25‘20 ‘30

100b

10b

Moore’s law prediction

4004

8080

8086

8028680386

80486

PentiumPentium Pro

Pentium II

Pentium III

Pentium III Xeon

1-billion transistors

100-billion transistors

CPU with Multimedia Capability

Nanoelectronics and Gigascale Systems Lab.

Silicon Nanoelectronics — Nano-CMOS

Courtesy: P. Wu



Nanoarchitectures


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Performance

CNT

RTD& QD

CMOS Compatibility

Scalability

Spin FET Molecular

SET

Energy Efficiency

Operational Reliability

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Performance

CNT

RTD& QD

CMOS Compatibility

Scalability

Spin FET Molecular

SET

Energy Efficiency

Operational Reliability Fall 2006 Prof. P. Mazumder

Monochromatic Image Processor

nm ff

RInzmzV

21221212

coscos

),(

0.10.2

0.3

0.4

0.50.1

0.2

0.3

0.40.5

0.0

0.5

1.0

V(f

m,f

n)/

I BR

f mfn

Z-transform of a QD pair =

Connecting Resistance Defines the Mutual Voltage between a pair of QD’s

Nanoscale Nonlinear Circuit TheoryNanoscale Nonlinear Circuit Theory


Edge Detection by QDA

0 ns 2 ns1 ns

5 ns 6 ns

Gray BinaryConversion

Vertical Line Detection (VLD)

6 ns0 ns

Image Processor is being fabricated and tested under a NIRT projectFall 2006 Prof. P. Mazumder

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eecs 498/598: nanocircuits and nanoarchitecturesweb.eecs.umich.edu/~mazum/eecs 498-a.pdf · eecs...

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