eecs 270c / winter 2014prof. m. green / uc irvine equalization/compensation of transmission media...

EECS 270C / Winter 2014 Prof. M. Green / UC Irvine

Equalization/Compensation of Transmission Media

Channel(copper or fiber)

1


Optical Receiver Block Diagram

O E

LA CDREQ DMUX

≈ -18 dBm ≈ 10 mV p-p≈ 10 µA ≈ 400 mV p-p

TIA

2


Copper Cable Model

Copper Cable

Where: L is the cable length a is a cable-dependent

characteristic

4-foot cable

15-foot cable

2


Effect of Copper on Broadband Data

waveform eye diagram

3


Adaptive Analog Equalizer for Copper

Implemented in Jazz Semiconductor SiGe BiCMOS process:• 120 GHz fT npn • 0.35 µm CMOS

4


Equalizer Block Diagram

5


Analog Equalizer Concept (1)

1

C11 1 1

V1V2 V3

1

simple channel model bandpass filter combined flat response+ peaked response

Simple linear circuit (normalized to 1Hz):

-0.5

+0.5

1s

6


V1 V2

1

C11 1 1

V1V2 V3

1-0.5

+0.5

1s


7


Equalized output pulses: Rise time = voltage swing/slew rate

Rise time nearly constant over different channels!


V3

8


Feedforward Path

Vout

9


f (Hz)

Equalizer Frequency Response

Vcontrol

10


• Simulations indicate that ISI correlates strongly with FFE transition time teq.

• Optimum teq is observed to be 60 ps.

• Nonlinearities affect pulse shape, but not location of zero crossings.

teq = 75psPW = 86ps

teq = 60psPW = 100ps

2.4 2.5 2.6 2.7 2.8

t (ns)

-0.3

0

0.3

VFFEteq = 45psPW = 108ps

ISI & Transition Time

11


Slicer

Restores full logic levels Exhibits controlled transition time

12


Feedback Path

13


Transition Time Detector

DC characteristic:

Rectification & filtering done in a single stage.

Transient Characteristic:

t

(a)

(b)

(a)

(b)

ISS

CSS

VS

V+ V-

14


Integrator

15


Detector + Integrator

slopedetector

slopedetector

FromSlicer

tslicer= 60ps

FromFFEtFFE

Vcontrol

+ _0 10 20 30 40 50

60

40

0

-40

20

-20

-60

t (ns)

Vcontrol (mV)

60ps

45ps

15ps

75ps

90ps

FFE transitionTime tFFE

16


+

_Kd

Kd

Keq

tslicer teqdetector

detector

feedforwardequalizer

integrator

H(s)

Vcontrol

Keq = 1.5 ps/mV

Kd = 2.5 mV/ps

int = 75ns

System Analysis

17


Measurement Setup

Die under test

231 PRBS signalapplied to cable

EQ inputs

EQ outputs

18


Measured Eye Diagrams

4-footRU256 cable

(-5 dB atten. @ 5 GHz)

15-footRU256 cable

(-15 dB atten. @ 5 GHz)

EQ input EQ output

4.0 ps rms jitter

3.9 ps rms jitter19


Supply voltage 3.3 V

Power Dissipation 350 mW(155 mW not including output driver)

Die Size 0.81mm X 0.87mm

Output Swing 490 mV single-ended p-p

Random Jitter 4.0 ps rms (4-foot cable)3.9 ps rms (15-foot cable)

Summary of Measured Performance

Presented at ISSCC Feb. 2004

20


Equalization vs. Compensation

Equalization is accomplished by inverting the transfer function of the channel.

Compensation is accomplished only by canceling the ISI at each unit interval.

Electronic Dispersion Compensation (EDC) refers to the electronics that accomplishes compensation of copper or optical transmission media.

EDC is becoming especially critical as bit rates increase on legacy equipment (e.g., backplane, optical connectors, optical fiber).

21


Pre-Cursor/Post-Cursor ISI

T

Input pulse (no ISI):

Output pulse:

0

cursor

pre-cursor ISI post-cursor ISI

T

0

22


Feedforward Equalization (FFE)

Idea: To cancel ISI, subtract a weighted & delayed version of the pulse:

d0

d-1

output pulse:

output pulse delayed by T:

Result with 0 pre-cursor ISI:

23


Feedforward Equalization (2)

T

a1

Time domain:

Frequency domain:

+

_

24



T

a1

T T

a0 a2 an

N-tap FFE structure:

FFE can cancel both pre- and post-cursor distortion.

25



ISS

V0 V1 V2

R R

Vout +_

3-tap summing circuit:

Coefficients set by gm of each differential pair.

negative coefficient

26



Fractional spacing:

1-tap T-spaced FFE frequency response

1-tap T/2-spaced FFE frequency response

5-tap T-spaced FFE eye diagram

5-tap T/2-spaced FFE eye diagram

27


Adaptation (1)

Assume original sequence Din(k) is known.Define error signal e(k) as:

^ where Dout(k) is an appropriately delayed version of Din(k).^

Steepest Descent Algorithm:

• Algorithm moves coefficients in direction of decreasing mean-square error.• Step size µ should be made sufficiently small to guarantee convergence.• Requires knowledge of properties of mean-square error; usually not available.

step size

a1

a2

optimumsetting

28


^

^

FFE output signal:

Adaptation (2)

Least mean-square (LMS) algorithm:

both signals are available on chip.

Analog version of LMS:

29


Adaptation (3)

1. Training Sequence

A training sequence with known properties is sent through the channel + equalizer. The equalizer output is compared to the original sequence and an error signal is generated.

2. Blind Adapation

Adaptation is continually performed while system is running. Only limited properties of the signal are known. An error signal must somehow be generated without having the original sequence.

Types of adaptation:

30


Adaptation (4)

FFE

^

+_

• Slicer restores logic levels and opens eye vertically.• Bit sequences at slicer input & input are identical.• Slicer has no effect on placement of zero crossing.• Slicer can be realized using CML buffers with sufficient gain and speed.

Generation of error signal:

31


Decision Feedback Equalization (DFE)

T

a1

T T

a0 a2 an

FFE structure:

Noise applied to FFE input will be retained (perhaps filtered) at the output.

DFE structure:

T T T

b1b2bm

+- - -

32


Decision Feedback Equalization (2)

• Slicer is embedded in the structure; Dout is a digital signal.

• Delay elements are digital -- commonly realized by DFFs.• Use of slicer suppresses input noise.• Cancels post-cursor distortion only.

T T T

b1b2bm

+- -

-

33


T T T

b1b2bm

+- -

-

Decision Feedback Equalization (3)

2/3

1/3

1

1

2/3

(desired)

1-tap example:post-cursor distortion

consistent with

• Tap weights provide a “look-up table,” canceling post-cursor distortion based on last m bits of output sequence.

• DFE can sometimes “latch up” with wrong tap weights during adaptation.

34


T

a1

T T

a0 a2 an

T T T

b1b2bm

+- - -

FFE + DFE

Combined FFE and DFE can be used to cancel both pre- and post-cursor distortion with low noise.

35


Front-End Circuits for DSP-Based Receivers

from channel

Programmable Gain Amplifier (PGA):

VinPGA ADC

AGC

VC

VADout [1:n]

where

Automatic Gain Control

“Linear in dB” gain characteristic gives settling time independent of input amplitude.

ADC requires strict control over its input amplitude VA.

36


PGA Design

1. Differential Pair:

VC

+_

Vin+ Vin-

Iout- Iout+

ISS

For biasing in weak inversion:

2. Source Degeneration:

2RS

Vin+ Vin-

Iout- Iout+

3. Op-Amp with Feedback:

Vin

+_

Vout

+_

RS

RS

Rf

Rf

RS varied with constant dB per step.

37


PGA Example (1)

Realization of RS:

2 dB steps

C.-C. Hsu, J.-T. Wu, “A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier,” JSSC, Oct. 2003, pp. 1663-1670.

38


PGA Example (2)

gain of single diff. pair

where N = number of diff. pairs turned on

J. Cao, et al., “A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s links over backplane and multimode fiber,” ISSC 2009, pp. 370-371.

39

Track & Hold Circuit

The T/H circuit is comprised of two switch-capacitor stages and an amplifier which provides gain and isolation.

Dummy switches are used to cancel channel charge injection and achieve better linearity.

40

Simulation Results

T/H differential output for fin = 1.5 GHz and fs=10 GS/sec41

High-speed Comparator

High-Level Clocking:

• Improves isolation between the

input and output, reducing kickback

from output.

• Cascoding of the clock switches

reduces the Miller effect of the

input transistors.

• Reduced headroom

42

Comparator/Latch Results (1)

43

Metastable Behavior (1)

Metastable event

T/H output

Comp./Latch output

What is the probability of this error occurring?

44


R R

CtCt

v1

+

−v2

+

−

t45


Vin (analog)

Vout (digital)

1 2 3

01

10

11

000

+e-e-Vdec +Vdec

2e2Vdec

VLSB

Vdec = minimum detectable logic levele = minimum input at t = 0 so that output

level is ≥ Vdec at t = T/2Error probability:

Including comparator gain:

46


t

Recall:

For error-free operation after half-clock period:

Error probability:

47

Additional high-speed latches following the comparator/latch stage reduces probability of metastable events at the output.

Latch output

Reducing Metastability Errors

48

eecs 270c / winter 2014prof. m. green / uc irvine equalization/compensation of transmission media...

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