eece 218eece 218 microcontrollers - school of engineeringeecs.vanderbilt.edu/courses/ee218/lecture...

EECE 218EECE 218Microcontrollers

Bus systems

EECE 218 Microcontrollers 1

HCS12 External InterfaceExternal memory interface is implemented across four I/O ports (A, B, E, and K).External memory signal pins are listed in Table 14.7.Signals ADDR0ADDR15 and XADDR14XADDR19 are used to select a memory location to access and are referred yto as the address bus.DATA0DATA15 are used to carry data and hence are referred to as the data bus.When the external memory is not paged, only the lower 16 address/data pins are used.Expanded memory: 20 address bits/upto 1MByte (paged!)p y p y (p g )If expanded memory is enabled, then ADDR14 and ADDR15 are not used.


HCS12 External Interface (1 of 3)Shorthand: A0A15 are used instead of ADDR0ADDR15. D0D15 are used instead of DATA0DATA15. XA14XA19 are used instead of XADDR14XADDR19. EXPANDED

ADDRESS (upto 1MB)R/~W signal is used to indicate the direction of data transferR/ W signal is used to indicate the direction of data transfer.LSTRB signal is used to indicate whether the lower data bus (D7D0) carries valid data.In expanded narrow mode external memory data pins areIn expanded narrow mode, external memory data pins are connected to D15D8.LSTRB, R/W, and A0 interface the type of bus access that is taking placetaking place. ECS (XCS on some systems): chip select signal for external memory (not on-chip, not on the HCS12 itself))


HCS12 External Interface (2 of 3)


HCS12 External Interface (3 of 3)Aligned 16-bit access takes one E clock cycle to complete.Misaligned external 16-bit access takes two E clock cycles to complete.Mi li d i t l 16 bit t k E l k l t l tMisaligned internal 16-bit access takes one E clock cycle to complete.E clock (ECLK) is used as the timing reference for external access.The ECS signal is used as the chip select signal for external memory chips This signal can be used to latch address signals so that they stay

Table 14.8 Access type vs. bus control signals

LSTRB A0 R/W Type of access

chips. This signal can be used to latch address signals so that they stay valid throughout the whole access cycle.

LSTRB A0 R/W Type of access

10100

01010

11001

8-bit read of an even address8-bit read of an odd address8-bit write of an even address8-bit write of an odd address16 bit read of an e en address0

1

01

01

01

11

00

16-bit read of an even address16-bit read of an odd address(low/high bytes swapped)16-bit write of an even address16-bit write of an odd address(low/high bytes swapped)


(low/high bytes swapped)

Waveforms of Bus Signals (1 of 3)The waveform of a typical digital signal is shown.

tr tf

0.9VDD0.9VDD

0.1VDD0.1VDD

The rise time (tr) of a signal is the time needed for a signal to rise from 10% of the power supply voltage to

Figure 14.25 A typical digital waveform

signal to rise from 10% of the power supply voltage to 90% of the power supply voltage. The fall time (tf) of a signal is the time needed for a signal to drop from 90% of the power supply voltagesignal to drop from 90% of the power supply voltage to 10% of the power supply voltage.


Waveforms of Bus Signals (2 of 3)

Single bus signal waveform

1

00

Figure 14.26 Single signal waveform

Multiple-signal waveform

1

one or multiple signalschange value

1

0

Figure 14 27 Multiple-signal waveform


Figure 14.27 Multiple signal waveform

Waveforms of Bus Signals (3 of 3)

unknownUnknown signal

unknown(a)

(b)Floating signals Figure 14.28 Unknown signals. (a) single signal. (b) multiple signal.

signal floating

signal floating(a)


(b)

Figure 14.29 Floating signals. (a) Single signal. (b) Multiple signals.

Categories of Bus Signals

AddressD tDataControl


Bus TransactionsIncludes sending the address and receiving or sending the dataA d t ti ( l ll d d b l ) t f d tA read transaction (also called read bus cycle) transfers data from memory to either the CPU or the I/O device.A write transaction (also called write bus cycle) writes data to the memorthe memory. In a read transaction, the address is first sent down the bus to the memory, together with the appropriate control signals indicating a readindicating a read. The memory responds by placing the data on the bus and asserting a control signal to indicate that the data is valid. A d b t ti i h i Fi 14 30A read bus transaction is shown in Figure 14.30.In Figure 14.30, a read cycle takes one clock cycle to complete. If necessary, the memory system can delay the assertion of the Ready signal


assertion of the Ready signal.

End of readtransaction

Clock

Address

Data

Read

Figure 14.30 A typical bus read transaction

Ready


g yp

Terminology

Bus master A device that can generate

Address

Data

Master asserts address

Slave drives data

address and control signals during a bus transaction

Bus slave A device such as a memory

Read

Request

A device such as a memory chip that can only respond to the bus transaction

Synchronous busACK

Figure 14.31 Asynchroous read bus transaction.

A bus that uses a clock signal to synchronize bus transactions

Asynchronous busAsynchronous bus A bus that does not use a

clock signal to synchronize the bus transaction


Bus MultiplexingIt is used to minimize the number of pins used in a chip: the same pin is time-multiplexed betweenchip: the same pin is time multiplexed between different functions (e.g. address or data)Address bus and data bus are often multiplexed.pAddress signals must be stable throughout the whole bus transaction cycle In a multiplexed bus system, an external circuit must

make a copy of the address signals to make them stable through out the whole bus cycle. ( Use a latch)


The HCS12 Bus CyclesThe timing diagrams of a read and a write bus cycle are combined in Figure 14 32bus cycle are combined in Figure 14.32.Figure 14.32 shows that a bus cycle starts with the MCU driving the address signals onto g gthe address bus.The events that occur during a read cycle are ill t t d i Fi 14 33illustrated in Figure 14.33.The events that occur during a write a cycle are illustrate in Figure 14 34are illustrate in Figure 14.34.


3 41, 2

6 10165ECLK

13

11

12 1487

615

10169

5

Addr/Data

Addr/Data(read) addr

dd

data

1917 18XA19:XA14

Addr/Data(write) addr data

26

2322

24 25

20 21

ECS

2927 28

LSTRB

R/W

35 363433IPIPE0

NOACC

30 31 32


IPIPE0IPIPE1

Figure 14.32 The HCS12 Read/Write bus cycle timing diagram

Table 14.9 HCS12 expanded bus timing characteristics

Num Parameter name Symbol UnitMin Typ Max

12

Frequency of operation (E-clock)Cycle time

fot

040

25.0 nsns

-2345678

Cycle timePulse width, E lowPulse width, E highAddress delay timeAddress valid time to E rise (PWEL - tAD)Muxed address hold timeAddress hold to data valid

tcycPWELPWEH

tADtAV

tMAHtAHDS

401919-

1127

---8---

nsnsnsnsnsnsns

-------8

91011121314

Address hold to data validData hold to addressRead data setup timeRead data hold timeWrite data delay timewrite data hold timeWrite data setup time1(PWEH - tDDW)

tAHDStDHAtDSRtDHRtDDWtDHWtDSW

72

130-2

12

---7--

nsnsnsnsnsnsns

------

15161718192021

Address access time1(tcyc - tAD - tDSR)E high access time1(PWEH - tDSR)Non-multiplexed address delay timeNon-muxed address valid to E rise (PWEL-tNAD)Non-multiplexed address hold timeChip select delay timeChip select access time1 (t t t )

tACCAtACCEtNADtNAVtNAHtCSDt

196-

152-

11

--6--

16

nsnsnsnsnsnsns

------

21222324252627

Chip select access time1 (tcyc - tCSD - tDSR)Chip select hold timeChip select negated timeRead/write delay timeRead/write valid time to E rise (PWEL - tRWD)Read/write hold timeLow strobe delay time

tACCStCSHtCSNtRWDtRWVtRWHtLSD

1128-

142-

---7--7

nsnsnsnsnsnsns

-------

282930313233

yLow strobe valid time to E rise (PWEL - tLSD)Low strobe hold timeNOACC strobe delay timeNOACC valid time to E rise (PWEL - tNOD)NOACC hold timeIPIPO[1:0] delay time

[ ] l d ( )

LSDtLSVtLSHtNODtNOVtNOHtP0D

142-

1422

--7--7

nsnsnsnsnsns

------


343536

IPIPO[1:0] valid time to E rise (PWEL - tP0D)IPIPO[1:0] delay time1 (PWEL - tP1V)IPIPO[1:0] valid time to E fall

tP0VtP1DtP1V

112

11

-25-

nsnsns

Notes. 1. Affected by clock stretch: add N x tcyc where N = 0, 2, or 3, depending on the number of clock stretches.

---

1 Set R/W to read

Address the memory

Microcontroller External memory

Read Cycle1. Set R/W to read2. Place address on bus3. Assert LSTRB if address is odd4. Assert ECS and XCS if in range

Output the data

1. Decode the address2. Place data on data bus

1. Latch the data2 N t LSTRB if t d

Acquire the data

2. Negate LSTRB if asserted3. Negate ECS and XCS if asserted

Terminate the read cycle

1. Remove data from data bus and release to HI-Z


Start the next cycle

Figure 14.33 Sequence of events occurred in an HCS12 read bus cycle

1 Set R/W to write

Address the memory

Microcontroller External memoryWrite Cycle1. Set R/W to write2. Place address on bus3. Assert LSTRB if address is odd4. Assert ECS and XCS if in range5. Place data on data bus

Input the data

1. Decode the address2. Store data from data bus

1. Negate LSTRB if asserted2. Negate ECS and XCS if asserted

Terminate write data

2. Negate ECS and XCS if asserted3. Remove data from data bus

Terminate the write cycle

1 R l d t t HI Z1. Release data to HI-Z

Start the next cycle


Figure 14.34 Sequence of events occurred in an HCS12 write bus cycle

External Memory Access1. Instruction execution requires that all memory reads and writes happen

within one clock cycle. For example, just before the instructionldaa 0,X ;register A

External Memory Access6. A read or write operation starts when the clock signal, ECLK, falls (goes from

high to low). First, the 9S12s MCU drives (puts) the address onto the bus.7 It t k ti f th lt t d t bili th b7. It takes time for the voltages to appear and stabilize on the bus.8. Therefore, after the onset of the clock cycle , tEL, there is a delay, tAD, before the

address is valid and can be gotten by the external memory controller. The address is assumed to be valid by the time the chip-select signal, ECS is asserted.

9. The data transfer half of the clock cycle starts at tEH, during ECLKs transition from low to high.

10. As with the address, there is a delay between tEH and valid data appearing on10. As with the address, there is a delay between tEH and valid data appearing on the bus.

11. The delays between clock transitions and address or data stability cause the address/data cycle to be out of phase with ECLK. Since the phase shift is effectively constant the address can be made to remain stable until a short timeeffectively constant, the address can be made to remain stable until a short time after tEH. Similarly for data and tEL. Therefore the rising edge of ECLK can be used to indicate a stable address and the falling edge to indicate stable data.


Timing parameters

D Q

D flip/flop

D Q

Q

D flip-flop: latches the content of D upon a L H transition on the CLK input Q

Setup time: Data has to be stable somewhat before the CLK transition

Hold time: Data has to stay stable for some time after the CLK transition


Important Data Read Timing Parameters

1. Address setup time: time interval that AD valid before the falling edge of ECS. This parameter is t20 t5 8 ns (= 16 ns 8 ns).

2 Address hold time: amount of time that AD remain valid after the2. Address hold time: amount of time that AD remain valid after the falling edge of ECS. This parameter is t7 + TE/2 t20 ( 5 ns).

3. Read data setup time: amount of time that data is valid before the falling edge of ECLK. This parameter is t10 ( 13 ns).

4 Read data hold time: amount of time that data remains valid after the4. Read data hold time: amount of time that data remains valid after the falling edge of ECLK. This parameter is t11 ( 0 ns).

5. Address access time: the delay from the moment that address signals are valid until data is driven by memory device. This parameter is t15 (> 19 ns).

6 Write data set up time: Write data valid before the W signal goes high6. Write data set up time: Write data valid before the W signal goes high. This parameter is t14 + t26 14 ns.

7. Write data hold time: Write data stay valid after the W signal goes high. This parameter is 0 ns.

Parameters 1 and 2 are important to make sure that the address signals can be Parameters 1 and 2 are important to make sure that the address signals can be latched correctly by the address latch.

Parameters 3, 4, and 5 are required by the MCU during a read access. The actual values for parameters 6 and 7 may be lengthened depending on how

the Write signal is derived for the memory chip.


Issues Related to Adding External Memory

Memory space assignmentAddress decoder and control circuitry designAddress decoder and control circuitry designTiming verification


Memory Space AssignmentEqual size assignment The available memory space is divided into blocks of equal The available memory space is divided into blocks of equal

size. Each block is assigned to a memory device without

regarding for the actual size of each memory-mappedregarding for the actual size of each memory mapped device.

Memory space tends to be wasted using this approach because most memory-mapped peripheral chips need only abecause most memory mapped peripheral chips need only a few bytes to be assigned to their internal registers.

Demand assignment Th i th di t th i f The user assigns the memory space according to the size of memory devices.


Memory assignment example Example: Suppose a designer is assigned to design a HCS12DP256-based embedded product that requiresHCS12DP256 based embedded product that requires 256 KB of external 16-bit SRAM, 256KB of 16-bit EEPROM, and a parallel peripheral interface (PPI) that

i l f b t f dd Th lrequires only four bytes of address space. The only available SRAM to this designer is the 128K 8 SRAM chips (This chip has 128K locations with each location containing 8 bits). The only available EEPROM is the 128K 8 EEPROM chips. Suggest a workable memory space assignmentspace assignment.


Memory assignment example Solution:

Two 8-bit wide memory chips are needed to construct a 16-bit memoryTwo 8-bit wide memory chips are needed to construct a 16-bit memory module.

- Two 16-bit wide SRAM modules are needed to provide the 512 KB capacity.

- One 16-bit wide EEPROM module is needed to offer the 256KB capacity.

A possible assignment is as follows:A possible assignment is as follows:

SRAM: 0x00000~0x3FFFF ; 256KB

EEPROM: 0x40000~0x7FFFF ; 256KB

PPI: 0xBFFFC~0xBFFFF ; 4 bytes


Address Decoder Design Address decoder selects one and only one memory device to respond to the memory access request.All memory devices have control signals such as chip-enable (CE), chip-select (CS), or output-enable (OE) to control their read and write operations. Two address decoding schemes have been used:Two address-decoding schemes have been used: Full decoding Partial decoding

Address decoder design is closely related to memory spaceAddress decoder design is closely related to memory space assignment.The programmable logic devices (PLDs) make full decoding easy and flexible.yPALs are often used to implement address decoders.


Timing Verification In a read cycle, the most critical timing requirements are the data setup time and data hold time required b th i t llby the microcontroller.The address setup time and hold time requirements for the memory devices are also critical.In a write cycle, the most critical timing requirements are the write data setup time and write data hold time required by the memory device.Th dd t ti d h ld ti t l bThe address setup time and hold time must also be satisfied.For a write cycle, the write pulse width must be long

h f th it l t b f lenough for the write cycle to be successful.


eece 218eece 218 microcontrollers - school of engineeringeecs.vanderbilt.edu/courses/ee218/lecture...

Documents