ee3950 class notes chapter 12 hambley 3-12
TRANSCRIPT
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Objectives
Understand MOSFET operation.
Use the graphical load-line technique to
analyze basic FET amplifiers.Analyze bias circuits.
Use small-signal equivalent circuits to
analyze FET amplifiers.
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Objectives
Compute the performance parametersof several FET amplifier configurations.
Select a FET amplifier configuration thatis appropriate for a given applications.
Understand the basic operation of
CMOS logic gates.
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Transistors
These are threeterminal devices,
where the current orvoltage at oneterminal, the inputterminal, controls
the flow of currentbetween the tworemaining terminals.
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Transistors
Can be classified as:
FETField Effect Transistor;
Majority carrier device; Unipolar device;
BJTBipolar Junction Transistor;
Minority carrier device;
Bipolar device.
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FETs
Two primary types: MOSFET, Metal-Oxide-Semiconductor FET. Also
known as IGFETInsulated Gate FET;
JFET, Junction FET.
MOS transistors can be: n-Channel;
Enhancement mode;
Depletion mode;
p-Channel;
Enhancement mode;
Depletion mode;
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MOSFET Structure
Figure 12.1 n-channel enhancement MOSFET
showing channel length Land channel width W.
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NMOS Symbol
Figure 12.2 Circuit symbol for an enhancement-
mode n-channel MOSFET.
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Threshold VoltageVto
The value of VGSwhere the drain
current just beginsto flow.
Typical values:
0.3 to 1.0 volts.
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Operation in the Cutoff Region
Figure 12.3 For vGS< Vto, the pnjunction between
drain and body is reverse biased and iD= 0.
for
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Operation in the Triode(Ohmic) Region
Figure 12.4 For vGS> Vto, a channel of n-type material is induced in
the region under the gate. As vGSincreases, the channel becomes
thicker. For small values of vDS, iDis proportional to vDS. The device
behaves as a resistance whose value depends on vGS.
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Operation in the Triode(Ohmic) Region
or< and
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Conduction Parameter K
or where nis the mobility of the electrons in the inversion layer.
Coxis the oxide capacitance per unit area.
KP is determined by the fabrication process.
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Operation in the Saturation Region
Figure 12.5 As vDSincreases, the channel pinches
down at the drain end and iDincreases more slowly.
Finally, for vDS> vGS
Vto, iDbecomes constant.
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Operation in the Saturation Region
or> and
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NMOS Characteristic Curves
Figure 12.6 Characteristic curves for an NMOS
transistor.
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PMOS Symbol
Figure 12.8 Circuit symbol for PMOS transistor.
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PMOS Characteristic Curves
Figure 12.9Characteristic curves for a PMOS
transistor.
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MOSFET Summary
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Depletion Mode MOSFETs
n-Channel is built in.
VGSvaries from
negative values topositive values,where negativevalues of VGS
depletes the channelwhile positive valuesenhance it further.
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JFETs
Depletion-mode FET with a different structure thanthat of the MOSFET.
Not generally used for switching elements of digitalcircuits.
Used in special applications such as analog circuits
where very high input impedance is required.
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JFETs
Every p-njunction has a depletion regiondevoid of carriers, and the width of thedepletion region can be controlled by theapplied voltage across the junction.
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JFETs
Note the highestvalue of VGS.
What happens if youmake VGSpositivewith respect toground.
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Load Line Analysis
Figure 12.10 Simple NMOS amplifier circuit.
sin 2000 4
20 1k
Solve for: 0 and 0
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Load Line Analysis
Figure 12.11 Drain characteristics and load line for
the circuit of Figure 12.10.
20 1k
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Load Line Analysis
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Bias Circuits
Figure 12.13 Fixed-plus self-bias circuit.
+ and +
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Bias Circuits
Figure 12.14 Graphical solution of Equations
12.12 and 12.13.
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Exercise 12.5
Determine IDQ and VDSQfor the circuit shown inFigure 12.16. The
transistor has: KP = 50A/V2
Vto = 1V
L= 10m
W= 200m
Figure 12.16 Circuit for
Exercise 12.5.
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Solution
Compute:
A/V 0.5mA/V
+ 20V K.M+K 7VGiven:
Then:
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Solution
2
0
Substitute known values results in: 6 0
The roots are: 2V 3V (correct root)
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Solution
Therefore:
2mA
16V
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Small-Signal Equivalent Circuits
Figure 12.18 Illustration of the terms in Equation 12.15.
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FETs Small-signal Equivalent Circuit
Figure 12.19 Small-signal equivalent circuit for
FETs.
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Small-Signal Equivalent Circuits
Given:
Substituting: We get:
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Small-Signal Equivalent Circuits
Expanding expression:
2
Reducing expression:
Q-points current cancels:
2
makes last term negligible: 2 (12.20)
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Small-Signal Equivalent Circuits
Defining transconductance of the FET as: 2
Allows the current equation to be written as:
0
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Transconductance Dependencyon Q-Point
Solving for andsubstituting it into 2 :
2 Transconductance is proportional to the square rootof the Q-point drain current.
Substitute into 2 and verifythe relationship between transconductance and thewidth-to-length ratio of the FET.
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Dependence of iDon vDS
Figure 12.20 FET small-signal equivalent circuit
that accounts for the dependence of iDon vDS.
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Transconductance and DrainResistance as Partial Derivatives
=
The condition 0is equivalent to remainingconstant at the Q-point, or . Therefore we canwrite: =and
Similarly:
=and
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Transconductance and DrainResistance as Partial Derivatives
=
The condition 0is equivalent to remainingconstant at the Q-point, or . Therefore we canwrite: =and
Similarly:
=and
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Exercise 12.7
Find gm and rdfor the characteristics of shown inFigure 12.21 at the Qpoint of VGSQ= 2.5V and VDSQ
= 6V.
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Solution
= ..mA
v 3.3mSSimilarly:
=
.9.mAV 0.05mS
. 20k
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Small-Signal Equivalent Circuits
Figure 12.18 Illustration of the terms in Equation 12.15.
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Common-source Amplifier.
Figure 12.22 Common-source amplifier.
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Common-source Amplifier.
+ +
and
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Common-source Amplifier.
Figure 12.24 Circuit used to find Ro.
+
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Source Follower
Figure 12.26 Source follower.
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Source Follower
+ +
and
+
+
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Source Follower
Figure 12.28 Equivalent circuit used to find the
output resistance of the source follower..
+ +
+ +
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Common-gate Amplifier
Figure 12.29 Common-gate amplifier.
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Logic Gates
AND gate
OR Gate
Inverter
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Logic Gates
NAND Gate
NOR Gate
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CMOS Inverter
Figure 12.31 CMOS inverter.
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Two-input CMOS NAND Gate
Figure 12.32 Two-input CMOS NAND gate.
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Three-input CMOS NOR Gate
Figure 12.35 Three-input CMOS NOR gate.
(Answer for Exercise 12.15.)