ee321 chap04 control unit -...

EE321Computer ArchitectureChap 04: Control UnitChap. 04: Control Unit

Dr. Abdelhakim KhouasEmail : [email protected]

ab khouas@univ boumerdes [email protected] (ex. INELEC)

University M’hamed Bougara of Boumerdes

Course chapters

1. Review of Digital Design1. Review of Digital Design2. Top Level of Computer3 Central Processing Unit (CPU)3. Central Processing Unit (CPU)4. Control Unit5 M5. Memory6. Instruction Set and Addressing Modes

EE321 - Chap. 04 – Control Unit © A. Khouas1

Lecture Objectives

Understand function and design of the control unit

Micro-operationsMicro-operationsControl unit functionControl unit implementations

Hardwired implementationMicroprogrammed implementation


Lecture Outline

1. CPU Function Review 2 Micro-operations2. Micro-operations3. Control Unit4 H d i d I l t ti4. Hardwired Implementation5. Microprogrammed Control

1. Basic Concepts2. Implementation3. Microinstructions


Readings

TextbookComputer Organization and Structure,

Designing for Performance, By William Stallings, 8th edition

SectionsSectionsChapter 15, sections: 3.1 to 3.3Chapter 16, sections: 16.1


1. CPU Function Review

CPU internalCPU internal structure


1. CPU Function Review

CPU FunctionCPU FunctionWe have already seen that:

The execution of a program consists of the sequential execution of instructionsThe execution of an instruction involves the execution of a sequence of cycles: fetch, decode, q y , ,and executeEach cycle contains many smaller cycles (states)Each cycle contains many smaller cycles (states) such as: read instruction, data operation, operand save, … etc.

EE321 - Chap. 04 – Control Unit © A. Khouas

save, … etc.

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2. Micro-operation

DefinitionDefinitionMicro-operations (MO) are the atomic operations

(smaller steps) of a processor that are executed in(smaller steps) of a processor that are executed in one clock cycle

Each instruction cycle (fetch, decode, execute, y ( , , ,interrupt) is composed of a set of micro-

ti th t f d i ioperations that are performed in a precise time sequence


q

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2. Micro-operation


Constituent Elements of a Program Execution

2. Micro-operation

Examples:Examples: For all instructions

Fetch Cycle: 3 steps and 4 micro-operationst1: MAR <-- PCt2: MBR <-- memory

PC <-- PC+I (I is the instruction length)t3: IR <-- MBR

t1, t2, and t3 are time unit (i.e. one or more clock cycles)


2. Micro-operation

Micro-operations groupingMicro operations groupingTo save time, some micro-operations that do not

interfere can be executed during same time unitinterfere can be executed during same time unit, following two simple rules:The proper sequence of events must be followedThe proper sequence of events must be followed (e.g. set MAR register before writing or reading MBR)MBR)Conflicts must be avoided

should not attempt to read to and write from the sameshould not attempt to read to and write from the same register in one time unitIf internal data bus, should not use the same data bus


,

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2. Micro-operation

Micro-operations groupingp g p gFor fetch cycle, the 3rd micro-operation could have been grouped with the 4th micro-operationbeen grouped with the 4 micro operation

t1: MAR <-- PCt2: MBR < memoryt2: MBR <-- memoryt3: IR <-- MBR

PC < PC+I (I is the instruction length)PC <-- PC+I (I is the instruction length)


2. Micro-operation

Examples: Direct add operationExamples: Direct add operationADD R1, (X) ; R1 <= R1 + [X]

R1 : General purpose register used as accumulatorX : Second operand (address)[X]: content of memory location XMBR is connected to ALU

Execution Cycle:t1: MAR <-- IR (X) ( )t2: MBR <-- memoryt3: R1 <-- R1 + MBR


2. Micro-operation

Examples: Immediate operationADI R1, X ; R1 <= R1 + X

R1 : General purpose register used as accumulatorR1 : General purpose register used as accumulatorX : Second operand (immediate value)MBR is connected to ALUMBR is connected to ALU

Execution Cycle:T1 R1 R1 MBR(X)T1: R1 <-- R1 + MBR(X)


2. Micro-operation

Examples:Examples: ISZ (X) ; Increment [X] and skip the next

f [ ] h dd f hinstruction if [X]=zero, X is the address of the operand Execution Cycle:

t11: MAR ← IR(X)t2t: MBR ← Memory t33: MBR ← MBR + 1 t4: Memory ← MBR

If (MBR = 0) then (PC ← PC + 1)


( ) ( )

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2. Micro-operation

Examples:Examples: Interrupt Cycle:

t11: MBR ← PC t22: MAR ← Save_Address

PC ← Routine_Addresst33: Memory ← MBR


2. Micro-operation

Examples:Examples: Indirect Operation: ADIN A, ((X)) ; A = A + [[X]]

Indirect Cyclet11: MAR ← IR(X)t22: MBR ← memory ([X]) T3: IR(Address) ← MBR

Execute Cyclet33: MAR ← IR(X)t33: MAR IR(X)t4: MBR <-- memory ([[X]])t5: A <-- A + MBR


t5: A < A + MBR

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2. Micro-operation

START

YFetchCycle

IndirectCycleIndirect?

Yes

NNo

Execute Cycle

InterruptCycleInterrupt?

Yes

Fl h f i i l

No


Flowchart for instruction cycle

2. Micro-operation

Instruction cycle codeInstruction cycle codeWe have four cycles: fetch, indirect, execute, and i t tinterruptWe can use 2-bit register ICC (Instruction Cycle Code) to code the cycles

ICC = 00: FetchICC = 01: Indirect ICC = 10: ExecuteICC = 11: Interrupt

At he end of each cycle, ICC is set appropriately


At he end of each cycle, ICC is set appropriately

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2. Micro-operation

Fl h f i i l i ICC


Flowchart for instruction cycle using ICC

3. Control Unit

The control unit controls the execution of each f h i i lstep of the instruction cycle

The control unit of a CPU performs two tasks:The control unit of a CPU performs two tasks: 1. It causes the processor to step through a series

of MO in the proper sequence2. It generates the control signals that cause the g g

execution of each MO


3. Control Unit


Control Unit Model

3. Control Unit

Inputs:Inputs:Clock: The control unit causes one micro-operation (or a set of simultaneous micro operations) to bea set of simultaneous micro-operations) to be performed for each clock pulse. Also known as the processor cycle time, or the clock cycle timeprocessor cycle time, or the clock cycle timeIR: The code of the inst. is used to determine which micro-operations to perform during the execute cyclep p g yFlags: These are needed by the control unit to determine the status of the processor and the outcome of previous ALU operationsControl signals from control bus


3. Control Unit

Outputs:Control signals within the processor: These are twoControl signals within the processor: These are two types:

Signals that cause data movement (register to another)Signals that cause data movement (register to another)Signals that activate specific ALU functions

Control signals to control bus: These are also ofControl signals to control bus: These are also of two types:

t l i l t ( d)control signals to memory (e.g. memory read)control signals to the I/O modules


3. Control Unit

Example Control Signal Sequence: MAR <- (PC)

Control unit activates signal to open gates between PC and MAR

MBR <- (memory)Open gates between MAR and address busMemory read control signalOpen gates between data bus and MBR


3. Control Unit

Data Paths and Control signals: CPU with single accumulator


Data Paths and Control signals: CPU with single accumulatorSource: Computer Organization and Architecture, by W. Stallings

3. Control Unit

l lControl SignalsThe terminations of the control signals are labeledThe terminations of the control signals are labeled Ci and indicated by a circleThe control unit receives inputs from the clock IRThe control unit receives inputs from the clock, IR, and flagsWith h l k l th t l it d ll fWith each clock cycle, the control unit reads all of its inputs and emits a set of control signals Ci to open/close the gates bet een the diffe ent pa tsopen/close the gates between the different parts of the processor to control data transfer


3. Control Unit

Control Signals: examplesControl Signals: examplesFetch Cycle:

Micro-operation Active signals Micro-inst.t1: MAR <-- PC C3 00...00100t2: MBR <-- memory C5, RD

10...10000PC <-- PC+1

t3: IR <-- MBR C4 00...01000

RD: Read control signal to bus


g

3. Control Unit

Control Signals: examplesControl Signals: examplesInterrupt Cycle:

Micro-operation Active signals Micro-inst.t11: MBR ← PC C1 00...00001t22: MAR ← Save_Address

PC ← Routine_Addresst33: Memory ← MBR C12, WR

101...0000

WR: Write control signal to bus


g

3. Control Unit

Micro-operations for ADD AC,X instruction: 5 clock cycles.

Control signals: AC: AccumulatorX : Address

Control signals: CPU with internal data bus


Source: Computer Organization and Architecture, by W. Stallings

3. Control Unit

We have discussed the control unit in terms of its inputs output and functions For theits inputs, output, and functions. For the implementation, a wide variety of techniques have been used. Most of these fall into one of t t itwo categories:

Hardwired implementationHardwired implementationMicroprogrammed implementation


4. Hardwired Implementation


Control Unit with Decoded inputs


Control unit is viewed as a state machine circuit, and can be implemented using standard digitaland can be implemented using standard digital logic techniques

For each control signal, we derive a Boolean expression as a function of the inputs and theexpression as a function of the inputs and the current stateDecoder is used to generate unique logic signal forDecoder is used to generate unique logic signal for each opcode



Example: Let us consider a control signal C5 thatExample: Let us consider a control signal C5 that causes data to be read from the external data bus into the MBR (MBR<-- Memory)

We assume two new control signal P and Q that have the following interpretation:

PQ = 00 Fetch CyclePQ = 01 Indirect CyclePQ = 10 Execute CyclePQ = 11 Interrupt Cycle




Micro-operations and control signals


Example: The control signal C5 will be asserted during the second time unit of the fetch and interrupt cycles, p y ,so the Boolean expression of control signal C5 is:

5C PQT PQT+

If we assume C5 is also needed during the execute 2 25C PQT PQT= +

cycle of three instructions that read from memory: LDA, ADD, and AND, then C5 is given by:

2 2 25 ( )C PQT PQT PQT LDD ADD AND= + + + +



Example: Signal C4 (IR <-- MBR)Th t l i l C4 ill b t d d i thThe control signal C4 will be asserted during the third time unit of the fetch and indirect cycles, so th B l i f t l i l C4 ithe Boolean expression of control signal C4 is:

4C PQT PQT3 34C PQT PQT= +



Main advantagesMain advantagesHigh(er) speed operationSmaller implementations (component counts)

Main disadvantagesMain disadvantagesInflexible design

d f h d b h d dModifications to the design can be hard to do

Difficult to add new instructionsComplex sequencing & micro-operation logicDifficult to design and test


Difficult to design and test

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5. Microprogrammed Control

An alternative to a hardwired control unit is a microprogrammed control unit

Control unit is specified by a microprogramControl unit is specified by a microprogramMicroprogram (firmware) consists of a sequence of

i i t ti (MI)microinstructions (MI)Each MI specify a micro-operation and is very simple



ImplementationTh t l it l t t f t lThe control unit only generate a set of control

signals, each control signal is on or offIn horizontal MI, each bit represents one control signalWe put each MI in a memory with unique addressAdd to the MI an address to specify the nextAdd to the MI an address to specify the next micro-instruction, depending on conditions



Horizontal MI format




Horizontal MI formatA code is used for each action to be performedCondition branch fieldCondition branch fieldAddress of the next MI if branchN d f i i t ti d dNo need for microinstruction decoderBigger (more bits) microinstruction and control memory




Vertical MI format C diti b h fi ldCondition branch fieldAddress of the next MI if branchNeed for microinstruction decoder to generate control signals Vertical gSmaller control memory microinstruction

format





Organization of Control Memory


d f llMI is interpreted as follows:i. To execute this MI, turn on/off all the controli. To execute this MI, turn on/off all the control

signals, the resulting control signals will cause one or more micro-operations to be performedone or more micro operations to be performed

ii. If the condition indicated by the condition bits is: false execute the next microinstruction infalse, execute the next microinstruction in sequence

iii If it is t e the ne t mic oinst ction to beiii. If it is true, the next microinstruction to be executed is indicated in the address field



This decoder is only This decoder is only used for vertical microinstruction

Functioning of Microprogrammed Control Unit



The control unit functions as follow:The control unit functions as follow:To execute an instruction, the sequencing logic unit issues a READ command to the control memoryThe control word is read into the control buffer registerThe content of the control buffer register generates control signals and next address information for the sequencing logic unitThe sequencing logic unit loads a new address into the control address register based on the next-address information and the ALU flags



Next address decisionNext address decisionDepending on ALU flags and control buffer register,

one of the three following decision is made:one of the three following decision is made:1. Add 1 to control address register

Add 1 to control address registerAdd 1 to control address register2. Jump to new routine based on jump

microinstructionmicroinstructionLoad control address register with address field of control buffer registerg

3. Jump to machine instruction routineLoad control address register based on opcode in IR


Load control address register based on opcode in IR

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Summary

Micro operationMicro-operation

Control Unit FunctionControl Unit FunctionInputsO t tOutputsControl signals

Control Unit Implementationd d lHardwired implementation

Microprogrammed Control


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