ee270 asynchronous sequential network - synthesisdr. tri caohuu © 2006 andy davis asynchronous...

EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy Davis

Asynchronous Circuit Design

Introduction Analysis Synthesis Races Static and dynamic hazards


Fundamental Mode Asynchronous Circuit

Comb

Delay

Input Output

Excitation

State

Secondary

State

Single Input Change

Asynchronous Sequential Circuit

Analysis


Example 1- Logic Diagram


Example 1- Excitation/Transition Table

Y1 = x2’y1 +x1’y1+x1’x2y2

Y2 = x1y1+x2y1y2+x1y2+x1x2

z = x2’y1 +x1’y1y2+x1x2‘y2

0000

1010

11 11

10

0110

00

00

01

01

01

1011

0000 01 01

11

01 10 11

ExcitationY1 Y2

PS

y1 y2

Input State x1x200 01 10 11

0 0 0 0

0 0 1 0

1 0 1 0

1 1 1 0

Output z

Input State x1x2


The State Table

A A

C C

D D

10

BC

00

00

B

B

01

C11

A A B B

D

01 10 11

Next StatePS


0 0 0 0

0 0 1 0

1 0 1 0

1 1 1 0

Output z

Input State x1x2

00 A

01 B

10 C

11 D


The Flow Table

A A

C C

D D

10

BC

00

00

B

B

01

C11

A A B B

D

01 10 11

Next StatePS


0 -- 0 ---- -- 1 0

1 0 -- ---- 1 1 --

Output z

Input State x1x2


The Flow Diagram

C D

BA

Asynchronous Sequential Network - SYNTHESIS

Synthesis

Races, Cycles, and Hazards


Synthesis of Asynchronous Sequential Circuit

When x1x2=00, then z1z2=00 Sequence x1x2=00 01 11, then z1z2=10. Output

remains at 10 until x1x2=00, then z1z2=00 Sequence x1x2=00 10 11, then z1z2=01. Output

remains at 01 until x1x2=00, then z1z2=00

2 2

x1x2z1z2


A. Partially completed Primitive Flow Table

x1x2

00 01 11 10

1 1 /00 -/-

2 2 /00 -/-

3 3 /10 -/-

4 4 /01 -/-

5 -/- 5 /10

6 -/- 6 /01

7 -/- 7 /00

8 -/- 8 /10

9 -/- 9 /01

Before output changes from 00

After output changes from 00

Two successfulsequences


B. Primitive Flow Table

x1x2

00 01 11 10

1 1 /00 2/00 -/dd 7/00

2 1/00 2 /00 5/d0 -/dd

3 1/d0 3 /10 5/10 -/dd

4 1/0d 4 /01 6/01 -/dd

5 -/dd 3/10 5 /10 8/10

6 -/dd 4/01 6 /01 9/01

7 1/00 -/dd 6/0d 7 /00

8 1/d0 -/dd 5/10 8 /10

9 1/0d -/dd 6/01 9 /01

Changes from 1 to 0

Changes from0 to 1

No change on output


C. Reduced Flow Table

2

3

4

5

6

7

8

9

1 2 3 4 5 6 7 8

56

)9,6,4(),8,5,3(),7,1(),2,1( a c b d

1

2

3

45

6

7

8

9


C. Reduced Flow Table Cont.

00 01 11 10

a a /00 a /00 b/d0 c/00

b a/d0 b /10 b /10 b /10

c c /00 a/00 d/0d c /00

d c /0d d /01 d /01 d /01


D. Race Free Assignment

a = 00 b = 01 c = 10 d = 11

a b

d c

11, 00

0110

00,11

a 00

ab

b 01c

ac

10

d=11


E. Excitation and Output Tables

x1x2 x1x2

00 01 11 10 00 01 11 10

00 00 00 01 10 00 00 d0 00

y1y2 01 00 01 01 01 d0 10 10 10

10 10 00 11 10 00 00 0d 00

11 10 11 11 11 0d 01 01 01

y1y2 z1z2


E. Excitation and Output Tables Cont.

212

211

2221212

2211211211

yyz

yyz

yxyxxxY

xyxyxyxyyY


F. Circuit

Delta

Delta

z1

z2

x1

x2

y1

y2


Race & Critical Race

Race Definition: Two or more secondary state (yi) variables change during a transition between stable state. Depending on which variables change firstly, we may end up in an incorrect stable state (critical race). However, if the circuit ends up in a correct state irrespect of which variable changes firstly, we have a case of non-critical race.


Race – Example

x1x2 x1x2

00 01 11 10 00 01 11 10

00 00 01 00 01 0 0 1 1

y1y2 01 00 01 10 01 0 0 0 0

10 00 10 10 11 1 1 0 0

11 00 10 00 11 0 0 1 1

y1y2 z


Race – Example Cont.

x1 x2 y1 y2

<1 0 1 1> <0000>

δ 1> δ 2 => 1011 => 0011 => 0010 => 0000

δ 2> δ 1 => 1011 => 0011 => 0001 => 0000

δ 1> δ 2 => 1001 => 1101 => 1100 => 1100We want to go from 01 to 10, but this change first before y1 change from 0 to 1

δ 2> δ 1 => 1001 => 1101 => 1111 => 1110

Non Critical

Not Correct

Correct


Avoidance

00 01 11 10

a a/0 b/0 a/1 b/1

b a/0 b/0 c/0 b/0

c a/1 c/1 c/0 d/0

d a/0 c/0 a/1 d/1

Critical RaceCol 01 => b, cCol 11 => a, cCol 10 => d, b


Avoidance Cont.

a b

d c

011000

110011 00

10

a b

d c

0110

1111

10


Avoidance Cont.

Let a = 00

ab => b = 01

bc = 01 => c = 11

cd => d = 10


Avoidance Cont.

00 01 11 10

00 00 01 00 01

01 00 01 11 01

11 00 11 11 10

10 00 11 00 10

Connected nodes of transition diagram differed by only one (1) bit


Race-Free State Assignment

00 01 11 10

a a/0 b/0 c/- a/0

b a/0 b/0 b/0 c/-

c a/- c/1 c/1 c/1

a b

c

01

11 10

a=00 => b=01, c=10 => b≠c


Method One (adding cycles)

00 01 11 10

a a/0 b/0 d/- a/0

b a/0 b/0 b/0 c/-

c d/- c/1 c/1 c/1

d a/- c/-

(a) -> d -> c -> (c)

a b

d c

01

1011

11

y1 y2

a 0 0b 0 1c 1 1d 1 0


Method One Cont.

00 01 11 10

00 00 01 10 00

01 00 01 01 11

11 10 11 11 11

10 00 dd 11 dd

y1y2

x1x2


Method Two: Universal state assignment


Method Two Cont.

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