ee241 - spring...
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EE241 - Spring 2006Advanced Digital Integrated Circuits
MoWe 2-3:30pm203 McLaughlin
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Practical InformationInstructor:
Jan M. Rabaey511 Cory Hall , 666-3102, jan@eecs
Office hours: M 3:30-5pm;
Reader: Simone Gambinisssimone@eecs
Admin: Jessica Budgin558 Cory Hall, 643-7804,
Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s06
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Lecture Videos
Lectures are videotaped and webcasted:http://webcast.berkeley.edu
New this year: podcast (pilot)Available starting 2/10
Please use the microphones when asking questions!
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Class Topics
This course aims to convey a knowledge of advanced concepts of circuit design for digital LSI and VLSI components in state of the art MOS technologies.
Emphasis is on the circuit design, and optimization of either very high speed or low power circuits for use in applications such asmicroprocessors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.
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EECS141 vs. EECS241
EECS 141:Basic transistor and circuit modelsBasic circuit design stylesFirst experiences with design – creating a solution given a number of specs
EECS 241:Transistor models of varying accuracyDesign under constraints: power-constrained, flexible, robust,…Learning the more advanced techniques Study the challenges facing design in the coming yearsCreating new solutions to challenging design problems
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Special Focus in Spring 2006
Design techniques for:Low-power and low-voltage design
Process Variations
Robust Design
Performance and Power Limits
Timing Strategies
Memory!!
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Class TopicsFundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks)
Design for deep-submicron CMOS - HIGH SPEED (2.5 weeks)Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles, dynamic logic
Design techniques for LOW POWER (2.5 weeks) analysis of power consumption sources
power minimization at the technology, circuit, and architecture level
Arithmetic circuits – adders, multipliers (2 weeks)
Driving interconnect, high-speed signaling (2 weeks)
Timing (2 weeks) Timing analysis, flip-flop/latch design, clock skew, clocking strategies, self-timed design, clock generation and distribution, phase-locked loops
Memory design (2 week)
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Class Organization
5 (+/-) assignments
1 term-long design projectPhase 1: Proposal (by week 3)
Phase 2: Study (report by week 7)
Phase 3: Design (presentation and report by final week)
Report and presentations last week of classes
Take-home final exam
Journal or Major Conference Paper
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Class Material
Baseline: “Digital Integrated Circuits - A Design Perspective”, 2nd ed. by J. M. Rabaey, A. Chandrakasan, B. NikolićOther reference books:
“Design of High-Performance Microprocessor Circuits,” edited by A. Chandrakasan, W. Bowhill, F. Fox“Low-Power Electronics Design,” C. Piguet, Ed.“High-Speed CMOS Design Styles, by K. Bernstein, et al.“Leakage in Nanometer CMOS Technologies,” by Narendra and Chandrakasan, Ed.“Digital Systems Engineering” by W. Dally“Low-Power CMOS Design,” by Chandrakasan and Brodersen“Logical Effort: Designing Fast CMOS Circuits,” by I. Sutherland, B. Sproull, D. Harris
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Class Material
List of background material available on web-site
Selected papers will be made available on web-siteLinked from IEEE Xplore and other resources
Need to be on campus to access, or use library proxy (check http://library.berkeley.edu)
Class-notes on web-site
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Sources
IEEE Journal of Solid-State Circuits (JSSC)
IEEE International Solid-State Circuits Conference (ISSCC)
Symposium on VLSI Circuits (VLSI)Other conferences and journals
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Project Topics
High-performance low-power logic Leakage suppressionCircuit optimization techniquesInterconnect in deep-submicronArithmetic circuitsHigh-speed communicationTiming strategies for gigascale circuitsMemory circuitsOther important circuit topics
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Tools
HSPICEYou need an account on cory.eecs
0.18 /0.13/0.09 μm CMOS device models and predictive sub-100nm models
Other tools, schematic or layout editors are optional
Cadence, Synopsys, available on mingus.eecs
More information to be posted on the web-site.
EE241 - Spring 2006Advanced Digital Integrated Circuits
Lecture 1: IntroductionTrends and Challenges in
Digital Integrated Circuit Design
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Suggested ReadingInternational Technology Roadmap (http://public.itrs.net) Chapter 1 – Impact of physical technology on architecture (J.H. Edmondson),Chapter 2 – CMOS scaling and issues in sub-0.25μm systems (Y. Taur)Baseline: Rabaey et al, Chapter 3.Selected papers from the web:
S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol.19, no.4, p.23-29, July-Aug. 1999.J. Meindl, “Low Power Microelectronics: Retrospect and Prospect”, Proceedings of the IEEE, April 1995.B. Davari et al., “CMOS Scaling for High Performance and Low Power - The Next Ten Years,” Proceedings of the IEEE, April 1995. A. Masaki, “Deep-Submicron warms up to High Speed Logic,” IEEE Cicuits and Devices Magazine, November 1992.
The contributions to this lecture by a number of people (P. Gelsinger, S, Borkhar, etc) are greatly appreciated.
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Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000.”Gordon Moore, Cramming more Components onto Integrated Circuits, (1965).
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18
10
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Moore’s law and cost
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Moore’s Law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tra
nsi
sto
rs (
MT
)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years
S. Borkar
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Moore’s Law - Logic Density
Shrinks and compactions meet density goalsNew micro-architectures drop density
Shrinks and compactions meet density goalsNew micro-architectures drop density
So
urc
e: In
telPentium (R)
Pentium Pro (R) 486
386
i860
1
10
100
1000
1.5μ
1.0μ
0.8μ
0.6μ
0.35
μ
0.25
μ
0.18
μ
0.13
μ
Lo
gic
Den
sity
2x trendL
og
ic T
ran
sist
ors
/mm
2
Pentium II (R)
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Die Size Growth
40048008
80808085
8086286
386486Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
S. Borkar
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Moore’s Wrong Prediction
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No end in sight yet…
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Technology EvolutionInternational Technology Roadmap for Semiconductors - 2003 data
2232456590Dram ½ pitch [nm]
8800M4400M2200M1100M550MMPU transistors/chip
14-1812-1612-1611-1510-14Wiring levels
913182537High-perf. physical gate [nm]
‘Low-power’ power [W]
Low-power VDD [V]
Cost-perf. power [W]
High-perf. power [W]
Local clock [GHz]
High-perf. VDD [V]
Year 20162013201020072004
0.80.91.01.11.2
4023159.34.2
3.03.02.82.52.2
0.50.60.70.80.9
15813812010484
288250220190160
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Printed vs. Physical Gate
ITRS’2003
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Some Recent Devices
Intel’s 30nm transistor
Ion = 570μm/μmIoff = 60nA/ μm
[B. Doyle, Intel]
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More Recent Devices
Intel’s 20nm transistor
[B. Doyle, Intel]
@0.75V
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More Recent Devices
SOI: Silicon-on-InsulatorUltra-Thin-Body (UTB) MOSFET
[Choi, UCB]
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18nm FinFET
Double-gate structure + raised source/drain
BOX Si fin - Body!
DrainSource
Gate
X. Huang, et al, 1999 IEDM, p.67~70
Gate
Silicon Fin
0
50
100
150
200
250
300
350
400
-1.5 -1.0 -0.5 0.0Vd [V]
I d[u
A/u
m]
-1.50 V
-1.00 V
-0.75 V
-0.50 V
-0.25 V
-1.25 V
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Not all is rosy …. Major Roadblocks
1. Managing complexityHow to design a 3 billion transistor chip?And what to use all these transistors for?
2. Cost of integrated circuits is increasingMask costs are more than $1M in 90nm technologyWith this cost increases, low volume ASICs are too expensive. Flexibility is needed.
3. The end of Frequency Scaling - Power as a limiting factor
4. Robustness issuesVariations, soft errors, coupling
5. The Interconnect scare
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Technology OutlookTechnology Outlook
Medium High Very HighMedium High Very HighVariabilityVariability
Energy scaling will slow downEnergy scaling will slow down>0.5>0.5>0.5>0.5>0.35>0.35Energy/Logic Op Energy/Logic Op scalingscaling
0.5 to 1 layer per generation0.5 to 1 layer per generation88--9977--8866--77Metal LayersMetal Layers
1111111111111111RC DelayRC Delay
Reduce slowly towards 2Reduce slowly towards 2--2.52.5<3<3~3~3ILD (K)ILD (K)
Low Probability High ProbabilitLow Probability High ProbabilityyAlternate, 3G etcAlternate, 3G etc
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1111
20162016
High Probability Low ProbabilitHigh Probability Low ProbabilityyBulk Planar CMOSBulk Planar CMOS
Delay scaling will slow downDelay scaling will slow down>0.7>0.7~0.7~0.70.70.7Delay = CV/I Delay = CV/I scalingscaling
256643216842Integration Integration Capacity (BT)Capacity (BT)
88161622223232454565659090Technology Node Technology Node (nm)(nm)
20182018201420142012201220102010200820082006200620042004High Volume High Volume ManufacturingManufacturing
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Complexity
105105
9090
7575
6060
4545
3030
1515
2.52.5 3.53.5 55 1010 1515 2020
0.13nm0.13nm
Gate Counts in Millions of GatesGate Counts in Millions of Gates
Eng
inee
ring
Eng
inee
ring
Man
-Yea
rs
ComplexityComplexity
90 nm90 nm
and DSMand DSM
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FAB Costs
$1
$10
$100
$1,000
$10,000
1960 1970 1980 1990 2000 2010
Fab
Co
st (
$M)
www.icknowledge.com
FAB Cost
$1
$10
$100
$1,000
$10,000
1960 1970 1980 1990 2000 2010
Fab
Co
st (
$M)
www.icknowledge.com
FAB Cost
$1
$10
$100
$1,000
$10,000
$100,000
1960 1970 1980 1990 2000 2010
Lit
ho
To
ol C
ost
($K
)
G. MooreISSCC 03
Litho Cost
$1
$10
$100
$1,000
$10,000
$100,000
1960 1970 1980 1990 2000 2010
Lit
ho
To
ol C
ost
($K
)
G. MooreISSCC 03
Litho Cost
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Mask Costs
0
500
1000
1500
2000
2500
1996 1998 2000 2002 2004 2006 2008
Year
Co
st [
in $
1000
]
45nm
65nm
90nm
0.13 μm
0.18 μm
0.25 μm
Mask costs follow Moore’s law as wellMask costs follow Moore’s law as well
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Cost Increases
Lithography is more complexLike “painting a 1cm line with a 3cm brush”
193nm → 157nm laser
Cost of exposure system
Cost of proximity correction, phase shift masks
Cost of mask repair
But – mask costs drop in subsequent years
Economic settings for maskless lithography
Design costs increase with added complexityChip starts ~$10M
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Optical Lithography Issues
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm193nm193nm248nm248nm
365nm365nmLithographyLithographyWavelengthWavelength
65nm65nm90nm90nm
130nm130nm
GenerationGeneration
GapGap
45nm45nm32nm32nm 13nm 13nm
EUVEUV
180nm180nm
Source: Mark Bohr, Intel
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm193nm193nm248nm248nm
365nm365nmLithographyLithographyWavelengthWavelength
65nm65nm90nm90nm
130nm130nm
GenerationGeneration
GapGap
45nm45nm32nm32nm 13nm 13nm
EUVEUV
180nm180nm
Source: Mark Bohr, Intel
Sub-wavelength lithography
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ASICs on the Road to Extinction (?)
0
2000
4000
6000
8000
10000
12000
1996 1997 1998 1999 2000 2001 2002* 2003* 2004* 2005* 2006*
ASIC ASSP
Courtesy R. Courtesy R. CamposanoCamposano, Synopsys, Synopsys
ASIC/ASSP Design StartsASIC/ASSP Design Starts
The Age of Concurrency and Flexibility
AMD Dual Core Microprocessor
Heterogeneous concurrency now prevalent in wireless, automotive,consumer, media processing, graphics and gaming
Heterogeneous concurrency now prevalent in wireless, automotive,Heterogeneous concurrency now prevalent in wireless, automotive,consumer, media processing, graphics and gamingconsumer, media processing, graphics and gaming
Berkeley Pleiades
ARMARMARM
Heterogeneousreconfigurable
fabric
HeterogeneousHeterogeneousreconfigurablereconfigurable
fabricfabric
NTT Video codecwith 4 Tensilica coresNTT Video codecNTT Video codecwith 4 with 4 TensilicaTensilica corescores
IBM/Sony Cell ProcessorIBM/Sony Cell ProcessorIntel Dual Core
Xilinx Vertex 4
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Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
qu
ency
(M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
S. Borkar
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Processor Frequency Trend
386486
Pentium(R)
Pentium Pro(R)
Pentium(R) II
MPC750604+604
601, 603
21264S
2126421164A
2116421064A
21066
10
100
1,000
10,000
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
Mh
z
1
10
100
Gat
e D
elay
s/ C
lock
Intel
IBM Power PC
DEC
Gate delays/clock
Processor freq scales by 2X per
generation
Frequency doubles each generationNumber of gates/clock reduce by 25%
V.De, S. BorkarISLPED’99
STOP!
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NO LONGER!
Frequency scaling of microprocessors has come to an abrupt end!Main reason: power-limited scaling!Performance increase to come from other sources (e.g. multi-core)
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The Power Challenge:Hottest chips published in ISSCC
Po
wer
per
ch
ip [
W]
1980 1985 1990 1995 20000.01
0.1
1
10
100
1000
Year
MPU
x4 / 3
year
s
DSP
x1.4 / 3 years
T. Kuroda, Keio University
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Microprocessor power
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
wer
(W
atts
)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
S. Borkar
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Power Will Be a Problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
S. Borkar
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Active Power Scaling
1
3.1)7.0
1()7.0()14.1
7.01
(fCVPower
),7.0
(Freqand,7.0VccIf.1
222 =×××==
==
8.1)2()7.0()14.17.0
1(fCVPower
,2Freqand,7.0VccIf.2
222 =×××==
==
7.2)2()85.0()14.17.0
1(fCVPower
,2Freqand,85.0VccIf.3
222 =×××==
==
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Power increase is due to scaling
0.1
1
10
100
1000
1 10
Po
wer
den
sity
: p
[W
/cm
2 ]
Design rule [µm]0.11
Scaling variable: κ
∝ κ3
10000
∝ κ0.7
MPU DSP
p = pDYNAMIC + pLEAK
Constant V scaling
→ pDYNAMIC ∝ κ3
V scaled as κ−1
IDS ∝ (VGS-VTH)1.3
→ pDYNAMIC ∝ κ0.7
(Sakurai, 2003)
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Power Density Will Increase
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Po
wer
Den
sity
(W
/cm
2)
Hot Plate
Nuclear Reactor
Rocket Nozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
S. Borkar
Sun’s Surface
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26
51
52
Source:R. Schmidt, IBM Corp
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Active leakage makes things even more interesting
Year2002 ’04 ’06 ’08 ’10 ’12 ’14 ’160
0.2
0.4
0.6
0.8
1
1.2
0
20
40
60
80
100
120
Tec
hn
olo
gy
no
de[
nm
]
Vo
ltag
e [V
]
VTH
VDD
Technology node
2002 ’04 ’06 ’08 ’10 ’12 ’14 ’160
1
2
Year
PDYNAMIC
PLEAK
Po
wer
[µW
/ g
ate]
Subthreshold leak(Active leakage)
T. Sakurai, ISSCC 03
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Active leakage may ruin the Moore’s law
Po
wer
per
ch
ip [
W]
1980 1985 1990 1995 20000.01
0.1
1
10
100
1000
Year
MPU
x4 / 3
year
s
DSP
x1.4 / 3 years
Processors published in ISSCC
2005 2010 2015
x1.1 / 3 years
ITRS requirement
10000
Dynamic
Leakage1/100
T. Sakurai, ISSCC 03
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Power and Energy Limiting Integration
1
10
100
1000
Active power density: k1.7
Leakage power density: k3.4
2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Compute density: k3
2003 ITRS – Low operating power scenario
• WRONG: stop voltage scaling
• PLAUSIBLE: slow down compute density increase
• WRONG: stop voltage scaling
• PLAUSIBLE: slow down compute density increase
Power and Energy Limiting Integration
Slow down compute density increase– Use slack to control leakage and power– Minimize connections to Vdd and GND!
1
10
100
2002 2004 2006 2008 2010 2012 2014 2016 2018 2020
Active power density: <k0.7
Compute density: k2
Leakage power density: <k1.4
But … signal integrity and reliability issuesBut … signal integrity and reliability issues
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57
Power Delivery Challenges
P6Pentium® proc
486386286
8086
80858080
800840040.01
0.10
1.00
10.00
100.00
1,000.00
1970 1980 1990 2000 2010Year
Icc
(am
p)
P6Pentium® proc
486386
286
8086
80858080
80084004
1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07
1970 1980 1990 2000 2010Year
L(d
i/dt)
/Vd
d
High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:
Challenges: IR drop and L(di/dt) noise
S. Borkar
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Process Variations
Control of minimum features does not track feature scaling
Relative device/interconnect variations increase
Sources:Random dopant fluctuations
Feature size, oxide thickness variations
Effects:Speed
Power, primary leakage
Yield
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Sources of VariationsSources of Variations
0
5 0
100
1 50
200
250H
eat
Flu
x (W
/cm
2)
Heat Flux (W/cm2)Results in Vcc variation
40
50
60
70
80
90
100
110
Tem
per
atu
re (
C)
Temperature Variation (°C)Hot spots
10
100
1000
10000
1000 500 250 130 65 32
Technology Node (nm)
Mea
n N
um
ber
of
Do
pan
t A
tom
s
Random Dopant Fluctuations
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm
193nm193nm248nm248nm365nm365nm
LithographyLithographyWavelengthWavelength
65nm65nm90nm90nm
130nm130nm
GenerationGeneration
GapGap
45nm45nm32nm32nm 13nm 13nm
EUVEUV
180nm180nm
Source: Mark Bohr, Intel
Sub-wavelength Lithography
0
20
40
60
80
100
120
-39.71 -25.27 -10.83 3.61 18.05 32.49
ΔVTn(mv)
# o
f C
hip
s
~30mV
VtVt DistributionDistribution
0.18 micron~1000 samples
Low FreqLow Isb
High FreqMedium Isb
High FreqHigh Isb
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Causes Larger Frequency DistributionCauses Larger Frequency Distribution
Courtesy IntelCourtesy Intel
Frequency & SD LeakageFrequency & SD Leakage
0.9
1.0
1.1
1.2
1.3
1.4
0 5 10 15 20
Normalized Leakage (Isb)
No
rmal
ized
Fre
qu
ency
0.18 micron~1000 samples
20X30%
Low FreqLow Isb
High FreqMedium Isb
High FreqHigh Isb
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The Reliability Challenge
Errors can and will happen• Voltage scaling, reduced noise margins and single-event upsets
make errors unavoidable• Complexity and DSM makes “full design-time verification” impossible• Using only “physical layer” solutions yields unacceptable overhead
VddVdd
GNDGND
Courtesy IBMCourtesy IBM
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The Interconnect Scare
33
SEMICONDUCTORSUPPLIERS
Interconnect Focus Centere¯e¯e¯e¯
65
IInterconnects Supersede Transistors :nterconnects Supersede Transistors :Energy DissipationEnergy Dissipation
MOSFET Switching Energy
InterconnectSwitching Energy
Lint=1mm
1.0 µm ~ 300 fJ ~ 400 fJ
100 nm ~ 2 fJ ~ 10 fJ
TechnologyGeneration
~ 0.1 fJ ~ 3 fJ35 nm(Cu,κ=2.0)
SEMICONDUCTORSUPPLIERS
Interconnect Focus Centere¯e¯e¯e¯
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Interconnects Supersede Transistors : Interconnects Supersede Transistors : Masking LevelsMasking Levels
FEOL BEOL
1.0 µm(Al, SiO2)
7 4 - 6
100 nm(Cu, κ=2.0) 8 - 20 18 - 24
TechnologyGeneration
35 nm(Cu, κ=2.0) 8 - 14 (SOI) 26 - 34
34
67
Why Technology Scaling?
Design new devices to be:Faster?Smaller?Lower power?Add new features?
Bottom line:Growth of semiconductor industry has been fueled by the “ever cheaper” transistor
Want to sell more functions (transistors) per chip for the same moneyBuild same products cheaper, sell the same part for less money
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Moore’s Law Challenge
Double transistors every two years (Obey Moore’s law)
Stay within the expected power trend
Still deliver the expected performance
Power-limited scaling regime
LOOKING AT SOLUTIONS TO THESE CHALLENGES IS WHAT THIS COURSE IS ALL ABOUT!