ee141 1 electronic design automation [ adopted from jan m. rabaey, alessandra nardi, abhay dixit,...

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Electronic Design Electronic Design AutomationAutomation

[Adopted from Jan M. Rabaey, Alessandra Nardi, Abhay Dixit, Meeta Bhate, Kedar Rajpathak, Tulika Mitra]

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Electronic Design AutomationElectronic Design Automation

Design Analysis Structural and Behavioral Modeling in HDL Design Verification Cell Based Design Programmable Logic Devices and FPGA Design Synthesis

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Design methodologiesDesign methodologies

analysis and verification- simulation is input dependent

- verification requires understanding of circuit operation

implementation and synthesis testability tools and techniques

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TerminologyTerminology HDL: Hardware Description Language

E.g.: Verilog, VHDL RTL: Register Transfer Level.

It is HDL written for logic synthesis: clock cycle to clock cycle operations and events are explicitly defined architecture of the design is implicit in RTL code

Behavioral HDLIt is HDL written for behavioral synthesis: it describes the intent and the algorithm behind the design

Behavioral synthesisIt tries to optimize the design at architectural level with constraints for clock, latency and throughput. The output is RTL level design with clocks, registers and buses.

Logic synthesisIt automatically converts RTL code into gates without modifying the implied architecture. It tries to optimize the gate-level implementation to meet performance (timing, area….) goals

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Verification at different levels of abstractionVerification at different levels of abstraction

Goal:Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction

In general this process consists of the followingconceptual steps:1. Creating the design at a higher level of abstraction2. Verifying the design at that level of abstraction3. Translating the design to a lower level of abstraction4. Verifying the consistency between steps 1 and 35. Steps 2, 3, and 4 are repeated until tapeout

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Verification at different levels of abstractionVerification at different levels of abstraction

Behavioral

HDL

System Simulators

HDL Simulators

Code Coverage

Gate-level SimulatorsStatic Timing

Analysis

Layout vs Schematic (LVS)

RTL

Gate-level

PhysicalDomain V

erif

icat

ion

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Verification TechniquesVerification Techniques

Simulation (functionalfunctional and timingtiming) Behavioral RTL Gate-level (pre-layout and post-layout) Switch-level Transistor-level

Formal Verification (functionalfunctional) Static Timing Analysis (timingtiming)

Goal:Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction

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Classification of SimulatorsClassification of Simulators

Logic Simulators

Emulator-based Schematic-basedHDL-based

Event-driven Cycle-based Gate System

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Classification of SimulatorsClassification of Simulators

HDL-basedHDL-based: Design and testbench described using HDL Event-driven Cycle-based

Schematic-basedSchematic-based: Design is entered graphically using a schematic editor

EmulatorsEmulators: Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.

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Instruction SetArchitecture

Design(Microarchitecture

Design-I)

System-LevelDesign

RTL Level Design

(MicroarchitectureDesign II)

CompilerDesign

CodeOptimizer

HardwareDesign

SwitchLevel

Design

CircuitLeveldesign

ISASimulator

System LevelSimulator

RTLLevel

Simulator

SwitchLevel

Simulator

CircuitLevel

Simulator

Arch./CompilerDesign Toolset Processor ArchitectureProcessor Architecture

Simulation and Design Simulation and Design Flow DiagramFlow Diagram

HDL (VHDL or Verilog)

CodeGenerator

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(Some) EDA Tools and Vendors(Some) EDA Tools and Vendors

Behavioral synthesis Behavioral compiler Synopsys

Logic Synthesis Design Compiler Synopsys BuildGates Ambit Design Systems Galileo (FPGA) Examplar (Mentor Graphics) FPGAExpress (FPGA) Synopsys Synplify (FPGA) Synplicity

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(Some) EDA Tools and Vendors(Some) EDA Tools and Vendors Logic Simulation

Scirocco (VHDL) Synopsys Verilog-XL (Verilog) Cadence Design Systems Leapfrog (VHDL) Cadence Design Systems VCS (Verilog) Chronologic (Synopsys)

Cycle-based simulation SpeedSim (VHDL) Quickturn PureSpeed (Verilog) Viewlogic (Synopsys) Cobra Cadence Design Systems Cyclone Synopsys

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Circuit SimulationCircuit Simulation Formulation of circuit equations

STA, MNA

Solution of linear equations LU factorization, QR factorization, Krylov Methods

Solution of nonlinear equations Newton’s method

Solution of ordinary differential equations One-step and Multi-step methods

AC Analysis and Noise Simulation Techniques for RF

Shooting-Newton Harmonic-Balance

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Analog Circuits – A World ApartAnalog Circuits – A World Apart Analog circuits’ behavior specified in terms of complex

functions: time-domain, frequency-domain, distortion, noise, power spectra….

Required accuracy of models much higher than digital

…emerging paradigm: Field Programmable Analog Array for prototyping (and more)

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Design analysis and simulationDesign analysis and simulation

Spice - exact but time consuming

discrete time steps circuit models timing simulation with

partitioning and relaxation method

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Timing SimulationTiming Simulation

Vdd

out1 out2in

out3

i(Vdd)

in

out1

out2

out3

Vdd-Vth

• Uses simplified (table-lookup) transistor model• Handles leakage, direct path, and reduced swing

• Up to 2 orders of magnitude faster than SPICE

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Switch-Level SimulationSwitch-Level Simulation

Linear Switch-Level Simulation RSIM (Terman), nRSIM (Chu), IRSIM (Horowitz) Model transistor as switched, linear resistor Ternary (0, 1, X) node states Elmore (RC product) model of circuit delay

aa

1

X

0

Voltage LogicValue

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Switch-Level SimulationSwitch-Level Simulation

A

B

X

F

Cap

(fF

/bit)

Sample

0102030405060708090

100

0 10 20 30 40 50 60

IRSIMSPICE

Up to 3 Orders of Magnitude Faster than Circuit

• Accurate for Dynamic Power

• Unreliable on leakage and direct path currents

Switch level model of inverter

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Event-driven SimulationEvent-driven Simulation

Event: change in logic value at a node, at a certain instant of time (V,T)

Event-driven: only considers active nodes Efficient

Performs both timing and functional verification All nodes are visible Glitches are detected

Most heavily used and well-suited for all types of designs

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Event: change in logic value, at a certain instant of time (V,T)

10

1

0

1

0

1

D=2a

b

cEvents:•Input: b(1)=1•Output: none

10

1

0

1

0

1

D=2a

b

cEvents:•Input: b(1)=1•Output: c(3)=03

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Uses a timewheel to manage the relationship between components

TimewheelTimewheel = list of all events not processed yet, sorted in time (complete ordering)

When event is generated, it is put in the appropriate point in the timewheel to ensure causality

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d

b(1)=1d(5)=1

d(5)=1

D=1

101

01

D=2a

bc

501

e01

3

c(3)=0d(5)=1

01

4

d(5)=1

e(4)=0

6

e(6)=1

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Cycle-based SimulationCycle-based Simulation

Take advantage of the fact that most digital designs are largely synchronous

Synchronous circuit: state elements change value on active edge of clock

Only boundary nodes are evaluated

Internal Node

Boundary NodeLatches

Latches

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Cycle-based SimulationCycle-based Simulation

Compute steady-state response of the circuit at each clock cycle at each boundary node

Latches

Latches

Internal Node

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Cycle-based versus Event-drivenCycle-based versus Event-driven

Cycle-based:Cycle-based: Only boundary nodes No delay information

Event-driven:Event-driven: Each internal node Need scheduling and

functions may be evaluated multiple times

Cycle-based is 10x-100x faster than event-driven (and less memory usage)

Cycle-based does not detect glitches and setup/hold time violations, while event-driven does

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Simulation: Simulation: Perfomance vs AbstractionPerfomance vs Abstraction

.001x

SPICE

Event-drivenSimulator

Cycle-basedSimulator

1x 10xPerformance and Capacity

Abs

trac

tion Timing

Simulator

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Perspective on accuracy and Perspective on accuracy and speedspeed

Comparison between circuit simulation (SPICE)and timing or switch analysis

% Error Speedup % Error SpeedupTiming 6 15 7 3.7Switch 27 60 4 22

Adder Shift Register

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Gate level simulationGate level simulation

faster than switch level

functional simulation

VHDL description used

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Epics PowerMillEpics PowerMill

*** Current information is calculated from 5.00 ns to 400.00 ns ***

average current on VDD : -0.442845 mApeak current on VDD : -10.269000 mA at 211.10 nsrms current on VDD : +0.877633 mA

average current on GND : +0.364263 mApeak current on GND : +6.720000 mA at 49.50 nsrms current on GND : +0.645861 mA

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PowerMill PerformancePowerMill Performance

Ckt’s Nodes Elements Vectors CPU Time*SW Avg Total Avg

1 582 1,134 406 3.33mA

SW/Total%

3.92mA 84.9% 13.6Min**

2 4,162 9,476 16 13.3mA 15.3mA 86.9% 15.7Min

3 1,066 60 12.3mA 22.6mA 54.4% 47.2Sec475

4 7.91mA 16.9mA 46.8% 28.5Min14,200 29,956 250

5 14.5mA 76.5mA 18.9% 2.65hr32,676 70,971 150

6 20.1mA 27.2mA 73.9% 10.6hr51,658 103,653 1,000

7 231mA 307mA 75.2% 15.2hr44,239 106,379 1,000

8 70.2mA 201mA 34.8% 19.6hr522,411 1,000183,103

** 70.2hr for Spice* On a 25-Mips machine

add

add

SRAM

Ctrl

DRAM

DSP

F.P.

SRAM

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Avant!s STAR-ADM (previously Anagram)Avant!s STAR-ADM (previously Anagram)

Mixed analog/digital simulation Claims to be more accurate for deep sub-micron design

than switch-level simulation

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Performance BenchmarksPerformance Benchmarks

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Structural model in VHDLStructural model in VHDL

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Behavioral model in VHDLBehavioral model in VHDL

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High level behavioral VHDLHigh level behavioral VHDL

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Digital Systems VerificationDigital Systems Verification

Overview Cycle-based and event-driven simulation Formal methods

Timing Analysis

Hardware Description Languages (Verilog-VHDL)

System C

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Verification - SimulationVerification - Simulation

Consistency: same testbench at each level of abstraction

Behavioral

Gate-level Design(Post-layout)

Gate-level Design(Pre-layout)

RTL Design

Testbench Simulation

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Formal VerificationFormal Verification Can be used to verify a design against a

reference design as it progresses through the different levels of abstraction

Verifies functionality without test vectors Three main categories:

Model Checking: compare a design to an existing set of logical properties (that are a direct representation of the specifications of the design). Properties have to be specified by the user (far from a “push-button” methodology)

Theorem Proving: requires that the design is represented using a “formal” specification language. Present-day HDL are not suitable for this purpose.

Equivalence Checking: it is the most widely used. It performs an exhaustive check on the two designs to ensure they behave identically under all possible conditions.

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Digital Systems VerificationDigital Systems Verification Timing AnalysisTiming Analysis

Not only has the design to “function properly”….it also has always tighter timing constraints

Design timing properties have

to be verified

Static Timing Analysis is the main method

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Static Timing AnalysisStatic Timing Analysis

Suitable for synchronous design

Verify timing without testvectors

Conservative with respect to dynamic timing analysis

Latches LatchesCombinationalLogic

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Static Timing AnalysisStatic Timing Analysis

Inputs: Netlist, library models of the cells and constraints

(clock period, skew, setup and hold time…) Outputs:

Delay through the combinational logic

Basic concepts: Look for the longest topological path Discard it if it is false

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Conventional Simulation Conventional Simulation Methodology LimitationsMethodology Limitations

Increase in size of design significantly impact the verification methodology in general Simulation requires a very large number of test

vectors for reasonable coverage of functionality Test vector generation is a significant effort Simulation run-time starts becoming a bottleneck

New techniques: Static Timing Analysis Cycle-based simulation Formal Verification

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New Verification ParadigmNew Verification Paradigm Functional: cycle-based simulation and/or formal

verification Timing: Static Timing Analysis

Gate-level netlist

RTL

TestbenchLogic Synthesis

Cycle-based Sim.

Event-driven Sim.

Static Timing Analysis

Formal Verification

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More issuesMore issues

System Level Simulation (Hardware/Software Codesign) CoCentric System Studio Synopsys Virtual Component Co-Design (VCC)

Cadence Design Syst.

Mixed-Signal Simulation Verilog-AMS

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Design verificationDesign verification

checking number of inversions between two C2MOS gates

checking pull-up and pull down ratio in pseudo-NMOS gates

checking minimum driver size to maintain rise and fall times

checking charge sharing to satisfy noise-margins

Electrical verification

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Spice too long simulation time RC delay estimated using Penfield-

Rubinstein-Horowitz method identification of critical path (avoid false

paths)

Timing verification

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components described behaviorally circuit model obtained from component

models resulting circuit behavior computed with

design specifications no generally acceptable verifier exists

Formal verification

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Physical issues verification (DSM)Physical issues verification (DSM)

Interconnects Signal Integrity

P/G integrity Substrate coupling Crosstalk

Parasitic Extraction Reduced Order Modeling Manufacturability and Reliability

Power Estimation

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(Some) EDA Tools and Vendors(Some) EDA Tools and Vendors Formal Verification

Formality Synopsys FormalCheck Cadence Design Systems DesignVerifyer Chrysalis

Static Timing Analysis PrimeTime Synopsys (gate-level) PathMill Synopsys (transistor-level) Pearl Cadence Design Systems

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SummarySummary

Conventional design and verification flow review

Verification Techniques Simulation

– Behavioral, RTL, Gate-level, Switch-level, Transistor-level

Formal Verification Static Timing Analysis

Emerging verification paradigm Functional: cycle-based, formal verification Timing: Static Timing Analysis

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““Prototyping” Techniques Prototyping” Techniques in Design Stagesin Design Stages

timetime

HardwareHardwareDesignDesign

ChangesChanges

SoftwareSoftwareSimulationSimulation

EmulationEmulation

PrototypePrototypeReplicationReplicationFlexibilityFlexibility

PerformancePerformance

CostCost

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Implementation approachesImplementation approaches

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Custom circuit designCustom circuit design

labor intensive high time-to-market cost amortized over a large volume reuse as a library cell was popular in early designs layout editor, DRC, circuit extraction

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Layout editorLayout editor

transistor symbols relative positioning compaction stick diagram description design rules automatically satisfied automatic pitch matching

1. Polygon based (Magic)2. Symbolic layout

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Automatic pitch matchingAutomatic pitch matching

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Design rule checkingDesign rule checking

on-line DRC- rules checked and errors

flagged during layout batch DRC

- post design verification

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Circuit extractionCircuit extraction

Circuit schematic derived from layout

Transistors are build with proper geometry

Parasitic capacitances and resistances evaluated

Extraction of inductance requires 3D analysis

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Cell-based designCell-based design

reduced cost reduced time reduced integration density reduced performance

standard cell compiled cells module generators macro cell place and route

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Standard cellStandard cell

library contains basic logic cells- inverter, AND/NAND, OR/NOR,

XOR/NXOR, flip-flop, AOI, MUX, adder, compactor, counter, decoder, encoder,

fan-in and fan-out specified schematic uses cells from library layout automatically generated

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Standard cellStandard cell cells have equal heights cell rows separated by routing channels

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Standard cell designStandard cell design

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Standard cellStandard cell layoutlayout and and descriptiondescription

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An Example CellAn Example Cell A 2-input dynamic C with a clearing

input and an inverting output (C_dic2)

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Single vs Double Height CellsSingle vs Double Height Cells

arbiter

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Single vs Double Height Cells…Single vs Double Height Cells… arbiter_dblht

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Existing Design FlowExisting Design Flow

Synopsys Synthesis

CadenceSilicon

Ensemble

CadenceComposerSchematic

CadenceVirtuosoLayout

ExistingDatapathLayout

Behavioral VerilogCode

YourLibraries

LVS

Verilog-XL

Verilog-XL

BehavioralVerilog

Structural Verilog

CircuitLayout

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New Design FlowNew Design Flow

Cadence to Synopsys Interface

CadenceSilicon

Ensemble

CadenceComposerSchematic

CadenceVirtuosoLayout

ExistingDatapathLayout

Standard Cell

Libraries

LVS

Verilog-XL

Structural Verilog

CircuitLayout

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Placed and RoutedPlaced and Routed

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What are Standard Cell LibrariesWhat are Standard Cell Libraries

Standard-cell libraries are fixed set of well-characterized logic blocks.

Basic logic functions are used several times on the same integrated circuit.

It will have leaf cells ranging from simple gates to latches and flip-flops. These can then be used to build arithmetic blocks like adders and multipliers.

ASIC designers commonly employ the use of standard cell libraries due to their robustness and flexibility resulting in quick turnaround times.

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Advantages of standard cell librariesAdvantages of standard cell libraries

Designers save time and money by reducing the product development cycle time.

Reduce risk by using predesigned, pretested and precharacterised standard cell libraries.

Optimisation is possible.

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Disadvantages of standard cell librariesDisadvantages of standard cell libraries

Time and expenses of designing or buying the standard cell library.

Time needed to fabricate all layers of ASIC for each new design when the standard cell library must be ported to a new

fabrication process, the physical layout of all the cells need to be changed.

There are no naming conventions There are no standards for cell behavior

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Standard cellStandard cell

large design cost amortized over a large number of designs

large number of different cells with different fan-ins large fan-out for cells to be used in different designs synthesis tools made standard cell design popular standard cell design outperform PLA in area and

speed standard cell benefit from multi level logic synthesis

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Classification of standard cell librariesClassification of standard cell libraries

Classical Libraries:--- Theses are the most common logic elements like gates, flip-flops, multiplexers, PAL, memories etc.

IP (Intellectual Property) offerings:

--- These include products like gate arrays and CPLDs which are IP offerings by many companies. Each one providing its own features and facilities in the product.

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Fragment of an ASIC LibraryFragment of an ASIC Library

Class ElementCombinationalfunctions

NAND, NOT, NOR, XOR

Storage functions D flip-flop,Latch, J-Kflip-flop, shift register,RAM, ROM

Information switches Selector, Multiplexer

Data Operator Adder, counter, ALU,Decoder

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MOSIS compatible cell libraries are provided by many organisations, commercial and non-commercial both

Commercial organisations are: Mentor Graphics, Cadence, Artisan, Avant, Barcelona Design, Tanner Research, LEDA systems etc.

Non Commercial Organisations are:MSU’s SCMOS Library, LASI, Ballistic, Magic etc.

MOSIS compatible design tools and cell librariesMOSIS compatible design tools and cell libraries

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Standard Cells Provided by Mentor GraphicsStandard Cells Provided by Mentor Graphics

There are over 200 standard cells available for the 2.0 um, 1.2 um, and 0.8 um technology.-- 2, 3, and 4-input AND, NAND, OR, NOR, AO

-- 2-input XOR and XNOR gates -- 2-1 MUX gate

-- multiple drive strength buffers, inverters and tri-state buffers -- four D-type flip-flops: dff, dffs, dffr, and dffsr -- four D-type latches: latch, latchs, latchr, latchsr

All of these cells have quickpart models with timing for full, backannotated simulation after layout

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MGC Digital LibrariesMGC Digital Libraries

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MGC Digital Libraries (Contd..)MGC Digital Libraries (Contd..)

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New Trends in Standard Cell LibrariesNew Trends in Standard Cell Libraries In a bid to improve the performance of standard-cell designs,

vendors of place-and-route and synthesis tools and cell libraries are teaming up to develop a technique that is likely to lead to the death of the standard cell itself.

Prolific Inc. (Newark, Calif.) has launched a tool called Liquid Libraries that will create tuned cells on the fly and insert them into the libraries used by place and route tools

Hot on the heels of Prolific's launch, Cadabra Design Automation (Santa Clara, Calif.) is working on a new flow that would ultimately move library generation as far forward as the synthesis phase, giving logic designers the ability to tune parts of a design for low power consumption or speed

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New Trends Contd..New Trends Contd..

Prolific is working with Cadence Design Systems, Magma Design Automation, Monterey Design Systems and Sapphire Design Automation..

Cadabra is working with Avanti, Cadence, Synopsis and Magma.

The first fruit of the Cadabra project will be the power and performance optimization (PPO) flow.

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Important Links to Standard Cell LibrariesImportant Links to Standard Cell Libraries

a) Tanner Inc. www.tanner.com.

b) Prolific Inc. www. prolificinc.com c) MOSIS organisation www.mosis.org MOSIS/Tech Support/MOSIS Compatible Design Toolsd) Cadabra Design www.cadabratech.com Automation Inc.e) Cadence Design Systems www.cadence.com Inc.

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Compiled cellCompiled cell

cell layout generated on the fly transistor or gate level netlist used with transistor

size specified layout densities approach that of human designers

Circuit schematicswith

transistor sizing

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Compiled cellCompiled cell

Generated layout

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Module generatorsModule generators

logic level cells not efficient for subcircuit design- shifters, adders, multipliers, data paths,

PLAs, counters, memories Macrocell generators

- use design parameters like number of bits data path compilers

- use bit slice modules and repeat them N times - generate interconnections between modules

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Datapath compilers Datapath compilers

Feedtroughs used to improve routing

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Datapath Datapath compilers compilers Datapath compiler

results

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Macrocell place and routeMacrocell place and route channel routing

- metal 2 horizontal segments

metal 1 vertical segments over the block routing

(3-6 metal layers used)

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Array-based design implementationArray-based design implementation

mask programmable arrays fuse based FPGAs nonvolatile FPGAs RAM based FPGAs

To avoid slow fabrication process which takes 3-4 weeks :

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Mask programmable arraysMask programmable arrays

gate-array - similar to standard cell

sea-of-gate- routed over the cells (high density)

- wires added to make logic gates challenge in design is to utilize the maximum

cell capacity utilization < 75% for random logic design

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Fuse-based PLD’sFuse-based PLD’s

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Fuse-based FPGA’sFuse-based FPGA’s

Actel sea-of-gate and standard cell approach

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Example : XOR gate obtainedby setting :A=1, B=0, C=0, D=1,SA=SB=In1,S0=S1=In2

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Anti-fuse provides short (low resistance) when blown out

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Nonvolatile FPGA’sNonvolatile FPGA’s

programming similar to PROM erasable programmable logic devices - EPLD electrically erasable - EEPLD design partitioned into macrocells flip-flops used to make sequential circuits software used to program interconnections to

optimize use of hardware input specified from schematics, truth tables,

state graphs, VHDL code

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RAM based (RAM based (volatilevolatile) FPGA’s) FPGA’s

programming is fast and can be repeated many times

no high voltage needed integration density is high information lost when the power goes

off

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XILINX FPGA’sXILINX FPGA’s

configurable logic blocks CLBs used five input two output combinational blocks two D flip flops are edge or level triggered functionality and multiplexers controlled by

RAM RAM can be used as look-up table or a

register file

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each cell connected to 4 neighbors routing channels provide local or global

connections switching matrices(RAM controlled) are

used for switching between channels

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XILINX FPGA’s (XC4025)XILINX FPGA’s (XC4025)

32 × 32 CLBs 25000 gates 422 k bites of RAM operates at 250 MHz 32 kbit adder uses 62 CLBs

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XILINX FPGA’s (XC4025)XILINX FPGA’s (XC4025)

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Universal Nanoscale ArchitectureUniversal Nanoscale Architecture Beyond lithographic

limits Crossed Wire

nanoarrays Implement PLAs,

memory, and xbars

NSC’02: to appear IEEE TR Nano

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Design synthesisDesign synthesis

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Circuit synthesisCircuit synthesis

derivation of the transistors schematics from logic functions

- complementary CMOS- pass transistor

- dynamic - DCVSL

(differential cascode voltage switch logic) transistor sizing

- performance modeling using RC equivalent circuits - layout generation

synthesis not popular due to designers reluctance

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Logic synthesisLogic synthesis

state transition diagrams, FSM, schematics, Boolean equations, truth tables, and HDL used

synthesis - combinational or sequential - multi level, PLA, or FPGA

logic optimization for - area, speed , power- technology mapping

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Logic optimizationLogic optimization

Expresso - two level minimization tool (UCB)

state minimization and state encoding MIS - multilevel logic synthesis (UCB)

Example : S = (AB) Ci

Co= AB + ACi + BCi

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Architecture synthesisArchitecture synthesis

behavioral or high level synthesis optimizing translation e.g. pipelining Cathedral and HYPER tools HYPER tutorial and synthesis example:

http://infopad.eecs.berkeley.edu/~hyper

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Architecture SynthesisArchitecture Synthesis

Automatic Tool

Application

Customized Architecture

Power

Size

Performance

Timing

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Architecture synthesis exampleArchitecture synthesis example

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Architecture synthesisArchitecture synthesis

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Tensilica: Xtensa ArchitectureTensilica: Xtensa Architecture

Copyright: Tensilica

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Design FrameworkDesign Framework

Copyright: Tensilica

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Silicon ChoicesSilicon Choices ASIC implementation of Processor

Fast but not flexible Time intensive design process Example: Tensilica, HP-STMicroelectronics

Processor core in ASIC but instruction set extensions in reconfigurable logic Medium speed but flexible Fast design process Example: Triscend Configurable System-on-Chip

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Triscend Configurable SoCTriscend Configurable SoC

Copyright: Triscend

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Reconfigurable Computing 101Reconfigurable Computing 101 Higher performance than software with higher level of flexibility than

hardware e.g. Field Programmable Gate Arrays (FPGA)

Logic Blocks– Array of computational elements whose functionality is

determined through multiple SRAM configuration bits Interconnection

– Logic blocks are connected using programmable routing resources

Any custom circuit can be mapped to FPGA by computing logic functions within logic blocks and using configurable routing to connect the logic blocks together

Dynamically reconfigurable Logic Logic reconfiguration during application execution Temporal partitioning of software reduces logic area Overhead for reconfiguration

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Use of Reconfigurable ComputingUse of Reconfigurable Computing

Two choices Map both control and datapath to RC Map only datapath to RC

Granularity of reconfigurable logic Bit Multiple bits ALU

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RC Coupled to I/O System BusRC Coupled to I/O System Bus

Most common form of commercial RC Overhead of data transfer between CPU and RC Requires large granularity of computation on RC

CPU

RC I/O

Memory

Local Bus

PCI BusPCI Bus

Local Bus

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RC Coupled to Local BusRC Coupled to Local Bus

Pilchard from Chinese University of Hong Kong Still requires large granularity of computation

CPU

RC I/O

Memory

Local Bus

PCI BusPCI Bus

Local Bus

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RC Coupled to CPU as CoprocessorRC Coupled to CPU as Coprocessor

Tight coupling between CPU and RC RC can execute ISA extensions CPU and RC cannot share register file

CPU

RC I/O

Memory

Local Bus

PCI BusPCI Bus

Local Bus

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PICO ArchitecturePICO Architecture

Copyright: Bob Rau et. al.

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Design FrameworkDesign Framework


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Design FlowDesign Flow


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Hardware/software Co-designHardware/software Co-design

Well studied problem. Then what’s new? High Level Synthesis (HLS)

Time-to-market constraint forces automated generation of reconfigurable bitstream from high level specification or software

Automated generation of interface Spatial and temporal partitioning

Partitioning among multiple configurable devices Map a function that exceeds the available space of

reconfigurable device using time sharing Requires new compilation techniques

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High Level Synthesis-1High Level Synthesis-1

High level hardware description language Start from software programming language

and add support for Parallelism via threads Message passing Examples: Handel-C, SystemC

Make current HDL more abstract Superlog, System Verilog

Still requires user to find parallelism

EE141132

High Level Synthesis-2High Level Synthesis-2

Combine research in two different fields: compiler and design automation

Traditional HLS techniques target ASIC implementation RC does not have the layout freedom Objective of RC is to minimize execution time Temporal partitioning if insufficient area Hardware library of operators or structures

commonly used by software programs

EE141133

High Level Synthesis-3High Level Synthesis-3 Concentrate on loops Leverage parallelizing compiler technology combined

with high level synthesis Parallelize computation Optimize external memory access Loop transformation: Area versus Performance

– Unroll and Jam– Loop unrolling– Software pipelining– Loop-invariant code motion– Data layout

Hardware specific optimizations Bitwidth reduction

ee141 1 electronic design automation [ adopted from jan m. rabaey, alessandra nardi, abhay dixit,...

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