ee 8351 digital logic circuits unit 5 - vhdl · vhdl – general guidelines 1. vhdl is not case...
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EE 8351 Digital Logic Circuits
Mrs.J.Jayaudhaya, ASP/EEE
&
Mr.N.S.Srivatchan, ASP/EEE
UNIT 5 - VHDL
Syllabus
RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).
3
Introduction
• Hardware description languages (HDL) – Language to describe hardware – Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description Language – Developed by DOD from 1983 – IEEE Standard 1076-1987/1993/200x – Based on the ADA language
• Verilog – IEEE Standard 1364-1995/2001/2005 – Based on the C language
4
Applications of HDL
• Model and document digital systems
– Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
– Convert from higher abstraction levels to lower abstraction levels
5
Input-Output specification of circuit
my_ckt
A
B
S
X
Y
Example: my_ckt
Inputs: A, B, C
Outputs: X, Y
VHDL description: entity my_ckt is
port (
A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit);
end my_ckt ;
6
my_ckt
A
B
S
X
Y
VHDL entity
• entity my_ckt is
port (
A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit
);
end my_ckt;
Name of the circuit User-defined Filename same as circuit name Example.
Circuit name: my_ckt Filename: my_ckt.vhd
Port names or Signal names
Name of the circuit User-defined Filename same as circuit name
recommended Example:
Circuit name: my_ckt Filename: my_ckt.vhd
Datatypes: In-built User-defined
Direction of port 3 main types: in: Input out: Output inout: Bidirectional
Note the absence of semicolon “;” at the end of the last signal and the presence at the end of the closing bracket
7
Built-in Datatypes
• Scalar (single valued) signal types: – bit
– boolean
– integer
– Examples: • A: in bit;
• G: out boolean;
• K: out integer range -2**4 to 2**4-1;
• Aggregate (collection) signal types: – bit_vector: array of bits representing binary numbers – signed: array of bits representing signed binary numbers – Examples:
• D: in bit_vector(0 to 7);
• E: in bit_vector(7 downto 0);
• M: in signed (4 downto 0); --signed 5 bit_vector binary number
8
User-defined datatype
• Construct datatypes arbitrarily or using built-in datatypes
• Examples: – type temperature is (high, medium, low);
– type byte is array(0 to 7) of bit;
9
Functional specification
• Example:
– Behavior for output X:
• When S = 0 X <= A
• When S = 1 X <= B
– Behavior for output Y:
• When X = 0 and S =0 Y <= ‘1’
• Else Y <= ‘0’
my_ckt
A
B
S
X
Y
10
VHDL Architecture
• VHDL description (sequential behavior): architecture arch_name of my_ckt is begin p1: process (A,B,S)
• begin
if (S=‘0’) then
X <= A;
else
X <= B;
end if;
if ((X = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
end process p1; end;
Error: Signals defined as output ports can only be driven and not read
11
VHDL Architecture
architecture behav_seq of my_ckt is
signal Xtmp: bit;
begin p1: process (A,B,S,Xtmp)
begin
if (S=‘0’) then
Xtmp <= A;
else
Xtmp <= B;
end if;
if ((Xtmp = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
X <= Xtmp;
end process p1;
end;
Signals can only be defined in this place before the begin keyword
General rule: Include all signals in the sensitivity list of the process which either appear in relational comparisons or on the right side of the assignment operator inside the process construct. In our example: Xtmp and S occur in relational comparisons A, B and Xtmp occur on the right side of the assignment operators
12
VHDL Architecture
• VHDL description (concurrent behavior):
architecture behav_conc of my_ckt is
signal Xtmp: bit;
begin
Xtmp <= A when (S=‘0’) else
B;
Y <= ‘1’ when ((Xtmp = ‘0’) and (S = ‘0’)) else
‘0’;
X <= Xtmp;
end ;
13
Signals vs Variables
• Signals
– Signals follow the notion of ‘event scheduling’
– An event is characterized by a (time,value) pair
– Signal assignment example:
X <= Xtmp; means
Schedule the assignment of the value of signal Xtmp to signal X at (Current time + delta)
where delta: infinitesimal time unit used by simulator for processing the signals
14
Signals vs Variables
• Variables – Variables do not have notion of ‘events’ – Variables can be defined and used only inside the process block and
some other special blocks. – Variable declaration and assignment example: process (…)
variable K : bit;
begin
…
-- Assign the value of signal L to var. K immediately
K := L;
…
end process;
Variables can only be defined and used inside the process construct and can be defined only in this place
15
Simulation
• Simulation is modeling the output response of a circuit to given input stimuli
• For our example circuit: – Given the values of A, B and S – Determine the values of X and Y
• Many types of simulators used – Event driven simulator is used popularly – Simulation tool we shall use: ModelSim
my_ckt
A
B
S
X
Y
16
Simulation
architecture behav_seq of my_ckt is
signal Xtmp: bit;
begin p1: process (A,B,S,Xtmp)
variable XtmpVar: bit;
begin
if (S=‘0’) then
Xtmp <= A;
else
Xtmp <= B;
end if;
if ((Xtmp = ‘0’) and (S = ‘0’)) then
Y <= ‘1’;
else
Y <= ‘0’;
end if;
X <= Xtmp;
XtmpVar := Xtmp;
end process p1;
end;
Time ‘T’
A B S Xtmp Y XtmpVar X
0- U U U ‘X’ ‘X’ ‘X’ ‘X’
0 0 1 0 ‘X’ ‘X’ ‘X’ ‘X’
0+d 0 1 0 0 0 0 ‘X’
0+2d 0 1 0 0 1 0 0
1 0 1 1 0 1 0 0
1+d 0 1 1 1 0 0 0
1+2d 0 1 1 1 0 0 1
Scheduled events
list:
Xtmp = (0,0+d)
Y = (0,0+d)
X = (‘X’,0+d)
Assignments executed:
XtmpVar = ‘X’
Scheduled events
executed:
Xtmp = 0
Y = 0
X = ‘X’
Assignments executed:
XtmpVar = 0
Scheduled events
list:
Xtmp = (0,0+2d)
Y = (1,0+2d)
X = (‘0’,0+2d)
Scheduled events
executed:
Xtmp = 0
Y = 1
X = 0
Scheduled events
list:
(empty)
VHDL – General Guidelines
1. VHDL is not case sensitive
2. Identifier must start with a letter
3. All statements end with a semi-colon
4. Comments precede with (--)
5. “<= “ - signal assignment
6. “:=“ - variable assignment
7. Variables are like C- type variables.
8. Signals have a one time value set associated to it at any time.
IF – THEN - ELSE
General syntax is:
if (condition_1) then
begin … statements_1 …
end;
elsif (condition_2) then
begin … statements_2 …
end;
else
begin …statements _i …end;
end if;
STRUCTURAL MODELING
1. Consider an example of a Dual 2 by 1 multiplexer using structural modeling.
2. Components required :
2- input AND gate
2- input OR gate
Inverter
ENTITY OF THE INVERTER
ENTITY inv IS
PORT(
i1: IN BIT;
o1: OUT BIT );
END inv;
ARCHITECTURE OF THE INVERTER
ARCHITECTURE single_delay OF inv IS
BEGIN
o1 <= not (i1) after 5ns;
END single_delay;
DESIGN OF A SIMPLE 2 INPUT AND GATE WITH A DELAY
ENTITY and2 IS
PORT(
i1, i2 :IN BIT;
o1: OUT BIT);
END and2;
ARCHITECTURE single_delay OF and2 IS
BEGIN
o1 <= (i1 AND i2) after 8ns;
END single_delay;
DESIGN OF A SIMPLE 2 INPUT OR GATE WITH A DELAY
ENTITY or2 IS
PORT(
i1, i2 :IN BIT;
o1: OUT BIT);
END or2;
ARCHITECTURE single_delay OF or2 IS
BEGIN
o1 <= (i1 or i2) after 8ns;
END single_delay;
SINGLE AND DUAL 2-1 MULTIPLEXER ENTITY
ENTITY single_mux IS
PORT(
s: IN BIT ; --select input
iA, iB : INT BIT; -- iA is selected if --s=‘0’ and iB is selected if s= ‘1’
oZ: OUT BIT –output of the mux );
END single_mux;
SINGLE AND DUAL 2-1 MULTIPLEXER ARCHITECTURE
ARCHITECTURE gate_level OF single_mux IS
COMPONENT c1 PORT (
i1 :IN BIT;
o1: OUT BIT);
END COMPONENT;
COMPONENT c2 PORT (
i1, i2 :IN BIT;
o1: OUT BIT);
END COMPONENT;
SINGLE AND DUAL 2-1 MULTIPLEXER ARCHITECTURE
COMPONENT c3 PORT (
i1, i2 :IN BIT;
o1: OUT BIT);
END COMPONENT;
FOR ALL: c1 USE ENTITY WORK.inv(single_delay);
FOR ALL: c2 USE ENTITY WORK.and2(single_delay);
FOR ALL: c3 USE ENTITY WORK.or2(single_delay);
SIGNAL im1, im2, im3: BIT;
SINGLE AND DUAL 2-1 MULTIPLEXER ARCHITECTURE
BEGIN
g0: c1 PORT MAP (s, im1);
g1: c2 PORT MAP (iA, im1, im2);
g2: c2 PORT MAP (iB, s, im3);
g3: c3 PORT MAP (im2, im3, oZ);
END gate_level;
DUAL 2-1 MULTIPLEXER ENTITY
ENTITY dual_mux IS
PORT(
s: IN BIT ; --select input
iA, iB : IN BIT _VECTOR(1 DOWNTO 0); -- iA is selected if --s=‘0’ and iB is selected if s= ‘1’
outZ: OUT BIT _VECTOR(1 DOWNTO 0)--output of the mux );
END dual_mux;
DUAL 2-1 MULTIPLEXER ARCHITECTURE
ARCHITECTURE element_level OF dual_mux IS
--we use only one component (the single 2:1 mux)
COMPONENT c1 PORT (s, iA, iB: IN BIT;
oZ : OUT BIT);
END COMPONENT;
FOR ALL : c1 USE ENTITY WORK. single_mux (gate_level);
BEGIN
g0 : c1 PORT MAP(sel, inA(0), inB(0), outZ(0)); --the 1st 2:1 mux is --wired.
g1 : c1 PORT MAP(sel, inA(1), inB(1), outZ(1)); --the 2nd 2:! Mux is --wired
END element_level;
BEHAVIORAL MODLEING
1. Show examples of a dual 2:1 multiplexer designed using behavioral models.
2. Initially components built are:
2- input AND gate
2- OR gate
Inverter
DIFFERENT METHODS OF BEHAVIORAL MODELING
1. WHEN …ELSE statements
2. BOOLEAN operators
3. PROCESSES
4. WITH … SELECT
5. CASE statements
WHEN – ELSE STATEMENT
ENTITY dual_mux IS
PORT(
sel: IN BIT ; --select input
iA, iB : INT BIT_VECTOR( 1 DOWN TO 0); -- iA is selected if --s=‘0’ and iB is selected if s= ‘1’
oZ: OUT BIT _VECTOR(1 DOWNTO 0)--output of the mux );
END dual_mux;
ARCHITECTURE behaioral_when_else OF dual_mux IS
BEGIN
outZ <= inA WHEN(sel = ‘0’) ELSE inB;
END behavioral_when_else;
BOOLEAN OPERATORS
ARCHITECTURE behavioral_boolean OF dual_mux IS
SIGNAL temp: BIT_VECTOR(1 downto 0);
BEGIN
temp <= (sel, sel);
--we assign sel to all the bits of the bus temp
outZ <= ((NOT) temp AND inA) OR (temp AND inB);
END behavioral_boolean;
PROCESS
1. A process is a block that contains only sequential statements.
2. Every process has a sensitivity list.
3. The signals in the sensitivity list determine when the sequential statements within the process will be executed.
PROCESS
ARCHITECTURE behavioral_process OF dual_mux IS
BEGIN
p1: PROCESS(sel, inA, inB) is
BEGIN
outZ <= inB;
if(sel = ‘0’) then
outZ <= inA;
End if;
END process p1;
END behavioral_process;
WITH ..SELECT STATEMENT
ARCHITECTURE behavioral_sel OF dual_mux IS
BEGIN
WITH sel SELECT
outZ <=
inA after 10 ns when ‘0’,
inB after 10 ns when others;
END behavioral_sel;
CASE STATEMENT
ARCHITECTURE behavioral_sel OF dual_mux IS
BEGIN
P1: PROCESS (sel, inA, inB) is
BEGIN
CASE sel is
when ‘0’ => outZ <= inA after 10 ns;
when others => outZ <= in B after 10 ns;
END CASE;
End process;
END behavioral_case;
TEST BENCHES
1. A VHDL block to test a design.
2. Example of a dual 2:1 multiplexer.
TEST BENCH
USE WORK. ALL;
ENTITY dual_mux_test IS
END dual_mux_test;
We do not need any interfacing since we only want to use the test-bench with the simulator.
TEST BENCH
ARCHITECTURE io_test OF dual_mux_test IS
COMPONENT c1 PORT(
sel: IN BIT;
inA, inB : IN BIT_VECTOR(1 downto 0);
outZ: OUT BIT_VECTOR(1 downto 0);
END COMPONENT;
SIGNAL sel_test: BIT;
SIGNAL inA_test, inB_test : BIT_VECTOR(1 downto 0);
SIGNAL outZ_test : BIT_VECTOR(1 downto 0);
TEST BENCH
BEGIN g0: c1 PORT MAP (sel_test, inA_test,inB_test, outZ_test); t1: inA_test <= “00”, “01” after 50 ns, “10” after 150 ns, “11” after 250 ns, “00” after 350 ns, “01” after 450 ns, “10” after 550 ns, “11” after 650 ns; t2: inB_test <= “00”, “01” after 100 ns, “10” after 200 ns, “11” after 300 ns, “00” after 400 ns, “01” after 500 ns, “10” after 600 ns, “11” after 700 ns, t3:sel_test <= ‘0’, ‘1’ after 325 ns; END io_test;
GENERIC CLAUSE
GENERIC allows us to communicate non-hardware and non-signal information between designs, and hence between levels of hierarchy. In the example discussed later, a delay is assigned a default value of 5ns but the delay can be changed when the component is used.
GENERIC CLAUSE
ENTITY decoder IS GENERIC ( delay: TIME := 5ns ); PORT ( sel: IN BIT_VECTOR(2 downto 0); outZ: OUT BIT_VECTOR(7 downto 0); ); END decoder; ARCHITECTURE single_delay OF decoder IS BEGIN
WITH sel SELECT outZ <= “00000001” after delay WHEN “000”, “00000010” after delay WHEN “001”, “00000100” after delay WHEN “010”, “00001000” after delay WHEN “011”, “00010000” after delay WHEN “100”, “00100000” after delay WHEN “101”, “01000000” after delay WHEN “110”, “10000000” after delay WHEN “111”, END single_delay;