ee 3563 vhsic hardware description language

Fall 2004 EE 3563 Digital Systems Design

EE 3563 VHSIC Hardware Description Language

Required Reading: – These Slides

– VHDL Tutorial

Very High Speed Integrated Circuit (VHSIC) VHSIC Hardware Description Language (VHDL)


EE 3563 VHDL

Used to model a digital system at numerous different levels– Algorithmic level to gate level to system level

Can express concurrent or sequential behavior, with or without timing

Models written in this language can be verified with simulation

The language is very complex, but we can focus on a small part and still make use of it

VHDL was constructed in the early 80’s as a DoD requirement– Many companies were making electronic components for DoD and

needed standardization in order to share designs– VHDL 7.2, was released in 1985– IEEE made it an industry standard in 1987– Book I have is based on 1993 standard


EE 3563 VHDL

Exchange medium between chip vendors and CAD tool users Communication medium between CAD and CAE tools

– Computer Automated Design, Computer Aided Engineering

– Schematic can be converted to VHDL for simulation Supports a hierarchy – one component can become a sub-component of a

larger system Not technology specific – can support many technologies Synchronous and Asynchronous models Supports finite state machines, algorithms, & boolean equations Publicly available, not proprietary IEEE and ANSI standard Three basic different description styles Wide range of abstraction levels, though not down to transistor level


EE 3563 VHDL

No limitations on design size imposed by VHDL Propagation delays, setup and hold timing, timing

constraints, and spike detection can all be modeled Tools that use VHDL code can work with designs from

multiple vendors since the language is a standard Behavioral models that conform to certain synthesis

description styles are able to be synthesized– The gate design can be generated from the behavior

There are other features, but this should give you an idea


EE 3563 VHDL Overview

A hardware abstraction is called an entity One entity, X, used inside another entity, Y, is called a

component VHDL has 5 primary constructs:

– Entity declaration– Architecture body– Configuration declaration– Package declaration– Package body

An entity has an entity declaration and at least one architecture body

The entity declaration describes the external view– An “AND” gate would have 2 inputs and 1 output – more later



The architecture body contains the internal description– Could be interconnected components representing the structure– Could be statements that represent the behavior– Each of these styles can be in a separate architecture body or mixed

A configuration declaration is used to specify the binding of one architecture body from the possibly multiple other architectures

It may also specify the bindings of components used in the architecture body to other entities

An entity may have multiple configurations A package declaration is a set of related declarations A package body contains the definitions associated with the

declarations– Ex: A course syllabus is the declaration, the actual course is the body



Once an entity is modeled, it must be validated by VHDL software which includes an analyzer and a simulator

The analyzer performs semantic checks and validates the syntax

Then it compiles the VHDL code into a library The simulator reads its compiled description from the design

library and then simulates the design It performs 3 steps

– Elaboration– Initialization– Simulation

NOTE: VHDL is case insensitive, so AND, and, AnD are the same


EE 3563 VHDL Example

The entity declaration specifies the name of the entity and it’s input/output ports

Ports are the signals that interface into and out of the entity Here is a half adder (why is it only a half adder?)

The name is: HALF_ADDER 4 ports: 2 input, 2 output They are of type BIT which means they can have one of two

different values, 0 or 1– The double dash indicates a comment



The schematic is just for our reference, so far, the only VHDL is the entity declaration

It says NOTHING about how HALF_ADDER works, its functionality or behavior

It ONLY specifies inputs and outputs– I made it bigger so you can see there is nothing else there

Three types of modeling: structural, dataflow, behavioral



Structural modeling of HALF_ADDER– this works in conjunction with the declaration

– an entity is described as a set of interconnected components

The architecture body is composed of two parts:– declarative part (after the keyword begin)

– the statement part (after the keyword begin)

In our case, two components are declared (XOR2, AND2)– they specify the interface of components used in the architecture

body

– They are either user-specified in their own entity declaration and architecture body or are used from the pre-defined library

They are instantiated in the statement part of the architecture body



The statement part of HALF_ADDER is inside the begin/end The X1 statement creates an instance of XOR2

– Many Dodge Vipers are made, but the one I own (1/100th scale) is a

specific instance of a Viper

The signals in the port map are associated with the signals of a component using positional association – (the X input for XOR2 is mapped to the A input of HALF_ADDER)



Dataflow modeling of HALF_ADDER The flow of data is expressed using concurrent signal

assignment statements Each assignment statement is executed at the same time

(concurrently) Order is NOT important SIDE NOTE:

– You may wonder how a computer simulation can do this? It can’t.

– However, we are talking about two different types of time.

– In real-time, the computer can only perform a single task at any given point, but here we mean the statements are executed in concurrently in simulated time.



Here is the dataflow model of HALF_ADDERarchitecture HA_CONCURRENT of HALF_ADDER is

begin

SUM <= A xor B after 8 ns;

CARRY <= A and B after 4 ns;

end HA_CONCURRENT;

The name is HA_CONCURRENT The signals SUM & CARRY get assigned (<= ) values Note the after statement, it specifies when the signal (in

simulated time) gets its new value If no after statement is given, then the default delay is used The default delay (0 ns) is called the delta delay and is a

number infinitesimally above zero



Behavioral style of modeling specifies the functionality of an entity with sequential statements

Order IS important, because one statement is executed (in simulated time) one right after the other

The statements are specified inside a process statement They only specify the functionality of an entity, NOT its

structure– Structure of XOR could be either

of these or some other design

– Example, could be a T-gate

implementation



Here is the behavior model of HALF_ADDERarchitecture HA_CONCURRENT of HALF_ADDER isbegin

process (A, B)begin

SUM <= A xor B;CARRY <= A and B;

end process;end HA_CONCURRENT;

Whenever there is an event on A or B, the process is executed

The sequential statements are executed regardless of whether an event occurs on the right hand side of their expression– In this case, an event must occur on A or B to get here, but this is not

the general case


EE 3563 VHDL Example: 2-to-4 Decoder

Now we will step through another example This is a 2-to-4 Decoder circuit, note the entity declaration BIT_VECTOR is another data type (it is an array of bits) Quiz: Entity name? # Inputs? # Outputs? Data types? How many components? How many instantiations?



Structural model of 2-to-4 Decoder



Dataflow model of 2-to-4 Decoder Note the signals: ABAR, BBAR of type BIT Concurrent or sequential? What time delay is used?



Behavioral model of 2-to-4 Decoder Concurrent or sequential? Note the variables ABAR, BBAR of type BIT

– Variables are different than signals in that they are assigned a value instantaneously ( := )

The process statement

also has declarative &

statement partsVariables are declared,

statements are within the

begin/end process statements

Scope is limited to process

in which variable is declared


EE 3563 VHDL Example: Flip-Flop

entity LS_DFF is -- declaration for level-sensitive flip-flopport(Q:out BIT; D, CLK:in BIT);

end LS_DFF

architecture LS_DFF_BEH of LS_DFF isbegin

process(D,CLK)begin

if CLK=‘1’ then -- if CLK is one, D is assigned to QQ <= D

end if;end process;

end LS_DFF_BEH;


EE 3563 VHDL Mixed Modeling

The three types of modeling can be combined within an architecture body– component instantiation – structural

– concurrent signal assignments – dataflow

– process statements – behavior

This is called the mixed style of modeling


EE 3563 VHDL

FULL ADDER

ee 3563 vhsic hardware description language

Documents

entitiesan entity

entityone entity

separate architecture

vhdl code

vhdl overviewonce

vhdl software

gate level

multiple vendors