ee 201a modeling and optimization for vlsi layoutjeff wong and dan vasquez ee 201a noise modeling...
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![Page 1: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/1.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
EE 201ANoise Modeling
Jeff Wong and Dan Vasquez
Electrical Engineering Department
University of California, Los Angeles
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MEMS Research Laboratory Joe Zendejas and Jack W. Judy
Efficient Coupled Noise Estimation for On-Chip Interconnects
Anirudh Devgan
Austin Research Laboratory
IBM Research Division, Austin TX
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Motivation
• Noise failure can be more severe than timing failure– Difficult to control from chip terminals– Expensive to correct (refabrication)
• Circuit or timing simulation (like SPICE) can be used– Linear reduction techniques can be applied for
linearly modeled circuits• i.e. moment matching methods
– Inefficient for noise verification and avoidance applications
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Noise Estimation
• The paper presents an electrical metric for efficiently estimating coupled noise for on-chip interconnects
• Capacitive coupling between an aggressor net and a victim net leads to coupled noise– Aggressor net: switches states; source of
noise for victim net– Victim net: maintains present state; affected by
coupled noise from aggressor net
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Schematic
Switching signal
Vs(t)
Coupling capacitors
CC = [CC,ii]
C1 = [C1,ii]
C2 = [C2,ii]
• Let’s analyze the case for one aggressor net and one victim net
V2,1 V2,n
V1,1 V1,n
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Equations
• Coupled equation for circuit:
• In Laplace domain:
1 1 111 12 1
2 2 221 22 2
dC dt
sdC dt
C C v t v tA A Bv t
C C v t v tA A B
1 11 12 11 1
2 21 22 22 2
Cs
C
C C A A BsV s V sV s
C C A A BsV s V s
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Equations
• Aggressor net:
• Victim net:
1 1 2 11 1 12 2 1
1
1 1 11 12 2 1
C s
C s
sC V sC V A V A V BV
V sC A A sC V BV
1 2 2 21 1 22 2 2
1
2 2 22 21 1 2
C s
C s
sC V sC V A V A V B V
V sC A A sC V B V
![Page 8: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/8.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Transfer Function
• Transfer function:
• Simplifications (details later):
• Simplified transfer function:
1
21 1 11 1 221
2 22 21 1 11 12
C
s C C
A sC sC A B BVH s
V sC A A sC sC A A sC
12 21 20, 0, 0A A B
1
1 11 122 1
2 22 1 11
C
s C
sC sC A BVH s
V sC A sC sC A
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Simplifications
• A12 = 0
– No resistive (or DC) path exists from the aggressor net to the victim net
• A21 = 0
– No resistive (or DC) path exists from the victim net to the aggressor net
• B2 = 0
– No resistive (or DC) path exists from the voltage/noise source to the victim net
![Page 10: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/10.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Maximum Induced Noise
• H(s=0) = 0– Coupling between aggressor and victim
net is purely capacitive–Maximum induced noise can be
computed
• Assume Vs is a finite or infinite ramp
– max2 2lim 0 is finited
dttV V
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
• Final value theorem:
–
• Ramp input u(s):–
–
–
1
1 11 1max2 2 10
2 22 1 11
lim C
sC
C sC A BV u
sC A sC sC A
Maximum Induced Noise
max2 2 2
0lim limt s
V v t sV s
max2 20 0 0
lim lim lims s s
H suV sH s u s sH s u
s s
max 1 12 22 11 1CV A C A B u
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Interpretation
max 1 12 22 11 1CV A C A B u
Switching slope
1ssV
CI
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations(matrix method)
• Step 1: Compute– Requires circuit analysis of the
aggressor net
• Step 2: Compute– Requires a matrix multiplication
• Step 3: Compute– Requires circuit analysis of the victim
net
11 11 1ssV A B u
1ss
C CI C V
max 12 22 CV A I
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations(by inspection)
• Step 1: Compute– Aggressor circuit transformation:
• Replace input source with it’s derivative• Replace aggressor net’s capacitors with
open circuits
11 11 1ssV A B u
![Page 15: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/15.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations (by inspection)
• Step 1: Compute– Typical interconnects:• Negligible loss: no resistive path to ground
•
11 11 1ssV A B u
1ss
sV V
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations (by inspection)
• Step 2: Compute– Convert steady state derivative on the
aggressor net to a current on the victim net
–
– i : index of node on the victim net– j : index of node on the aggressor net
1ss
C CI C V
, 1ss
C i C ij jj
I I C V
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations (by inspection)
• Step 3: Compute– Victim circuit transformation:
• Replace capacitors with coupling currents• The voltage at each node corresponds to
that node’s maximum induced noise
max max 12 22 CN V A I
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations (by inspection)
• Step 3: Compute– Typical interconnects:• Compute by inspection in linear time
•
max max 12 22 CN V A I
max max max1
i
C i i j iL
V V R I N
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Circuit Computations (by inspection)
• Step 3: Compute– 3RC Circuit example:
max max 12 22 CN V A I
max max1
i
i i j iL
N R I N
max1 1 1 2 3N R I I I
max2 1 1 2 3 2 2N R I I I R I
max1 1 1 2 3 3 3N R I I I R I
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Computation Costs
• Step 1:– No computation required
• Step 2:
– Simple multiplications
• Step 3:
– Simple multiplications
• Multiple aggressor nets:– Coupling currents from step 2
determined from a linear superposition
1ss
sV V
, 1ss
i C ij jj
I C V
max max1
i
i i j iL
N R I N
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Experiment
• Typical small RC interconnect structure– Rise time of 200 ps or 100 ps– Power supply voltage of 1.8 V– Conventional circuit simulation vs.
proposed metric– Run-time comparisons for various
circuit sizes
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Accuracy Results
Node Circuit Simulation Proposed Metric % Error1 0.0084 0.0084 0.00%2 0.016 0.016 0.00%3 0.0227 0.0227 0.00%4 0.0286 0.0286 0.00%5 0.0336 0.0336 0.00%6 0.0378 0.0379 0.26%7 0.0412 0.0412 0.00%8 0.0437 0.0438 0.23%9 0.0454 0.0454 0.00%10 0.0462 0.0463 0.22%
• 10 nodes, 200 ps rise time
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Accuracy Results
• 10 nodes, 100 ps rise time
Node Circuit Simulation Proposed Metric % Error1 0.0147 0.0168 7.73%2 0.0277 0.0319 13.10%3 0.0392 0.0454 13.65%4 0.0492 0.0572 13.98%5 0.0578 0.0673 14.11%6 0.0651 0.0757 14.00%7 0.0709 0.0824 13.95%8 0.0752 0.0875 14.05%9 0.0782 0.0908 13.87%10 0.0797 0.0925 13.83%
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Accuracy Results
• Metric accuracy degrades with reduction in rise times
• Metric estimation is more conservative than circuit model’s– Fast rise times don’t allow circuit to reach
ramp steady state noise
• Loading of interconnect normally does not allow for very small rise times– Metric accuracy should be acceptable for
many applications
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Run-time Results
Circuit Number
Number of Elements
Arnoldi Model Reduction
Proposed Metric (Matrix
Method)
Proposed Metric (By
Inspection)
1 500 .2s .00s .00s2 5,000 5.86s .07s .01s3 50,000 145s 3.44s .05s4 500,000 - 360.55s .35s
• Arnoldi-based model reduction used a matrix solution to compute circuit response– Requires repeated factorizations, eigenvalue
calculations, and time exponential evaluations
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Conclusions
• The proposed metric determines an upper bound on coupled noise for RC and over-damped RLC interconnects–Metric becomes less accurate as rise
time decreases
• The proposed metric is much more run-time efficient than circuit modeling methods
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MEMS Research Laboratory Joe Zendejas and Jack W. Judy
Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Department of Computer Science, UCLAMagma Design Automation, Inc.
2 Results Way, Cupertino, CA 95014
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Motivation• Deep sub-micron net designs have higher
aspect ratio (h/w)– Increased coupling capacitance between nets• Longer propagation delay• Increased logic errors --- Noise
• Reduced noise margins– Lower supply voltages– Dynamic Logic
• Crosstalk cannot be ignored
![Page 29: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/29.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Aggressor
Victim
Aggressor / Victim Network
• Assuming idle victim net– Ls: Interconnect length before coupling
– Lc: Interconnect length of coupling
– Le: Interconnect length after coupling
• Aggressor has clock slew tr
![Page 30: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/30.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
2- Model• Victim net is modeled as 2 -RC circuits
• Rd: Victim drive resistance
• Cx is assumed to be in middle of Lc
Rise timevictim / aggressor
coupling capacitance
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Aggressor
Victim
2- Model Parameters
2e
L l
CC C 1 2
sCC 2 2
s eC CC
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Analytical Solution
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Analytical Solution part 2• s-domain output voltage
• Transform function H(s)
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Analytical Solution part 3• Aggressor input signal
• Output voltage
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Simplification of Closed Form Solution
• Closed form solution complicated
• Non-intuitive– Noise peak amplitude, noise width?
• Dominant-pole simplification
![Page 36: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/36.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Dominant-Pole Simplification
RC delay from upstream resistance of coupling element
Elmore delay of victim net
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Intuition of Dominant Pole Simplification
• vout rises until tr and decays after
• vmax evaluated at tr
![Page 38: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/38.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Extension to RC Trees
• Similar to previous model with addition of lumped capacitances
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Results• Average errors of 4%
• 95% of nets have errors less than 10%
![Page 40: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/40.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Spice Comparison
peak noise noise width
![Page 41: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/41.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Effect of Aggressor Location• As aggressor is moved close to receiver,
peak noise is increased
Ls varies from 0 to 1mm
Lc has length of 1mm
Le varies from 1mm to 0
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Optimization Rules• Rule 1: – If RsC1 < ReCL • Sizing up victim driver will reduce peak
noise
– If RsC1 > ReCL and tr << tv
• Driver sizing will not reduce peak noise
• Rule 2:– Noise-sensitive victims should avoid
near-receiver coupling
![Page 43: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/43.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Optimization Rules part 2• Rule 3:– Preferred position for shield insertion is near a
noise sensitive receiver
• Rule 4:– Wire spacing is an effective way to reduce
noise
• Rule 5:– Noise amplitude-width product has lower
bound
– And upper bound
![Page 44: EE 201A Modeling and Optimization for VLSI LayoutJeff Wong and Dan Vasquez EE 201A Noise Modeling Jeff Wong and Dan Vasquez Electrical Engineering Department](https://reader033.vdocuments.site/reader033/viewer/2022052504/551b23c9550346cf5a8b59b1/html5/thumbnails/44.jpg)
EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
Conclusions
• 2- model achieves results within 6% error of HSPICE simulation
• Dominant node simplification gives intuition to important parameters
• Design rules established to reduce noise
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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez
References
• Anirudh Devgan, “Efficient Coupled Noise Estimation for On-chip Interconnects”, ICCAD, 1997.
• J. Cong, Z. Pan and P. V. Srinivas, “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization”, Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico Yokohama, Japan.