edpga chapter 1 - upb · embedded design using programmable gate arrays chapter 1 verilog verilog...

Chapter 1Chapter 1

Verilog HardwareVerilog HardwareDescription LanguageDescription Language

Embedded Design using Programmable Gate ArraysChapter 1

VerilogVerilog

Verilog was invented by Verilog was invented by Phil Phil MoorbyMoorby and and PrabhuPrabhu GoelGoel in in 1985 as a proprietary hardware modeling language. 1985 as a proprietary hardware modeling language. Verilog came into the public domain under the Verilog came into the public domain under the Open Open Verilog InternationalVerilog International (OVI) organization. Verilog was later (OVI) organization. Verilog was later submitted to submitted to IEEEIEEE and became and became IEEEIEEE Standard 1364Standard 1364--1995, commonly referred to as 1995, commonly referred to as VerilogVerilog--9595..

Extensions to VerilogExtensions to Verilog--95 were submitted95 were submittedto cover the deficiencies that users hadto cover the deficiencies that users hadfound in the original Verilog standard.found in the original Verilog standard.These extensions became These extensions became IEEEIEEEStandard 1364Standard 1364--2001 also known as2001 also known asVerilogVerilog--20012001..

Embedded Design using Programmable Gate Arrays Chapter 1

VerilogVerilog

VerilogVerilog--20052005 ((IEEEIEEE Standard 1364Standard 1364--2005) consists of 2005) consists of minor corrections, clarifications, and a few new language minor corrections, clarifications, and a few new language features.features.

SystemVerilogSystemVerilog ((IEEEIEEE standard P1800standard P1800--2005) is a 2005) is a supersetsupersetof Verilogof Verilog--2005, with many new features and capabilities 2005, with many new features and capabilities to aid designto aid design--verification and designverification and design--modeling.modeling.


Verilog Number FormatVerilog Number Format. Integer numbers are specified . Integer numbers are specified as <as <sign>sign><<sizesize><><base formatbase format><><numbernumber>.>. If the <If the <sizesize> is > is not given, then the number of bits is a default minimum of not given, then the number of bits is a default minimum of 32.32.

Listing 1.7Listing 1.7 Examples of valid and invalid integer number formats in VeriloExamples of valid and invalid integer number formats in Verilogg

138138 // decimal number, 32 bit as 00000000000000000000000010001010// decimal number, 32 bit as 000000000000000000000000100010101010′′d138d138 // decimal number, 10 bit as 0010001010// decimal number, 10 bit as 001000101066′′o74o74 // octal number, 6 bits as 111100// octal number, 6 bits as 1111002424′′h25Fh25F // hexadecimal number, 24 bit as 000000000000001001011111// hexadecimal number, 24 bit as 00000000000000100101111188′′hxBhxB // hexadecimal number, 8 bit as xxxx1011// hexadecimal number, 8 bit as xxxx101133′′b010b010 // binary number, 3 bits as 010// binary number, 3 bits as 010--66′′b101b101 // 6 bit, two// 6 bit, two’’s complement of 000101 or 111011s complement of 000101 or 111011--1010′′d15d15 // 10 bit, two// 10 bit, two’’s complement of 0000001111 or 1111110001s complement of 0000001111 or 111111000155′′d124d124 // decimal number, 5 bits as 11100 since 7 bits are required// decimal number, 5 bits as 11100 since 7 bits are required1212′′oF2oF2 // invalid, F is not a octal digit// invalid, F is not a octal digit


Verilog Number FormatVerilog Number Format. The <. The <base formatbase format> consist of > consist of an apostrophe ( ' ) followed by an apostrophe ( ' ) followed by b b (binary, base(binary, base--2), 2), d d (decimal, base(decimal, base--10), 10), oo (octal, base(octal, base--8) or 8) or h h (hexadecimal, (hexadecimal, basebase--16) for integer numbers. If the <16) for integer numbers. If the <base formatbase format> is not > is not used, the base is assumed to be decimal. used, the base is assumed to be decimal.

Listing 1.7Listing 1.7 Examples of valid and invalid integer number formats in VeriloExamples of valid and invalid integer number formats in Verilogg

138138 // decimal number, 32 bit as 00000000000000000000000010001010// decimal number, 32 bit as 000000000000000000000000100010101010′′d138d138 // decimal number, 10 bit as 0010001010// decimal number, 10 bit as 001000101066′′o74o74 // octal number, 6 bits as 111100// octal number, 6 bits as 1111002424′′h25Fh25F // hexadecimal number, 24 bit as 000000000000001001011111// hexadecimal number, 24 bit as 00000000000000100101111188′′hxBhxB // hexadecimal number, 8 bit as xxxx1011// hexadecimal number, 8 bit as xxxx101133′′b010b010 // binary number, 3 bits as 010// binary number, 3 bits as 010--66′′b101b101 // 6 bit, two// 6 bit, two’’s complement of 000101 or 111011s complement of 000101 or 111011--1010′′d15d15 // 10 bit, two// 10 bit, two’’s complement of 0000001111 or 1111110001s complement of 0000001111 or 111111000155′′d124d124 // decimal number, 5 bits as 11100 since 7 bits are required// decimal number, 5 bits as 11100 since 7 bits are required1212′′oF2oF2 // invalid, F is not a octal digit// invalid, F is not a octal digit


Verilog ConstantsVerilog Constants. Constants in Verilog are declared . Constants in Verilog are declared with the keyword with the keyword parameterparameter and can include arithmetic and can include arithmetic expressions with other constants. The keyword expressions with other constants. The keyword defparamdefparamis used to redefine a parameter within a module. The is used to redefine a parameter within a module. The redefinition can be specifically applied to the parameters redefinition can be specifically applied to the parameters of a specific (M2) nested module (of a specific (M2) nested module (auxbusauxbus).).

Listing 1.8 Listing 1.8 Constant Constant parameter parameter declaration and declaration and defparamdefparam redefinition with in redefinition with in VerilogVerilog

parameter BUS_WIDTH = 32;parameter BUS_WIDTH = 32; // integer// integerparameter XMAX=640, YMAX = 480;parameter XMAX=640, YMAX = 480; // integers// integersparameter START_VALUE = 8parameter START_VALUE = 8′′b00001111;b00001111; // register// registerparameter SIZE = XMAX*YMAX;parameter SIZE = XMAX*YMAX; // arithmetic expression// arithmetic expressiondefparamdefparam auxbus.M2.BUS_WIDTH = 16;auxbus.M2.BUS_WIDTH = 16; // redefinition of BUS// redefinition of BUS--WIDTH in WIDTH in

// instance M2 of nested // instance M2 of nested // module // module auxbusauxbus


Verilog WireVerilog Wire. The net variable type . The net variable type wirewire establishes establishes behavioral connectivity with logic values of 0, 1, behavioral connectivity with logic values of 0, 1, x x (unknown) or (unknown) or zz (high impedance) determined by the (high impedance) determined by the module module portport that drives the signal variable.that drives the signal variable.

Listing 1.9 Listing 1.9 Net variable Net variable wire wire declaration in Verilogdeclaration in Verilog

wire wire glbrstglbrst;; // scalar net signal // scalar net signal wire wire mclkmclk, , davdav;; // scalar net signals// scalar net signalswire [31:0] average;wire [31:0] average; // 32// 32--bit vector net signalbit vector net signalwire [0:7] wire [0:7] adc_valueadc_value;; // 8// 8--bit vector net signal, reversed MSBbit vector net signal, reversed MSB


Verilog Register VariablesVerilog Register Variables. Register variables are used . Register variables are used in behavioral modeling, are assigned values by procedural in behavioral modeling, are assigned values by procedural statements and store information. Register variables that statements and store information. Register variables that are used in a Verilog HDL behavioral description are are used in a Verilog HDL behavioral description are declared by the keywords declared by the keywords reg reg and and integerinteger..

The keyword The keyword regreg is the abstraction of a hardware storage is the abstraction of a hardware storage element and has a default size of one bit and an initial element and has a default size of one bit and an initial logic value of logic value of xx (unknown).(unknown).

Listing 1.10Listing 1.10 Register variable Register variable reg reg declaration in Verilogdeclaration in Verilog

reg clock;reg clock; // register signal// register signalreg reset, read_data;reg reset, read_data; // register signals// register signalsreg signed [7:0] sum;reg signed [7:0] sum; // 7// 7--bit plus sign register signalbit plus sign register signalreg [15:0] accum;reg [15:0] accum; // 16// 16--bit register signal, reversed MSBbit register signal, reversed MSB


Verilog Register VariablesVerilog Register Variables. The integer type of register . The integer type of register variable supports numerical computation in Verilog variable supports numerical computation in Verilog behavioral synthesis. Integer variables are declared by behavioral synthesis. Integer variables are declared by the keyword the keyword integerinteger, have a default but fixed size of 32 , have a default but fixed size of 32 bits in signed twobits in signed two’’s complement format and a default initial s complement format and a default initial value of zero.value of zero.

Integers are Integers are true abstractionstrue abstractions that must have a numerical that must have a numerical value, but the procedures that they comprise are compiled value, but the procedures that they comprise are compiled by the Verilog HDL to synthesizable hardware.by the Verilog HDL to synthesizable hardware.

Listing 1.11Listing 1.11 Register variable integer declaration in Verilog

integer data; // integer integer i, j, k; // multiple integersinteger data[1:1000] // integer array


Verilog String VariablesVerilog String Variables. Verilog utilizes the register . Verilog utilizes the register variable with the variable with the regreg declaration to store ASCII character declaration to store ASCII character strings as 8strings as 8--bit values. The string can be initially assigned bit values. The string can be initially assigned to the register variable to the register variable regreg declaration by enclosing it declaration by enclosing it within quotation marks.within quotation marks.

If the string assignment uses less than the available If the string assignment uses less than the available number of bits, the unused register variable number of bits, the unused register variable regregdeclaration bits are filled with zero.declaration bits are filled with zero.

Listing 1.12Listing 1.12 String and memory register variable String and memory register variable reg reg declaration in Verilogdeclaration in Verilog

parameter STRING_LENGTH = 11;parameter STRING_LENGTH = 11; // parameter declaration// parameter declarationreg [8 * STRING_LENGTH] reg [8 * STRING_LENGTH] string_datastring_data;; // arithmetic calculation of size// arithmetic calculation of sizereg [7:0] reg [7:0] byte_memorybyte_memory [0:511];[0:511]; // MSB bit first, 512 byte memory// MSB bit first, 512 byte memorystrdatastrdata = = ””hello worldhello world””;; // string assignment to a register// string assignment to a register


Verilog String VariablesVerilog String Variables. The assignment of a string to a . The assignment of a string to a register variable with the register variable with the regreg declaration is a single declaration is a single address address memorymemory. Multiple addressable register variables . Multiple addressable register variables of the same size can be accommodated with the format of the same size can be accommodated with the format <<word size>word size><<variable namevariable name><><memory sizememory size>.>.


parameter STRING_LENGTH = 11;parameter STRING_LENGTH = 11; // parameter declaration// parameter declarationreg [8 * STRING_LENGTH] reg [8 * STRING_LENGTH] string_datastring_data;; // arithmetic calculation of size// arithmetic calculation of sizereg [7:0] reg [7:0] byte_memorybyte_memory [0:511];[0:511]; // MSB bit first, 512 byte memory// MSB bit first, 512 byte memorystrdatastrdata = = ””hello worldhello world””;; // string assignment to a register// string assignment to a registerlcddata[7:0] = strdata[ilcddata[7:0] = strdata[i--:8]; :8]; // variable selection of a register// variable selection of a registerlcddata[7:0] = strdata[87:80]; lcddata[7:0] = strdata[87:80]; // fixed selection of a register// fixed selection of a registerreg [3:0] data = {adata[1:0], bdata[1:0]};reg [3:0] data = {adata[1:0], bdata[1:0]}; // concatenation// concatenation


Verilog String VariablesVerilog String Variables. Verilog supports the selection . Verilog supports the selection of a word or the contiguous part of a word for net or of a word or the contiguous part of a word for net or register variables with the part select operators (<register variables with the part select operators (<start bitstart bit> > +: <+: <widthwidth> and <> and <start bitstart bit> > ––: <: <widthwidth>). The parameter >). The parameter width width specifies the size of the selection which is obtained specifies the size of the selection which is obtained by either incrementing ( +: ) or decrementing ( by either incrementing ( +: ) or decrementing ( ––: ) the : ) the index of the bits in the register. The integer registerindex of the bits in the register. The integer registervariable i sets the parameter variable i sets the parameter start bit start bit as the starting as the starting position for the selection.position for the selection.


lcddata[7:0] = strdata[ilcddata[7:0] = strdata[i--:8]; :8]; // variable selection of a register// variable selection of a registerlcddata[7:0] = strdata[87:80]; lcddata[7:0] = strdata[87:80]; // fixed selection of a register// fixed selection of a registerreg [3:0] data = {adata[1:0], bdata[1:0]};reg [3:0] data = {adata[1:0], bdata[1:0]}; // concatenation// concatenation


Verilog Array VariablesVerilog Array Variables. Although Verilog supports . Although Verilog supports multidimensional array, the Xilinx ISE WebPACK EDA multidimensional array, the Xilinx ISE WebPACK EDA software tool only supports arrays with no more than three software tool only supports arrays with no more than three dimensions. dimensions.

Listing 1.13Listing 1.13 Multidimensional arrays and word selection in Verilog 2001Multidimensional arrays and word selection in Verilog 2001

reg [7:0] reg [7:0] pix_datapix_data [0:639] [0:479];[0:639] [0:479]; // two dimensional array of bytes// two dimensional array of byteswire [7:0] wire [7:0] pixoutpixout [120] [330];[120] [330]; // fixed word of pixel (120,330)// fixed word of pixel (120,330)wire wire msb_pixmsb_pix = = pix_datapix_data [120] [330] [7];[120] [330] [7]; // MSB of pixel (120,330)// MSB of pixel (120,330)


Verilog Bitwise Signal OperationsVerilog Bitwise Signal Operations. Verilog provides . Verilog provides intrinsic signal operations which describe logic intrinsic signal operations which describe logic symbolically in behavioral synthesis, rather than by symbolically in behavioral synthesis, rather than by Verilog primitives in a structural model which utilize Verilog primitives in a structural model which utilize combinational logic gates.combinational logic gates.

The The bitwisebitwise operators combine two signal operands to operators combine two signal operands to form a signal result.form a signal result.

Table 1.1Table 1.1 Bitwise operations in VerilogBitwise operations in Verilog

~~ NegationNegation (one(one’’s complement)s complement)&& AndAnd|| Inclusive OrInclusive Or^̂ Exclusive OrExclusive Or~ ^~ ^ Exclusive Not OrExclusive Not Or^ ~^ ~ Exclusive Not OrExclusive Not Or


Verilog Reduction OperationsVerilog Reduction Operations. The . The reduction reduction operators operators produce a scalar with logic values of 0, 1, or produce a scalar with logic values of 0, 1, or x x (unknown) (unknown) from a single signal operand. Each bit of the signal from a single signal operand. Each bit of the signal operand participates in the reduction operation to produce operand participates in the reduction operation to produce the result. For example, if x = 1001, then &x = 0 and |x = the result. For example, if x = 1001, then &x = 0 and |x = 1. The scalar value is 1. The scalar value is x x (unknown) if the operand contains (unknown) if the operand contains at least a single bit which is unknown.at least a single bit which is unknown.

Table 1.2Table 1.2 Reduction operations in VerilogReduction operations in Verilog

&& AndAnd~ &~ & Not AndNot And|| OrOr~ |~ | Not OrNot Or^̂ Exclusive OrExclusive Or~ ^~ ^ Exclusive Not OrExclusive Not Or^ ~^ ~ Exclusive Not OrExclusive Not Or


Verilog Relational OperationsVerilog Relational Operations. The . The relationalrelational operators operators compare two signal operands and produce a scalar with compare two signal operands and produce a scalar with logic values of 0 (false), 1 (true), or logic values of 0 (false), 1 (true), or x x (unknown).(unknown).

The scalar value is The scalar value is x x (unknown) if either operand contains (unknown) if either operand contains at least a single bit which is unknown or at least a single bit which is unknown or zz (high (high impedance).impedance).

Table 1.3Table 1.3 Relational operations in VerilogRelational operations in Verilog

<< Less ThanLess Than< =< = Less Than or Equal ToLess Than or Equal To>> Greater ThanGreater Than> => = Greater Than or Equal ToGreater Than or Equal To


Verilog Equality OperationsVerilog Equality Operations. The . The logical equalitylogical equality and and logical inequality logical inequality operators compare two signal operands operators compare two signal operands bitbit--byby--bit bit and produce a scalar with logic values of 0 and produce a scalar with logic values of 0 (false), 1 (true), or (false), 1 (true), or x x (unknown).(unknown).

The scalar value is The scalar value is x x (unknown) if the operand contains at (unknown) if the operand contains at least a single bit which is unknown or least a single bit which is unknown or z z (high impedance).(high impedance).

Table 1.4Table 1.4 Equality operations in VerilogEquality operations in Verilog

= = == = = Case EqualityCase Equality! = =! = = Case InequalityCase Inequality= == = Logical EqualityLogical Equality! = ! = Logical InequalityLogical Inequality


Verilog Equality OperationsVerilog Equality Operations. The . The case equalitycase equality and and case inequalitycase inequality operators compare two signal operands operators compare two signal operands bitbit--byby--bitbit utilizing the four logic values (0, 1, utilizing the four logic values (0, 1, xx, , zz) and ) and produce a scalar with logic values of 0 (false) and 1 (true).produce a scalar with logic values of 0 (false) and 1 (true).

Table 1.4Table 1.4 Equality operations in VerilogEquality operations in Verilog

= = == = = Case EqualityCase Equality! = =! = = Case InequalityCase Inequality= == = Logical EqualityLogical Equality! = ! = Logical InequalityLogical Inequality


Verilog Logical OperationsVerilog Logical Operations. The . The logicallogical operators are operators are similar to the reduction operators but produce a scalar similar to the reduction operators but produce a scalar with logic values of 0, 1, or with logic values of 0, 1, or x x (unknown) from two signal (unknown) from two signal operands. Each bit of the two signal operands operands. Each bit of the two signal operands participates in the logical operation to produce the result.participates in the logical operation to produce the result.

Table 1.5Table 1.5 Logical operations in VerilogLogical operations in Verilog

& && & Logical AndLogical And| || | Logical OrLogical Or!! Logical NegationLogical Negation


Verilog Logical OperationsVerilog Logical Operations. For example, if x = 1001 . For example, if x = 1001 and y = 0110 then x && y = 0 and x || y = 1.and y = 0110 then x && y = 0 and x || y = 1.

The scalar value is The scalar value is x x (unknown) if either of the operands (unknown) if either of the operands contains at least a single bit which is unknown. The contains at least a single bit which is unknown. The operation is evaluated from left to right and ends as soon operation is evaluated from left to right and ends as soon as result is unequivocally true or false.as result is unequivocally true or false.

Table 1.5Table 1.5 Logical operations in VerilogLogical operations in Verilog

& && & Logical AndLogical And| || | Logical OrLogical Or!! Logical NegationLogical Negation


Verilog Logical Shift OperationsVerilog Logical Shift Operations. The logical shift . The logical shift operator shifts the bits in a signal operand to the right or operator shifts the bits in a signal operand to the right or left and fills the vacated bits with a logic value of 0.left and fills the vacated bits with a logic value of 0.

For example, if x = 10011100 then x << 2 = 01110000.For example, if x = 10011100 then x << 2 = 01110000.

Table 1.6Table 1.6 Logical shift operations in VerilogLogical shift operations in Verilog

> >> > Logical Shift RightLogical Shift Right< << < Logical Shift LeftLogical Shift Left


Verilog Arithmetic Shift OperationsVerilog Arithmetic Shift Operations. Verilog supports . Verilog supports the arithmetic shift operator which shifts the bits in a signal the arithmetic shift operator which shifts the bits in a signal to the right or left and fills the vacated bits with the most to the right or left and fills the vacated bits with the most significant bit (MSB) if a right shift and a logic value of 0 ifsignificant bit (MSB) if a right shift and a logic value of 0 ifa left shift.a left shift.

For example, if x = 10011100 then x >>> 2 = 11100111. For example, if x = 10011100 then x >>> 2 = 11100111. The left shift arithmetic operator is functionally the same The left shift arithmetic operator is functionally the same as the left shift logical operator.as the left shift logical operator.

Table 1.7Table 1.7 Arithmetic shift operations in VerilogArithmetic shift operations in Verilog

> > >> > > Arithmetic Shift RightArithmetic Shift Right< < << < < Arithmetic Shift LeftArithmetic Shift Left


Verilog Arithmetic OperationsVerilog Arithmetic Operations. The common arithmetic . The common arithmetic operations in Verilog manipulate the register variable operations in Verilog manipulate the register variable reg reg declaration as signed or unsigned integers of any bit size. declaration as signed or unsigned integers of any bit size.

The keyword The keyword signed signed is used to declare that the register is used to declare that the register variable variable reg reg declaration is signed. The register variable declaration is signed. The register variable integerinteger declaration has a default but fixed size of 32 bits declaration has a default but fixed size of 32 bits for signed twofor signed two’’s complement arithmetic.s complement arithmetic.

Table 1.8Table 1.8 Arithmetic operations in VerilogArithmetic operations in Verilog

** MultiplicationMultiplication// DivisionDivision%% ModulusModulus++ AdditionAddition–– SubtractionSubtraction


Verilog Conditional OperationsVerilog Conditional Operations. The conditional . The conditional operation in Verilog can utilize the logic true or false of a operation in Verilog can utilize the logic true or false of a Boolean expression to select one of two possible Boolean expression to select one of two possible arithmetic expressions.arithmetic expressions.

The form of the conditional operation is:The form of the conditional operation is:<<Boolean expressionBoolean expression> ? <> ? <result if trueresult if true> : <> : <result if falseresult if false>.>.

Listing 1.14 Listing 1.14 Conditional operation in VerilogConditional operation in Verilog

reg signed [15:0] c;reg signed [15:0] c;reg signed [7:0] a;reg signed [7:0] a;reg signed [7:0] b;reg signed [7:0] b;

c = (a > b) ? 1 : 0;c = (a > b) ? 1 : 0; // c will be either 1 or 0// c will be either 1 or 0c = (a == b) ? a c = (a == b) ? a –– b : a + b;b : a + b; // c will be either a // c will be either a –– b or a + bb or a + bc = (a c = (a –– b) > 4 ? a : b;b) > 4 ? a : b; // c will be either a or b// c will be either a or b


Verilog Nested Modules. Verilog Nested Modules. Modules can be Modules can be nested nested or or called multiple times. Unlike subroutines each separate called multiple times. Unlike subroutines each separate instance is evoked in hardware. The Verilog structural instance is evoked in hardware. The Verilog structural model for a combinational model for a combinational halfhalf--adderadder is shown. is shown.

Listing 1.15 Listing 1.15 Verilog structural model of a 1Verilog structural model of a 1--bit adder with carrybit adder with carry

module module half_add(outputhalf_add(output sum, carry, input a, b); sum, carry, input a, b);

xor (sum, a, b);xor (sum, a, b); // exclusive OR// exclusive ORand (carry, a ,b);and (carry, a ,b); // and// and

endmoduleendmodule


Verilog Modules. Verilog Modules. The Verilog structural or behavioral The Verilog structural or behavioral model consists of declarations beginning with the keyword model consists of declarations beginning with the keyword modulemodule and ending with the keyword and ending with the keyword endmoduleendmodule..

The declarations specify the signal inputs and outputs of The declarations specify the signal inputs and outputs of the model at the the model at the port port and the manipulation of the signals and the manipulation of the signals using the Verilog operations.using the Verilog operations.




endmoduleendmodule


Verilog Modules. Verilog Modules. The module name is case sensitive The module name is case sensitive and the names and the names half_adderhalf_adder and and Half_adderHalf_adder are assumed are assumed by the Verilog compiler to be different modules.by the Verilog compiler to be different modules.




endmoduleendmodule


Verilog Nested Modules. Verilog Nested Modules. Modules can be nested using Modules can be nested using the the connection by positionconnection by position in the definition. in the definition.

Listing 1.16Listing 1.16 Verilog nested structural model of a 1Verilog nested structural model of a 1--bit fullbit full--adder with carry adder with carry with port with port connection by positionconnection by position

module module full_add(outputfull_add(output sum_outsum_out, , carry_outcarry_out, input , input a_ina_in, , b_inb_in, , carry_incarry_in); );

wire w1, w2, w3;wire w1, w2, w3;

half_addhalf_add M1 (w1, w2, M1 (w1, w2, a_ina_in, , b_inb_in););half_addhalf_add M2 (M2 (sum_outsum_out, w3, , w3, carry_incarry_in, w1);, w1);or (or (carry_outcarry_out, w2, w3);, w2, w3);

endmoduleendmodule


Verilog Nested Modules. Verilog Nested Modules. Modules can be nested using Modules can be nested using the the connection by name connection by name in the definition using the in the definition using the dot dot (.) (.) notation notation

Listing 1.17Listing 1.17 Verilog nested structural model of a 1Verilog nested structural model of a 1--bit fullbit full--adder with carry adder with carry with port with port connection by nameconnection by name

module module full_add(outputfull_add(output sum_outsum_out, , carry_outcarry_out, input , input a_ina_in, , b_inb_in, , carry_incarry_in); );

wire w1, w2, w3;wire w1, w2, w3;

half_addhalf_add M1 (.M1 (.a(a_ina(a_in), .sum(w1), .), .sum(w1), .b(b_inb(b_in), .carry(w2));), .carry(w2));half_addhalf_add M2 (.M2 (.sum(sum_outsum(sum_out), .b(w1), .carry(w3), .), .b(w1), .carry(w3), .a(carry_ina(carry_in));));or (or (carry_outcarry_out, w2, w3);, w2, w3);

endmoduleendmodule


Verilog Control Flow. Verilog Control Flow. The case statement is used The case statement is used extensively for control flow and for finite state machines extensively for control flow and for finite state machines (FSM).(FSM).

Listing 1.28Listing 1.28 Verilog behavioral model of a four channel multiplexer using tVerilog behavioral model of a four channel multiplexer using the he casecase statementstatement

module mux4ch (output reg data, input [1:0] select, input a, b, module mux4ch (output reg data, input [1:0] select, input a, b, c, d);c, d);

always@(aalways@(a or b or c or d or select)or b or c or d or select)case (select)case (select)

0: data = a;0: data = a;1: data = b;1: data = b;2: data = c;2: data = c;3: data = d;3: data = d;default data = 1default data = 1′′bz;bz;

endcaseendcaseendmoduleendmodule


Verilog Control Flow. Verilog Control Flow. The The for for loop is used with a nonloop is used with a non--register variable to form a repetitive flow.register variable to form a repetitive flow.

Listing 1.30 Listing 1.30 Verilog behavioral model of an odd parity generator using theVerilog behavioral model of an odd parity generator using thefor loopfor loop constructconstruct

module module oddparity_foroddparity_for (output reg parity, input [7:0] data);(output reg parity, input [7:0] data);integer k;integer k;always@(data)always@(data)

beginbeginparity = 1;parity = 1;for (k = 0; k <= 7; k = k+1) for (k = 0; k <= 7; k = k+1) beginbegin

if (if (data[kdata[k] == 1)] == 1)parity = ~parity;parity = ~parity;

endendendend

endmoduleendmodule


Verilog Control Flow. Verilog Control Flow. The The repeatrepeat loop is similar but uses loop is similar but uses a constant expression.a constant expression.

Listing 1.31 Listing 1.31 Verilog behavioral model of an odd parity generator using theVerilog behavioral model of an odd parity generator using therepeat looprepeat loop constructconstruct

module module oddparity_repeatoddparity_repeat (output reg parity, input [7:0] data);(output reg parity, input [7:0] data);integer k;integer k;always@(data)always@(data)

beginbeginparity = 1;parity = 1;k = 0;k = 0;repeat (8) repeat (8)

beginbeginif (if (data[kdata[k] == 1)] == 1)

parity = ~parity;parity = ~parity;k = k + 1;k = k + 1;

endendendend

endmoduleendmodule


Verilog Nested Modules. Verilog Nested Modules. The The while while looploop construct is construct is similar to the C language. similar to the C language.

Listing 1.32 Listing 1.32 Verilog behavioral model of a gated clock generator using theVerilog behavioral model of a gated clock generator using thewhile loopwhile loop constructconstruct

module module gated_clockgated_clock (output reg (output reg gclkgclk, input , input clkclk, , clkgateclkgate););

always@(clkalways@(clk or or clkgateclkgate))beginbegin

while (while (clkgateclkgate))gclkgclk = = clkclk;;

endend

endmoduleendmodule


Verilog FunctionVerilog Function

Listing 1.33 Listing 1.33 Verilog module with a function which returns the greater of two Verilog module with a function which returns the greater of two 88--bit signed variablesbit signed variables

module greater (input signed [7:0] a, b, output reg signed [7:0]module greater (input signed [7:0] a, b, output reg signed [7:0] c); c); always @(a, b)always @(a, b)

beginbeginc = great(a, b);c = great(a, b);

endend

function [7:0] great (input signed [7:0] x, y); function [7:0] great (input signed [7:0] x, y); begin begin

if (x >= y)if (x >= y)great = x;great = x;

elseelsegreat = y;great = y;

end end endfunctionendfunctionendmoduleendmodule


Verilog TaskVerilog Task

Listing 1.34 Listing 1.34 Verilog module of a 1Verilog module of a 1--bit full adder with a task implementing two bit full adder with a task implementing two 11--bit half addersbit half adders

module module full_add(outputfull_add(output reg sum, output reg reg sum, output reg carry_outcarry_out, input a, b,, input a, b, carry_incarry_in); ); reg reg psumpsum, p1carry, p2carry;, p1carry, p2carry;always@(aalways@(a, b, , b, carry_incarry_in))

beginbeginhalf_adder(psum, p1carry, b, carry_in);half_adder(psum, p1carry, b, carry_in);half_adder(sum, p2carry, psum, a);half_adder(sum, p2carry, psum, a);carry_out=p1carry | p2carry;carry_out=p1carry | p2carry;

endend

task half_adder(output half_sum, half_carry, input x, y); task half_adder(output half_sum, half_carry, input x, y); begin begin

half_sum=x ^ y;half_sum=x ^ y;half_carry=x & y;half_carry=x & y;

end end endtaskendtaskendmoduleendmodule


Finite State Machines (FSM)Finite State Machines (FSM)

Figure 1.5Figure 1.5



Xilinx Xilinx StateCADStateCAD graphical interface for state machine graphical interface for state machine design.design. Figure 1.7Figure 1.7


Arbitrary Moore FSMArbitrary Moore FSM




Listing 1.39 Listing 1.39 Verilog HDL of the arbitrary Moore FSMVerilog HDL of the arbitrary Moore FSM

reg [2:0] state; reg [2:0] state;

always@(posedgealways@(posedge CLOCK)CLOCK)beginbegin

if (RESET)if (RESET)beginbeginstate <= 1;state <= 1;X <= 0;X <= 0;

Y <= 0;Y <= 0;Z <= 0;Z <= 0;

endendelseelse



case (state) case (state) 1: begin1: begin

if (A | | B)if (A | | B)state <= 2;state <= 2;

X <= 0;X <= 0;Y <= 0;Y <= 0;Z <= 0;Z <= 0;

endend2: begin2: begin

if (!A && C)if (!A && C)state <= 1;state <= 1;

else if (A && D)else if (A && D)state <= 3;state <= 3;

X <= 1;X <= 1;Y <= 1;Y <= 1;Z <= 0;Z <= 0;

endend



3: begin3: beginif (!A | | !C)if (!A | | !C)

state <= 5;state <= 5;else if (A && C)else if (A && C)

state <= 4;state <= 4;X <= 0;X <= 0;Y <= 0;Y <= 0;Z <= 1;Z <= 1;


if (D)if (D)state <= 5;state <= 5;

X <= 0;X <= 0;Y <= 1;Y <= 1;Z <= 0;Z <= 0;

endend



5: begin5: beginif (!B && D)if (!B && D)

state <= 3;state <= 3;else if (B)else if (B)

state <= 1;state <= 1;X <= 1;X <= 1;Y <= 0;Y <= 0;Z <= 0;Z <= 0;

endenddefault: state <= 1;default: state <= 1;

endcaseendcase

endend


ControllerController--Datapath Construct. Datapath Construct. The The datapathdatapath is the is the module that inputs andmodule that inputs andoutputs data. The datapathoutputs data. The datapathaccepts control signalsaccepts control signalsfrom and returns statusfrom and returns statussignals to the controller. signals to the controller.



ControllerController--Datapath Construct. Datapath Construct. The The controllercontroller acceptsacceptscontrol inputs (stimuli) fromcontrol inputs (stimuli) fromand provides status outputand provides status outputsignals to other modules. signals to other modules.



C to Verilog Translation. C to Verilog Translation. C language assignment and C language assignment and loop statement construct.loop statement construct.



C to Verilog Translation. C to Verilog Translation. C language branch statement C language branch statement construct.construct.



C to Verilog Translation. C to Verilog Translation. Greatest common denominator Greatest common denominator (GCD) algorithm.(GCD) algorithm.

Listing 1.40 Listing 1.40 Greatest common denominator C language algorithmGreatest common denominator C language algorithm

int int gcdgcd (int (int xinxin, int yin), int yin){{int x, y;int x, y;

x = x = xinxin;;y = yin;y = yin;while(xwhile(x != y)!= y)

{{if (x < y)if (x < y)

y = y y = y –– x;x;elseelse

x = x x = x –– y;y;}}

return x;return x;}}


C to Verilog Translation.C to Verilog Translation.FSM for the greatestFSM for the greatestcommon denominatorcommon denominator(GCD) algorithm.(GCD) algorithm.



C to Verilog Translation.C to Verilog Translation.Verilog controllerVerilog controller--datapath construct for thedatapath construct for thegreatest commongreatest commondenominatordenominator(GCD) algorithm.(GCD) algorithm.



C to Verilog Translation. C to Verilog Translation. GCD controller module.GCD controller module.

Listing 1.41Listing 1.41 Greatest common denominator C language algorithm Verilog Greatest common denominator C language algorithm Verilog controller modulecontroller module

module module gcdcontrollergcdcontroller (input clock, (input clock, gcddatagcddata, , lddatalddata, , xneqyxneqy, , xltyxlty, input , input xysubxysub, , yxsubyxsub, output , output gcdinitgcdinit, , datagcddatagcd, , datalddatald, , subxysubxy, , subyxsubyx) )

reg [2:0] reg [2:0] gcdstategcdstate;;

always@(posedgealways@(posedge clock)clock)beginbegin

if (if (gcddatagcddata == 0)== 0)beginbegin

gcdstategcdstate = 1;= 1;datagcddatagcd = 0;= 0;gcdinitgcdinit = 1;= 1;datalddatald = 0;= 0;

endendelseelse



elseelsecase(gcdstatecase(gcdstate))

1: begin1: begingcdinitgcdinit = 0;= 0;datalddatald = 1;= 1;if (if (lddatalddata))

beginbegindatalddatald = 0;= 0;gcdstategcdstate = 2;= 2;

endendendend

2: begin2: beginif (if (xneqyxneqy))

gcdstategcdstate = 3;= 3;elseelse

gcdstategcdstate = 6;= 6;endend



3: begin3: beginif (if (xltyxlty))

gcdstategcdstate = 4;= 4;elseelse

gcdstategcdstate = 5;= 5;endend4: begin4: begin

subyxsubyx=1;=1;if (if (yxsubyxsub))

beginbeginsubyxsubyx = 0;= 0;gcdstategcdstate = 2;= 2;

endendendend



5: begin5: beginsubxysubxy = 1;= 1;if (if (xysubxysub))

beginbeginsubxysubxy = 0;= 0;gcdstategcdstate = 2;= 2;

endendendend

6: begin6: begindatagcddatagcd = 1;= 1;gstategstate = 6;= 6;

endenddefault: default: gstategstate = 6;= 6;

endcaseendcaseendend

endmoduleendmodule


C to Verilog Translation. C to Verilog Translation. GCD datapath module.GCD datapath module.

Listing 1.42Listing 1.42 Greatest common denominator C language algorithm Verilog Greatest common denominator C language algorithm Verilog datapath moduledatapath module

module module gcddatapathgcddatapath (input clock, (input clock, gcdinitgcdinit, , datagcddatagcd, , datalddatald, input , input subxysubxy, , subyxsubyx, , output output lddatalddata, output , output xneqyxneqy, , xltyxlty, , xysubxysub, , yxsubyxsub, , inoutinout [15:0] [15:0] xdataxdata, , input signed input signed ydataydata))

reg [15:0] x;reg [15:0] x;reg [15:0] y;reg [15:0] y;always@(posedge clock)always@(posedge clock)

beginbeginif (if (gcdinitgcdinit))

beginbeginlddatalddata = 0;= 0;xneyxney = 0;= 0;xltyxlty = 0;= 0;xysubxysub = 0;= 0;yxsubyxsub = 0;= 0;

endend



if (if (datalddatald))beginbegin

x = x = xdataxdata;;y = y = ydataydata;;if (x != y)if (x != y)

xneyxney = 1;= 1;if (x < y)if (x < y)

xltyxlty = 1;= 1;lddatalddata = 1;= 1;

endendif (if (subxysubxy))

beginbeginx = x x = x –– y;y;if (x == y)if (x == y)

xneyxney=0;=0;if (x < y)if (x < y)

xltyxlty = 1;= 1;xysubxysub = 1;= 1;

endend



if (if (subyxsubyx))beginbegin

y = y y = y –– x;x;if (x == y)if (x == y)

xneyxney = 0;= 0;if (x < y)if (x < y)

xltyxlty = 1;= 1;yxsubyxsub = 1;= 1;

endend

if (if (datagcddatagcd))xdataxdata = x;= x;

endendendmoduleendmodule


PGA and Microprocessor Comparison. PGA and Microprocessor Comparison. Verilog Verilog modules can operate in parallel facilitating realmodules can operate in parallel facilitating real--time time operation.operation.

Listing 1.43 Listing 1.43 Verilog HDL modules operating in parallel in an embedded Verilog HDL modules operating in parallel in an embedded design applicationdesign application

s3eadc M0 (CCLK, s3eadc M0 (CCLK, adcdavadcdav, , davadcdavadc, adc0data, adc1data, , adc0data, adc1data, adcsckadcsck, , adcspodadcspod, , conadconad););

adclcdadclcd M2 (CCLK, BTN0, M2 (CCLK, BTN0, resetlcdresetlcd, , clearlcdclearlcd, , homelcdhomelcd, , datalcddatalcd, , addrlcdaddrlcd, , initlcdinitlcd, , lcdresetlcdreset, , lcdclearlcdclear, , lcdhomelcdhome, , lcddatalcddata, , lcdaddrlcdaddr, , lcddatinlcddatin, , digitmuxdigitmux, data);, data);

lcdlcd M3 (CCLK, M3 (CCLK, resetlcdresetlcd, , clearlcdclearlcd, , homelcdhomelcd, , datalcddatalcd, , addrlcdaddrlcd, , lcdresetlcdreset, , lcdclearlcdclear, , lcdhomelcdhome, , lcddatalcddata, , lcdaddrlcdaddr, , rslcdrslcd, , rwlcdrwlcd, , elcdelcd, lcdd, , lcdd, lcddatinlcddatin, , initlcdinitlcd););

genampadcgenampadc M4 (CCLK, SW0, SW1, SW2, SW3, M4 (CCLK, SW0, SW1, SW2, SW3, ampdavampdav, , davampdavamp, , ampcmd0, ampcmd1, ampcmd0, ampcmd1, adcdavadcdav, , davadcdavadc, adc0data, adc1data, , adc0data, adc1data, digitmuxdigitmux, data);, data);


PGA and Microprocessor ComparisonPGA and Microprocessor Comparison

Listing 1.44Listing 1.44 Sequential processor data transfer in ASMSequential processor data transfer in ASM--86 for the Intel 808686 for the Intel 8086

sdatosdato proc nearproc near ;SDATA from ;SDATA from bxbx to DACto DACmovmov ax,400H ax,400H ;IOW 400H;IOW 400Hmovmov dx,axdx,axmovmov cl,12 cl,12 ;count for 12 SDATA bits;count for 12 SDATA bits

sdatlpsdatlp: : rolrol bx,1bx,1movmov al,blal,bland al,1 and al,1 ;SDATA bit 0, SCLK=0 bit 1;SDATA bit 0, SCLK=0 bit 1out out dx,aldx,alor al,2 or al,2 ;SDATA bit 0, SCLK=1 bit 1 ;SDATA bit 0, SCLK=1 bit 1 out out dx,aldx,aland al,0FDH and al,0FDH out out dx,aldx,al ;SDATA bit 0, SCLK=0 bit 1;SDATA bit 0, SCLK=0 bit 1decdec clcl ;decrement count;decrement countjnzjnz sdatlpsdatlp ;jump if count is not zero;jump if count is not zeroretret

sdatosdato endpendp


PGA and Microprocessor Comparison. PGA and Microprocessor Comparison. Verilog Verilog controllercontroller--datapath construct for the data transfer.datapath construct for the data transfer.



PGA and Microprocessor Comparison. PGA and Microprocessor Comparison. Data transfer Data transfer datapath module.datapath module.

Listing 1.45Listing 1.45 Verilog datapath module for the data transferVerilog datapath module for the data transfer

module sdat0(input clock, module sdat0(input clock, dacdavdacdav, input [11:0] data, output reg , input [11:0] data, output reg sdatasdata, output , output reg reg sclksclk, output reg , output reg davdacdavdac););

reg [1:0] reg [1:0] dacstatedacstate;;integer i;integer i;

always@(posedge clock)always@(posedge clock)beginbegin

if (if (dacdavdacdav == 0)== 0)beginbegin

i = 12;i = 12;dacstatedacstate = 0;= 0;sclksclk = 1;= 1;

endend



elseelsebeginbegin

davdacdavdac = 0;= 0;case (case (dacstatedacstate))

0: begin0: begini = i i = i –– 1;1;if (i == 0)if (i == 0)

dasstatedasstate = 3;= 3;elseelse

sdatasdata = = data[idata[i –– 1];1];dacstatedacstate = 1;= 1;

endend



1: begin1: beginsclksclk = 0;= 0;dacstatedacstate = 2;= 2;


sclksclk = 1;= 1;dacstatedacstate = 0;= 0;


davdacdavdac = 1;= 1;dacstatedacstate = 3;= 3;

endendendcaseendcase

endendendendendmoduleendmodule

End of Chapter 1End of Chapter 1

Verilog HardwareVerilog HardwareDescription LanguageDescription Language

edpga chapter 1 - upb · embedded design using programmable gate arrays chapter 1 verilog verilog...

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