Haeng Kon KimSio-Iong AoMahyar A. AmouzegarBurghard B. RiegerEditors

IAENG Transactions on Engineering Technologies

Lecture Notes in Electrical Engineering 247

Special Issue of the World Congress on Engineering and Computer Science 2012

Lecture Notes in Electrical Engineering

Volume 247

For further volumes:http://www.springer.com/series/7818

Haeng Kon Kim • Sio-Iong AoMahyar A. Amouzegar •

Burghard B. RiegerEditors

IAENG Transactions onEngineering Technologies

Special Issue of the World Congress onEngineering and Computer Science 2012

123

EditorsHaeng Kon KimEngineering College, Department of

Computer and CommunicationCatholic University of DaeGuDaeGuKorea, Republic of South Korea

Sio-Iong AoInternational Association of EngineersHong KongHong Kong SAR

Mahyar A. AmouzegarCollege of EngineeringCalifornia State Polytechnic UniversityPomona, CAUSA

Burghard B. RiegerInst. Computerlinguistik, Abt. Linguistische

DatenverarbeitungUniversität TrierTrierGermany

ISSN 1876-1100 ISSN 1876-1119 (electronic)ISBN 978-94-007-6817-8 ISBN 978-94-007-6818-5 (eBook)DOI 10.1007/978-94-007-6818-5Springer Dordrecht Heidelberg New York London

Library of Congress Control Number: 2013945283

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Preface

A large international conference on Advances in Engineering Technologies andPhysical Science was held in San Francisco, California, USA, October 24–26,2012, under the World Congress on Engineering and Computer Science (WCECS2012). The WCECS 2012 is organized by the International Association of Engi-neers (IAENG). IAENG is a non-profit international association for engineers andcomputer scientists, which was founded originally in 1968 and has been under-going rapid expansions in the recent years. The WCECS congress serves as anexcellent platform for the engineering community to meet with each other and toexchange ideas. The congress has also struck a balance between theoretical andapplication development. The conference committees have been formed with over200 members who are mainly research center heads, deans, department heads/chairs, professors, and research scientists from over 30 countries. The full com-mittee list is available at the congress’ web site: www.iaeng.org/WCECS2012/committee.html. The congress is truly an international meeting with a high level ofparticipation from many countries. The response to the conference call for paperswas excellent with more than 800 manuscript submissions for WCECS 2012. Allsubmitted papers went through the peer review process and the overall acceptancerate was 53.16 %.

This volume contains 49 revised and extended research articles, written byprominent researchers participating in the conference. Topics covered includecircuits, engineering mathematics, control theory, communications systems, sys-tems engineering, manufacture engineering, computational biology, chemicalengineering and industrial applications. This book offers the state of art of tre-mendous advances in engineering technologies and physical science and appli-cations, and also serves as an excellent source of reference for researchers andgraduate students working with/on engineering technologies and physical scienceand applications.

Haeng Kon KimSio-Iong Ao

Mahyar A. AmouzegarBurghard B. Rieger

v

Contents

1 A 480 MHz Band-Pass Sigma Delta Analog to DigitalModulator with Active Inductor Based Resonators . . . . . . . . . . . 1Kevin Dobson, Shahrokh Ahmadi and Mona Zaghloul

2 Basic Computations Using a Novel ScalablePulse-Mode Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Thamira Hindo

3 Hardware Implementation of Microprogrammed ControllerBased Digital FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Syed Manzoor Qasim and Mohammed S. BenSaleh

4 Drude-Lorentz Model of Semiconductor Optical Plasmons. . . . . . 41Mohamed Eldlio, Franklin Che and Michael Cada

5 Optimal Power Conversion of Standalone Wind EnergyConversion Systems Using Fuzzy Adaptive Control . . . . . . . . . . . 51Hoa M. Nguyen and D. Subbaram Naidu

6 Design of Augmented Observer for Rotor Systems. . . . . . . . . . . . 67Zhentao Wang, Rudolf Sebastian Schittenhelmand Stephan Rinderknecht

7 Cooperative Tasks Using Teams of Mobile Robots. . . . . . . . . . . . 83Ignacio Mas and Christopher Kitts

8 An Optimized, Authenticated Key Distribution Protocolfor Optical Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Sara Abozied, Hassan Elkamchouchi, Yasmine Abouelseoudand Refaat El-Attar

9 Adaptive Controller Design for Two-LinkFlexible Manipulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Rasheedat Modupe Mahamood

vii

10 Fuzzy Adaptive Control for a Class of Non-Affine SystemsBased on Singular Perturbation Theory . . . . . . . . . . . . . . . . . . . 129Daoxiang Gao, Dunmin Lu and ZengQi Sun

11 Using Multi-Agent Systems for Hardware Upgrade Advicein Smart Grid Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Ala Shaabana, Sami Syed, Ziad Kobti and Kemal Tepe

12 Ballistic Behaviour in Bounded Velocity Transport . . . . . . . . . . . 155F. Debbasch, D. Espaze and V. Foulonneau

13 Fuzzy Logic Control Versus Traditional PI Control Appliedto a Fixed Speed Horizontal Axis Wind Turbine . . . . . . . . . . . . . 167Luis Alberto Torres Salomao, Hugo Gámez Cuatzin,Juan Anzurez Marín and Isidro Ignacio Lázaro Castillo

14 Linear Quadratic Regulation of a Rotating Shaft BeingSubject to Gyroscopic Effect Using a GeneticOptimization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183Rudolf Sebastian Schittenhelm, Matthias Borsdorf,Zhentao Wang and Stephan Rinderknecht

15 Adaptive Control System for Solution of FaultTolerance Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Yuri A. Vershinin

16 Multiple Direction-of-Arrival Estimation for a MobileRobotic Platform with Small Hardware Setup . . . . . . . . . . . . . . . 209Caleb Rascon and Luis Pineda

17 Analysis of Metallic Plume Image Characteristics DuringHigh Power Disk Laser Welding . . . . . . . . . . . . . . . . . . . . . . . . . 225Xiangdong Gao, Runlin Wang, Yingying Liu and Yongchen Yang

18 Accurate Spectral Estimation of Non-periodic SignalsBased on Compressive Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . 241Isabel M. P. Duarte, José M. N. Vieira, Paulo J. S. G. Ferreiraand Daniel Albuquerque

19 Stereoscopic 3D Adjustment Under SpecificCapture Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Tzung-Han Lin

viii Contents

20 Cursive Handwritten Text Document PreprocessingMethodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Neeta Nain and Subhash Panwar

21 Tracing Malicious Injected Threads Using AlkanetMalware Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Yuto Otsuki, Eiji Takimoto, Takehiro Kashiyama, Shoichi Saito,Eric W. Cooper and Koichi Mouri

22 Syntatic and Semantic Taxonomy of PreferentialVoting Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301Sung-Hyuk Cha and Yoo Jung An

23 High Assurance Enterprise Scaling Issues . . . . . . . . . . . . . . . . . . 317William R. Simpson and Coimbatore Chandersekaran

24 The ACROSS Integrity Model . . . . . . . . . . . . . . . . . . . . . . . . . . 333Armin Wasicek

25 Modeling of the Stress Distribution in TemporomandibularJoint with Subtotal Replacement . . . . . . . . . . . . . . . . . . . . . . . . . 349Josef Danek, Tatjana Dostálová, Milan Hubácek,Nima Mahdian and Jirí Nedoma

26 Fault-Tolerant Optimization for Application-SpecificNetwork-on-Chip Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 363Farnoosh Hosseinzadeh, Nader Bagherzadeh,Ahmad Khademzadeh and Majid Janidarmian

27 Improved Anytime D* Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 383Weiya Yue, John Franco, Weiwei Cao and Qiang Han

28 Scheduling of Real-Time Networks with a ColumnGeneration Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397Ernst Althaus, Sebastian Hoffmann, Joschka Kupilasand Eike Thaden

29 A Unifying Framework for Parallel Computing . . . . . . . . . . . . . . 413Victor Eijkhout

30 Improving Network Intrusion Detection with ExtendedKDD Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431Edward Paul Guillén, Jhordany Rodríguez Parraand Rafael Vicente Paéz Mendez

Contents ix

31 On the Numerical Solutions of Boundary Value Problemsin the Plane for the Electrical Impedance Equation:A Pseudoanalytic Approach for Non-Smooth Domains . . . . . . . . . 447Cesar Marco Antonio Robles Gonzalez,Ariana Guadalupe Bucio Ramirez, Marco Pedro Ramirez Tachiquinand Victor Daniel Sanchez Nava

32 An Ontology-Based Methodology for Buildingand Matching Researchers’ Profiles . . . . . . . . . . . . . . . . . . . . . . 455Nawarat Kamsiang and Twittie Senivongse

33 Automated Attention Analysis Across Brands and Culturesin Online Beer Marketing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469Tomáš Kincl, Michal Novák, Pavel Štrach and Michal Charvát

34 Inspiring Creative Minds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Anjum Zameer Bhat

35 Mitigating Rural E-Learning Sustainability ChallengesUsing Cloud Computing Technology . . . . . . . . . . . . . . . . . . . . . . 497S. A. Odunaike, O. O. Olugbara and S. O. Ojo

36 Information Harvest from Social Network Data(Facebook 100 million URLS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 513P. Nancy and R. Geetha Ramani

37 Human Gait Modeling and Statistical Registrationfor the Frontal View Gait Data with Applicationto the Normal/Abnormal Gait Analysis . . . . . . . . . . . . . . . . . . . . 525Kosuke Okusa and Toshinari Kamakura

38 Statistical Recognition of Aspiration Presence . . . . . . . . . . . . . . . 541Shuhei Inui, Kosuke Okusa, Kurato Maeno and Toshinari Kamakura

39 Classification of Hyperspectral Images Using MachineLearning Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555Bolanle Tolulope Abe, Oludayo O. Olugbara and Tshilidzi Marwala

40 Evaluating the Effect of Single and Combined ClimateModes on Rainfall Predictability . . . . . . . . . . . . . . . . . . . . . . . . . 571Fatemeh Mekanik and Monzur Alam Imteaz

x Contents

41 A Simplex-Crossover-Based Multi-ObjectiveEvolutionary Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583Claudio Comis Da Ronco and Ernesto Benini

42 Efficient Operational Management of Enterprise File Serverwith File Size Distribution Model . . . . . . . . . . . . . . . . . . . . . . . . 599Toshiko Matsumoto, Takashi Onoyama and Norihisa Komoda

43 Dispersed Software Environment in Virtual Prototypingof Underground Mining Mechanical Systems. . . . . . . . . . . . . . . . 611Jaroslaw Tokarczyk

44 An Integrated Approach Based on 2-Tuple Fuzzy Representationand QFD for Supplier Selection . . . . . . . . . . . . . . . . . . . . . . . . . 621Mehtap Dursun and E. Ertugrul Karsak

45 Development of a Novel Approach for Electricity Forecasting . . . 635Mehdi K. Moghaddam and Parisa A. Bahri

46 Energy Consumption of Biodiesel Production from MicroalgaeOil Using Homogeneous and Heterogeneous Catalyst . . . . . . . . . . 651Nezihe Azcan and Ozlem Yilmaz

47 Detrended Fluctuation Analysis: An Experiment Aboutthe Neural-Regulation of the Heart and Motor Vibration. . . . . . . 665Toru Yazawa and Yukio Shimoda

48 Identification of Diabetic Neuropathic Conditions of SimulatedUlnar Nerve Response Using Prony’s Method . . . . . . . . . . . . . . . 683V. Sajith, A. Sukeshkumar and Jinto Jacob

49 Despeckling of Ultrasound Images of Bone FractureUsing RADWT Based Non-Linear Filtering . . . . . . . . . . . . . . . . . 697Deep Gupta, Radhey Shyam Anand and Barjeev Tyagi

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

Contents xi

Chapter 1A 480 MHz Band-Pass Sigma DeltaAnalog to Digital Modulator with ActiveInductor Based Resonators

Kevin Dobson, Shahrokh Ahmadi and Mona Zaghloul

Abstract This chapter presents a 480 MHz, continuous time, 6th order band-passSigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. Wereplace traditional RLC circuits, containing spiral inductors with high qualityfactor, active inductor based resonators utilizing negative impedance circuits. Thisreduces chip area and eliminates post processing needs. Pad to pad simulation ofthe extracted layout in Cadence yields an enhanced SNDR of 70 dB and powerconsumption of 29 mW. The modulator occupies 0.5 mm2 of chip area.

Keywords Active inductor � Analog to digital converter � Negative impedancecircuit � Sigma delta � Sixth order

1.1 Introduction

Analog to Digital Converters (ADCs) allow us to convert analog signals to digitalrepresentations suitable for processing by a digital computer. Sigma-Delta (RD)modulators utilize the processes of oversampling and noise shaping in order toobtain high Signal to Noise Ratios (SNR). RD modulators utilize a few criticalcomponents and produce high accuracy results [1]. These are highly desirable

K. Dobson (&) � S. Ahmadi � M. ZaghloulDepartment of Electrical and Computer Engineering, George Washington University,801 22nd Street NW, Washington DC 20052, USAe-mail: kdobson@gwu.edu

S. Ahmadie-mail: ahmadi@gwu.edu

M. Zaghloule-mail: zaghloul@gwu.edu

H. K. Kim et al. (eds.), IAENG Transactions on Engineering Technologies,Lecture Notes in Electrical Engineering 247, DOI: 10.1007/978-94-007-6818-5_1,� Springer Science+Business Media Dordrecht 2014

1

attributes. The relationship between the SNR measured at the output of a RDmodulator and the effective number of bits (ENOB) is given by:

SNR ¼ 6:02ENOBþ 1:76 ð1:1Þ

Continuous Time (CT) RD modulators offer inherent antialiasing and are ableto operate at higher frequencies than their discrete time counterparts.

In Radio Frequency (RF) receivers an incoming signal is repeatedly filtered andmixed down to lower frequencies before being digitized and processed. A CTband-pass RD modulator capable of digitizing an RF carrier signal would eliminatethe need for analog filtering and mixing, and these functions would be passed on toa Digital Signal Processor (DSP). This results in a simpler, cheaper and moreefficient receiver [2].

1.2 Design of Continuous Time Sigma Delta Modulator

The general architecture of a CT RD modulator is shown in Fig. 1.1. Whendesigning the loop filter G(s) for a CT RD modulator we begin with a discrete timemodulator transfer function F(z).

Once F(z) has been chosen the impulse invariant method can be used todetermine the equivalent CT loop filter G(s) as outlined in Lelandais-Perrault et al.[3]. For modulators with a non-return-to-zero (NRZ) feedback we get:

FðzÞ ¼ ð1� z�1ÞZTfL�1½GðsÞe�ds

s�g ð1:2Þ

Here d represents the delay introduced by the ADC and Digital to AnalogConverter (DAC). For a sixth order band-pass Sigma Delta modulator theequivalent continuous time loop filter transfer function is of the form:

GðsÞ ¼ðs� aÞðs2 þ xa

Qa sþ x2aÞðs2 þ xb

Qb sþ x2bÞ

ðs2 þ x0Q0

sþ x20Þðs2 þ x1

Q1sþ x2

1Þðs2 þ x2Q2

sþ x22Þ

ð1:3Þ

x is the normalized resonator frequency with respect to the sampling frequency inradians per second, and Q is the quality factor of the resonators. The samplingfrequency is T. When d is equal to 1.4 T and the sample rate is 4 times the frequencyof the input signal then the term a in the numerator approximates to zero [4].

Fig. 1.1 Continuous timesigma delta modulator

2 K. Dobson et al.

1.3 Active Inductor Resonator Structure

A parallel RLC resonator is shown in Fig. 1.2.The transfer function of a parallel RLC circuit resonator H(s) is given by:

HðsÞ ¼ As

s2 þ x0Q þ x2

0

where x0 ¼1ffiffiffiffiffiffi

LCp and Q ¼ RPCx0 ¼

RP

Lx0ð1:4Þ

G(s) cannot be realized as a cascade of resonators but can be realized by thestructure in Fig. 1.3. Here g, AH and AL represent amplifier gains, and H theresonators. The R block is an analog adder.

Traditionally resonators for band-pass CT RD modulators have been realized byRLC parallel circuits with spiral inductors. Such circuits occupy a large siliconarea. Spiral inductors also have low quality factors. Active inductor based RLCcircuits occupy a much smaller area, and when Q enhancement techniques areused, high quality factors can be achieved.

Fig. 1.2 RLC resonator

Fig. 1.3 Sixth order active inductor based loop filter

1 A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator 3

The active inductor based resonator is explained by the gyrator C theorem asshown in Fig. 1.4.

I0 ¼ �VinGm1 ð1:5Þ

�Iin ¼ V 0Gm2 ð1:6Þ

V 0 ¼ I01

sCð1:7Þ

After substitution we get:

Vin

Iin¼ sC

Gm1Gm2ð1:8Þ

In Eq. (1.8) we note that the s is in the numerator indicating that the circuit isinductive. Gm1 and Gm2 can be realized using CMOS devices.

The circuit in Fig. 1.5 realizes an active inductor with M1 and M2 acting asGm1 and Gm2 respectively.

A detailed small signal analysis results in an expression for Zin as shown in Eq.(1.9) below [5].

Fig. 1.4 Gyrator topology

Fig. 1.5 CMOS activeinductor

4 K. Dobson et al.

Zin ¼goc þ go1 þ sðCgs2 þ Cgd2 þ Cds1Þ

gm1gm2 þ ½gm2 � gm1 þ goc þ sðCgs2 þ Cds1Þ�ðgo2 þ sCgd2Þð1:9Þ

Here go is the drain-source conductance and goc represents the loading effect ofthe non-ideal biasing current source. Zin can be interpreted to represent the parallelRLC circuit as shown in Fig. 1.2.

Separating the Resistive, Capacitive and inductive parts of Eq. (1.9) yields thefollowing:

Rp ¼1

gm1ð1:10Þ

Cp ¼ Cgs1 ð1:11Þ

Lp ¼Cgs2

gm1gm2ð1:12Þ

Rs ¼goc þ go1

gm1gm2ð1:13Þ

The intrinsic self-resonant frequency and intrinsic quality factor of the circuit isgiven respectively by:

x0 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

gm1gm2

Cgs1Cgs2

r

ð1:14Þ

Q0 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

gm2Cgs1

gm1Cgs2

s

ð1:15Þ

By utilizing two similar circuits to that in Fig. 1.5 and a Negative ImpedanceCircuit (NIC), a high Q fully differential resonator can be designed for use in aband-pass RD modulator. This resonator is shown in Fig. 1.6. Output buffers areused but not shown.

A PMOS device is used to couple the input to the circuit. It draws a smallamount of current and does not disturb the gyrator function. Output gain can becontrolled by varying the size of this MOSFET. The effect of cascoding M3 withM2 reduces the output conductance thereby reducing Rs and increasing the Q. TheNIC is comprised of 3 cross-coupled differential pairs of MOSFETs with drainstied to the opposing gates. It provides a negative resistance that seeks to cancel theparallel resistance Rp, further increasing the Q. When one cross coupled pair ofMOSFETs is used as a NIC, it provides a negative resistance of -2/gm and adds aCgs/2 parasitic shunt capacitance [6]. These simple NICs however, are notoriouslynonlinear. In order to obtain greater linearity a multi-tanh version of the NICcircuit was used. This requires the addition of two extra cross coupled pairs ofMOSFETs with a 2:1 size ratio [7, 8]. When the signal is large and the

1 A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator 5

symmetrical differential pair has saturated, the unbalanced differential pairs canstill provide a differential current proportional to the input voltage. This schemeworks effectively at high frequencies. We can rewrite Q0 as:

Q0 ¼1

gm1

ffiffiffiffiffiffi

Cp

Lp

s

ð1:16Þ

If we denote the enhanced quality factor of the circuit with a NIC asQn; then;

Qn ¼1

gm1 � gnic

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

Cp þ Cnic

Lp

s

ð1:17Þ

Here gnic is the NIC transconductance and Cnic is the capacitance the NIC addsto the circuit [7]. As can be seen from Eq. (1.17) the closer the transconductance ofM1 and the NIC the higher the Q. Care must be taken during design to ensure thatthe NIC transconductance does not exceed the transconductance of M1. The addedNIC capacitance decreases the resonant frequency. This can be compensated forby increasing biasing currents.

While there is no limit to the voltage that can be applied to spiral inductors, themaximum input voltage to active inductor based circuits must not cause MOSFETsto cease operating in saturation mode. Active inductor based circuits are alsonoisier than circuits with real inductors by a factor of 2Q0 [7].

We were able to design and simulate the schematics of active inductor basedresonators in Cadence with resonant frequencies between 100 MHz and 1.5 GHzand were consistently able to achieve a Q of 50 or greater.

Fig. 1.6 CMOS activeinductor based resonator withNIC

6 K. Dobson et al.

1.4 Simulation of Continuous Time Sigma DeltaModulator

A Matlab program was used to generate initial values of the resonator multiplyingcoefficients g, AH and AL that fulfilled G(s). Pole-Zero plots were then done toconfirm modulator stability. Next, Simulink simulations were used to further refinethe modulator design. The Simulink model was easily modified to reflect the non-idealities of an actual circuit such as limited gain due to nonlinearity and smalldelays introduced by each circuit component. In the ideal case with high gain in thepath containing the most resonators a theoretical Signal to Noise-plus-DistortionRatio (SNDR) of 95 dB was obtained. When the limitations of nonlinearity andcircuit delay were considered a goal of 75 dB for operation at 1.2 GHz was settledon. This required a 300 MHz resonator. For this schematic design, linear operationwas observed when the input was limited to less than 10 mv p-p. The Q was 50.

Cadence simulation of the designed schematic followed. A block diagram of thecomplete circuit simulated in Cadence is shown in Fig. 1.7.

A series of comparators [9] A, are used to provide the required delay of 1.4Tand effective amplification of the signal prior to quantization. A large enoughsignal at the input of the quantizer is necessary to prevent clock feed-through [9].Since there is a non-zero delay it is necessary to add a direct loop between theDAC and the ADC input [1]. The Adder used is described in [4].

A Differential pair is used to subtract the DAC output from the input signal asshown in Fig. 1.8.

A clocked comparator [9] coupled with a SR flip flop is used to generate themodulator output. The flip flop is necessary because a NRZ output is required.

The DAC shown in Fig. 1.9 converts the rail to rail output swing of thequantizer to a smaller voltage equal to the maximum peak to peak analog input.

Cadence schematic simulation results were similar to Simulink simulations inFig. 1.10, albeit with deteriorated noise shaping due to the circuit non-idealitiespreviously mentioned and others such as settling time of the adder output, andoffset errors. Nevertheless both yielded a SNDR of 75 dB as outlined in [10].

The layout of the schematic previously simulated was created and extracted.Upon simulation of the extracted layout it was evident that there needed to besome circuit modifications in order to achieve a working modulator. During theschematic simulation, the impedance of interconnecting wires was ignored.

Fig. 1.7 Active inductor based sixth order continuous time modulator

1 A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator 7

Simulation of the extracted view takes these impedances into account. Theinterconnecting wire leading to the active inductor and the gate capacitances of theinput PMOS device form a voltage divider. In order to couple input signalseffectively to the active inductor, while maintaining the required gains previouslydetermined, it is necessary to make the PMOS devices larger so that the capaci-tances seen at the gates of the PMOS devices are large and will effectively couplemost of the input voltage to the active inductor.

The addition of parasitic series resistances and parallel capacitances to thecircuit results in a lower resonant frequency and decreased Q. The extra parasiticsalso result in greater propagation delays between sub-circuits. This limits themodulator clock speed.

By increasing the size of M3 we decrease Rs which increases our deterioratedQ. Since Gm1 and Gm2 form a feedback loop, instability occurs when Gm2 gets toohigh i.e. when M3 is too large [11].

The output buffers between active inductors have to be slightly adjusted inorder to maintain bias points.

Because we have both digital and analog circuits on the same substrate we useseparate VDD and GND for these sub-circuits. We also surround our analog

Fig. 1.9 DAC

Fig. 1.8 Subtracterdifferential pair with bufferedoutput

8 K. Dobson et al.

sub-circuits with two guard rings separated by BFMOAT in order to protect themfrom digital noise [12].

The changes discussed above were made to the layout and Input/Output padsadded. Figure 1.12 shows this layout. The layout was re-extracted and a pad to padsimulation was conducted. We were able to achieve a SNDR of 70 dB for amodulator clocked at 480 MHz with 120 MHz resonators. This result is shown inFig. 1.11.

This still compares favorably with other non-active inductor based sixth orderband-pass RD modulators such as [13], which yields a SNDR of 68 dB. Our circuitconsumes 29 mW which is much smaller than the 160 mW consumed in [13] andoccupies a mere 0.5 mm2, as compared to the 2.5 mm2 used consumed in [13].

Fig. 1.11 Modulator output power spectrum density from Cadence pad to pad extracted layoutsimulation

Fig. 1.10 Simulink modulator output power spectrum density

1 A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator 9

1.5 Conclusion

We have succeeded in designing and simulating the first Sixth Order, CT RDmodulator using active inductor based resonators in the loop filter. The use ofQ enhancing techniques has resulted in a modulator with a high SNDR, and wehave avoided the use of area consuming spiral inductors. When compared to the47 dB, fourth order, active inductor based CT RD mentioned in [14] we are able toachieve a greater SNDR and consume roughly the same amount of power. Ourdesign goes beyond schematic simulation and tackles and overcomes the real lifedesign issues encountered when laying out this novel architecture.

References

1. Benabes P, Keramat M, Kielbasa R (1998) Synthesis and analysis of sigma-delta modulatorsemploying continuous-time filters. Analog Integr Circ Sig Process 23:141–152

2. Schreier R, Temes G (2005) Understanding delta-sigma data converters. IEEE press,Piscataway

3. Lelandais-Perrault C, Benabes P, De Gouy J, Kielbasa R (2003) A parallel structure of acontinuous-time filter for bandpass sigma-delta A/D Converters. In: Proceedings of 10thIEEE international conference on electronics, Sharjah (Emirates Arabes Unis)

4. Benabid S, Benabes P (2003) High linear integrated LC filter for a continuous-time bandpasssigma-delta ADC circuits and systems, vol 1(30). 2003 IEEE 46th Midwest symposium,pp 291–294, Dec 2003

5. Gao Z, Yu M, Ye Y, Ma J (2006) A CMOS bandpass filter with wide-tuning range forwireless applications, circuits and systems. ISCAS 2006. In: Proceedings of 2006 IEEEinternational symposium

6. Jung B, Harjani R (2004) A wide tuning range VCO using capacitive source degeneration,circuits and systems. ISCAS ‘04. In: Proceedings of the 2004 international symposium, vol 4,pp IV–145-8, 23–26 May 2004

7. Wu Y, Ding X, Ismail M, Olsson H (2003) RF bandpass filter design based on CMOS activeinductors, IEEE transactions on circuits and systems—II: analog and digital signalprocessing, vol 50, no. 12, Dec 2003

Fig. 1.12 Layout of480 MHz band-pass sigmadelta analog to digitalmodulator with activeinductor based resonators

10 K. Dobson et al.

8. Ryan AP, McCarthy O (2004) A novel pole-zero compensation scheme using unbalanceddifferential pairs, IEEE transactions on circuits and systems—I: regular papers, vol. 51, no. 2,Feb 2004

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10. Dobson K, Ahmadi S, Zaghloul M (2012) A 1.2 GHz band-pass sigma delta analog to digitalmodulator with active inductor based resonators. In: Lecture notes in engineering andcomputer science: proceedings of the world congress on engineering and computer science2012, WCECS 2012, San Francisco, USA, pp 875–879, 24–26 Oct 2012

11. Bakken T, Choma J (2002) Gyrator-based synthesis of active on-chip inductances. J AnalogIntegr Circ Sig Process 34:171–181

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13. Lu C-Y, Silva-Rivas JF, Kode P, Silva-Martinez J, Hoyos S (2010) A sixth-order 200 MHzIF bandpass sigma-delta modulator with over 68 dB SNDR in 10 MHz bandwidth. Solid-State Circ IEEE J 45(6):1122–1136

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1 A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator 11

Chapter 2Basic Computations Using a NovelScalable Pulse-Mode Modules

Thamira Hindo

Abstract In this chapter the basic computational functions used in many algorithmsare implemented in pulse mode. For this purpose, a novel circuit is proposedfor pulse-based logarithmic computation using integrate-and-fire (IF) structures.The smallest unit in the module is a network of three IF units that implements amargin propagation (MP) function using integration and threshold operationsinherited in the response of an IF neuron. The three units are connected togetherthrough excitatory and inhibitory inputs to impose constraints on the network firing-rate. The MP function is based on the log likelihood computation in which themultiplication of the inputs is translated into a simple addition. The advantage ofusing integrate-and-fire margin propagation (IFMP) is to implement a complexnon-linear and dynamic programming functions of spike based (pulse based)computation in a modular and scalable way. In addition to scalability, the objectiveof the proposed module is to map algorithms into low power circuits as an attemptto implement signal processing applications on silicon. The chapter shows themechanism of IFMP circuit, dynamic characteristics, the cascaded modularity,the verification of the algorithm in analog circuit using standard 0:5lm CMOStechnology and the basic functions computation.

Keywords Excitatory � Inhibitory � Integrate and fire � log-sum-exp � Marginpropagation � Pulse mode computation.

T. Hindo (&)Department of Electrical and Computer Engineering, Michigan State University,East Lansing, MI 48824, USAe-mail: hindotha@msu.edu

H. K. Kim et al. (eds.), IAENG Transactions on Engineering Technologies,Lecture Notes in Electrical Engineering 247, DOI: 10.1007/978-94-007-6818-5_2,� Springer Science+Business Media Dordrecht 2014

13

2.1 Introduction

Although Von Neumann computer architecture perform high speed computationand communication but they are unable to perform brain tasks processes in anefficient way such as the biological sensing in the retina and cochlea. A new trendin computer architecture for applications other than precise, high speed calculationand efficient communications is now in the fourth generation of research work tobuilt up a neuromorphic systems. The goal of the neuromorphic systems is toimplement sensory devices in an efficient way as in the biological sensors [1–5].The architecture of the morphed biological systems are different from the tradi-tional Von Neumann architecture such as asynchronous- parallel processinginstead of synchronous- single processing, hybrid computation instead of digitalcomputation, neuron model as a basic core of the processing instead of thearithmetic logic unit and finally, analog VLSI design instead of digital VLSI. As acontribution in this huge project, a novel and scalable algorithm is proposed toapproximate non-linear function as an important procedure to implement signalprocessing algorithms in the sensory applications such as recognition and classi-fication. The main objective of this work is to map a pulsed mode algorithm intolow power silicon circuits as an attempt to implement signal applications in theneuromorphic systems.The proposed module has three concepts, the first concept is to map the non-linearfunctions into margin propagation ‘‘MP’’ [6] which is an approximation functionto the log-sum-exp (LSE) expression. The second concept of the proposed moduleis based on an integrate and fire neuron model. The third concept is to implementthe non-linear function in pulse stream mode. The proposed pulse mode compu-tation module is abbreviated as ‘‘IFMP’’ since it implements a MP function usingIF neuron model.

For the first concept, the LSE math function is used in factor graph algorithmsin which the sum of product terms are used [7]. In these algorithms, the proba-bilities or the marginal functions of passing messages are evaluated between thenodes and variables of a factor graph. Since the product of probability terms tendto decrease as the number of probability terms increase, then we would have aproblem of underflow that cause false computations. Therefore, such algorithmsuse the log-likelihood computation to eliminate the underflow problem as well asto increase the dynamic range of variables in the computation process. But therepresentation of LSE is not scalable in hardware design. Therefore the marginpropagation function (scalable function in hard ware design) is used as anapproximation method to the LSE function. The concept of margin propagation(MP) algorithm is based on the idea of reverse water-filling (RWF) algorithm, [8].Given a set of random inputs (scores) Li 2 R; i ¼ 1 : m, the RWF algorithmcomputes the solution z according to the constraint,

X

m

i¼1

½Li � z�þ ¼ c ð2:1Þ

14 T. Hindo

where ½:�þ ¼ maxð:; 0Þ denotes a threshold operation and c� 0 represents aparameter of the algorithm. Note that z is in the log domain. The solution of theequation 2.1 is represented by z, where z can be written in LSE and MP forms as,

z ¼ logðX

m

i¼1

eLi ’ MðL1; L2; L3 . . . Lm; cÞ ð2:2Þ

where M denotes as the MP function, m denotes the number of the input operand.In previous work [9], it was proven that MP is successfully an approximationmethod to LSE. The input/output variables in the above work are represented ascurrents, also the computation procedure is implemented using kirchoffs currentlaw. MP was implemented in [9] to achieve scalability in the decoding algorithms.In this work, we introduce the concept of MP propagation as an approximationmethod to LSE in pulse computation mechanism.

Secondly, the structure of the proposed module is based on an integrate and fire(IF) neuron model that implement integration and threshold operation. Since the IFmodel is a simple representation of a neuron, it is extensively used as a neuronmodel in spiking neural networks [10–12] and neuromorphic systems [4, 13]. TheIF neuron itself is the basic computational unit in the sophisticated and efficientarchitecture, ‘‘the brain’’.

The brain is the most realistic example of an efficient system, ‘‘hybrid system’’,which is the third concept of the proposed module. The type of the signals (data)transferred in the brain is mixed between digital as spikes (pulses) and analog asthe variable time between these spikes. The above signal processing is called pulsestream mode or hybrid computations [14, 15]. Hybrid (pulse) computation is apromising research topic since it mixes the advantages of analog and digitaldesigns. The noise accumulation in analog stages can be eliminated by digitalnoise immunity. The analog design has the advantage of small area, low cost andlow power especially if the design of computational units is implemented in weakinversion mode of complementary metal oxide semiconductors (CMOS).Figure 2.1 shows the flow of the proposed module which includes manipulatingthe input pulse rate (scaling and converting into logarithm domain), mapping thefunction into MP and evaluate the output z, then scaling back and calculatingthe exponent of z to realize the function.

The concept of the proposed algorithm is analyzed, mapped and verified into alow power analog circuit, verify the properties of IFMP and the computations ofthe basic functions that are the core of signal processing algorithms and finallyverified the concept of pulse computation on 0:5lm process chip. This chapter isorganized as following: Sect. 2.2 demonstrates the analysis, synthesis, dynamiccharacteristics of IFMP module. Section 2.3 explains the circuit description andthe hardware verification of IFMP. Section 2.4 shows the chip test implementation.Section 2.5 describes the properties of the IFMP modules and how they are used toimplement computational functions. Section 2.6 concludes the chapter with thefuture work.

2 Basic Computations Using a Novel Scalable Pulse-Mode Modules 15

2.2 IFMP: Concepts and Analysis

Figure 2.2 shows a schematic diagram of the proposed spiking network module.The network is referred to as an IFMP module and consists of three integrate-and-fire structures N1;N2 and N3. The excitatory/inhibitory inputs are represented byblack/white triangles. Units N1 and N2 have self-inhibitory feedback connectionsand unit N3 has inhibitory input denoted as c. Given the rate of input spike-trainsL1½n� and L2½n� with n being a discrete time-index, it can be shown that firing-rate

of the output Lz½n� (denoted by EðLzÞ ¼ limT!11T

PTn¼1 Lz½n�) asymptotically

satisfies the following equation,

EðL1½n�Þ � EðLz½n�Þ½ �þþ EðL2½n�Þ � EðLz½n�Þ½ �þ�! Eðc½n�Þ ð2:3Þ

and in general for m inputs,

X

m

i¼1

EðLi½n�Þ � EðLz½n�Þ½ �þ�! Eðc½n�Þ ð2:4Þ

Note that equation 2.4 converges only in probability. The difference betweenthe left and right hand side of the above equation decreases as the time increases(or the number of stream sequence of random inputs increases) and hence thesummation of the expected values of the input stream converges to the expectedvalues of the output stream. In Hindo [16], we proved the convergence of oneneuron in order to prove the convergence of IFMP Eq. 2.4. For one neuron, theexpected value of output spikes d½n� is equal to the expected value of the inputspike L½n� overall the samples as following,

EnfL½n�gþ ¼ Enfd½n�g ð2:5Þ

Fig. 2.1 Input/output stages in the pulsed computational module

16 T. Hindo

Figure 2.3 shows the plot of instantaneous spiking-rates for N1, N2 and N3, whenthe rate of the inputs are varied as shown in Fig. 2.3. In this experiment, c ¼ 0:3and the input rate L2 ¼ 0:5 for N2 while input rate L1 for N1 increases from 0 to 1.The dynamic of the figure follows the IFMP equation 2.4 such that½L1 � z�þ þ ½L2 � z�þ ¼ c. Initially, when L1 is between 0 and 0.25, then the outputrate of N1;N2 and N3 is equal to 0; 0:3 and 0:2 respectively. When L1 is 0:3, thenthe output rate of units N1;N2 and N3 are 0:05; 0:25 and 0:25 respectively. WhenL1 is 0:6, then the output rate of units N1;N2 and N3 are 0:2; 0:1 and 0:4 respec-tively and so on. Hence, the sum of the output rates for the first two IF units N1;N2

converges to a constrain rate c over enough and sufficient time for convergence inwhich the dynamics of IFMP satisfies equation 2.4 as shown in Fig. 2.3.

N1

N2

N3

[L1-z]+

[L2-z]+

z

L1

L2

[.]+

Feedback current- -

+Excitatory inputInhibitory input

Integrator ThresholdFig. 2.2 Schematic of theproposed IFMP unitcomprising of three integrate-and-fire modules

0

0.2

0.4

0.6

0.8

Out

put r

ate

0 8 16 24 32 400

0.5

1

Time(sec)

Inpu

t rat

e

N3 N1 N2

L1L2

Fig. 2.3 Spike-rates forneurons N1, N2 and N3 (upperfigure) when the spike-rate ofL1 is monotonicallyincreased, The rate L2 is keptconstant at 0.5 (lower fig)

2 Basic Computations Using a Novel Scalable Pulse-Mode Modules 17

Figure 2.4 shows the plot of instantaneous spiking-rates for N3, when spiking-rate of the input rate L1 is varied from 0.01 to 0.9. For this result, the spiking-ratefor input L2 is kept constant to 0:5 as c changes from 0:01 : 0:05 : 0:56. The plotshows that the spiking-rate of N3 increases according to a piece-wise linearapproximation to the margin propagation function. It was shown in [9] that themargin propagation (MP) is an approximation to the log-sum-exp. However, theydid not provide close form representation for the approximation and the parametersinvolved. Furthermore, they did not demonstrate the efficacy of cascading theapproximated model. In Hindo [16], we addressed the parameter involved in theapproximation such that zMP ¼ zLSE � c where zMP is the approximated marginpropagation value to the LSE value ( zLSE). Figure 2.5a shows the approximationwhich is equal to c between zLSE and zMP; zIFMP where zIFMP ¼ zMP. Furthermore,we showed that the MP formulation can be mapped onto a cascaded topology suchthat the convergence equation for second IFMP in Fig. 2.5b expressing L2 ¼ �1and derived in Hondo [16] as ½zLSE1 � zLSE2 þ c�þ þ ½L3 � zLSE2 þ c�þ ¼ c, and ingeneral,

½zLSE½K� � zLSE½Kþ1� þ c�þ þ ½L½Kþ2� � zLSE½Kþ1� þ c�þ ¼ c ð2:6Þ

Equation 2.6 shows that three inputs MP can be implemented using twoidentical units of MP which is applicable for higher number of inputs too as shownin Fig. 2.5b. The advantage of cascading is that the algorithms can be implementedusing array of 2-IFMP units integrated on silicon while the connectivity couldpotentially be achieved using a field programmable gate array (FPGA). Therefore,we do not have to redesign the hardware for different applications.

Fig. 2.4 Dynamiccharacteristics of IFMP unitfor different values of c forMP and IFMP ( the analogmode and pulse mode of MPrespectively)

18 T. Hindo

2.3 IFMP: Circuit Description

The analog circuit of IFMP is designed and shown in Fig. 2.6a, where the shadedarea round blocks B1, B2 ,and B3 represent units N1, N2 and N3 of Fig. 2.2respectively. Block B2 in the upper right of Fig. 2.6a represents the circuit of theintegrator and inverter for the three blocks B1, B2 and B3. Figure 2.6b shows theresponse of the membrane voltage and the convergence equation between the inputand output rates for one neuron (represented by block B1 in Fig. 2.6a). Figure 2.6cshows the output pulses (d), membrane voltage (v) and input voltage ðinÞ of theintegrator in Block B1.

The integration and threshold are designed between two bounds (2:34v; 0:9v).Initially, if the input of the integrator is zero, the outputs of the integrator and thecascoded inverter are equal to 3.3 and zero volts respectively. If the input voltageincreases and reaches the high gain region of integrator amplifier (60 db), then theintegration phase will be built which is the discharging phase of the capacitor. Theinput current is integrated and the output voltage of the integrator discharges to thelower bound. At this point, the output of the cascoded inverter turned into logicone which will turn the output voltage of the integrator to the upper bound(charging phase of capacitor). The cycle of charging and discharging the capacitorC is repeated according to the amount of the current injected to the inputs of theintegrator (‘in’ node). The injected currents to the three integrators are appliedrespectively during off and on states of the input pulses for the excitatory path(PMOS transistors) and inhibitory path (NMOS transistors). Modules N1;N2 havetwo excitatory inputs (PMOS path), one self feedback inhibitory input (NMOSpath) and one feedback inhibitory input (NMOS path) from the output of unit N3,whereas module N3 has two excitatory inputs (PMOS paths) and one inhibitoryinput. The last inhibitory input is represented by an adjustable constrain rate cexplained earlier.

MP MP 1MPz 1LSEz

MPMPz LSEz

iL

1L

2L 3L

2MPz 2LSEz

4LMP

(b)

(a)Fig. 2.5 a Approximation ofIFMP to the LSE mathfunction. b Serial cascadingor (modularity) of IFPMstructure

2 Basic Computations Using a Novel Scalable Pulse-Mode Modules 19

2.4 IFMP: Chip Test Implementation

The dynamic characteristics of the IFMP module is verified in Matlab simulation(discussed in Sect. 2.2), cadence simulation and layout design on 0:5l process.Figure 2.7b shows successfully the balance trend in the dynamic characteristics ofone IFMP out of an array of 8� 8 IFMP on a (1:5� 1:5 mm ) package. Exper-iments are implemented to test the dynamic characteristics for two inputs IFMP,when gamma changes between 0.2:0.6. In the experiments, the chip is biased toensure the balance between the excitatory and inhibitory parts using Nationalinstrument (NI) data acquisition Input/ Output embedded systems. The appliedbiasing voltages are applied through Matlab program to initialize the ADC and

V [n-1] V[n]

Convergence in one neuron

._ [ 1] [ ] ( [ ] [ ])sI t

step voltage v n v n L n d nC

v

d

in

(b) (c)

(a)

= =

{ [ ]} { [ ]}E L n E d n=

−− −

Fig. 2.6 a Schematic circuit of the IFMP model. b The membrane voltage of block B1 and theconvergence equation between the input and output rates for one neuron. c Output pulses of blockB1 (labled by d variable), the membrane voltage at the output of the integrator (labled byv variable), and input voltage of the integrator (labled by in variable)

20 T. Hindo

DAC converters of the NI card. The USB is supported with functions to com-municate the input / outputs between the chip and FPGA. The inputs are applied asrandom pulses with specified rate. The pulses are generated using Verilog hard-ware description language (Verilog HDL). The HDL program is converted into bitfile and configured into hardware components on FPGA using Xilinx IntegratedSoftware Environment (ISE 9.2) software as shown in Fig. 2.7a. Samples of theresults in Fig. 2.7b that shows the rate of two inputs IFMP output as theoreticaland practical rate values when both inputs changed from 0.1:0.9 and the errorbetween them when c ¼ 0:4.

2.5 IFMP Properties and Examples of Basic Computations

In Gu et al. [17], the properties were mentioned for analog margin propagation. Inthis work, the properties are tested in pulse computation mode. Experiments areimplemented for both the theoretical and circuit pulse based margin propagationand shows the similarity between the two modes. The following margin propa-gation properties are verified in pulse mode.

PC USBControllers FPGA IFMP

Chip

NI data acquisitionCard Initialization Biasing voltage

Trigger inputs to collect the stored pulses instack memory from FPGA to PC

Decoders

8*8 IFMP

(a) (b)

(c)

Input/ output pulses to /from IFMP

Fig. 2.7 a System architecture to test the dynamic characteristics of IFMP chip b. c Dynamiccharacteristics that shows the output rate of IFMP unit and the error between the practical andtheoritical rate

2 Basic Computations Using a Novel Scalable Pulse-Mode Modules 21