Efficient Analog Fault Simulation in AC Circuits

Tiago Veiga, C. F. B. Almeida, J. Soares Augusto

Inesc-ID/IST/Un. Lisboa, Fac. Sciences, Dep. Physics

Abstract

In this paper we present an efficient AC domainfault simulator. We describe the circuit tech-niques which lead to this efficiency, as well assome results obtained by running the simulatorover some Mixed-Test benchmark circuits [1].The speed-up is more than 40, in a mediumsize circuit, and this figure goes up with theincreased complexity of the circuits.

1 Introduction

Efficient fault simulation is an important is-sue in test and in diagnosis of electronic cir-cuits. There are several widely-used efficientfault simulation techniques suitable for digitalcircuits: the parallel, deductive and concur-rent techniques [2]. In what respects analogcircuits, most of the works reported in the lit-erature are devoted to linear circuit AC anal-ysis, and usually are based on the Sherman-Morrison-Woodbury formulas of modificationof the inverse matrix [3, 4].

The application of efficient fault simulationtechniques to nonlinear DC circuits is reportedin [5, 6]. Both the works rely on the ideaof reusing, partially, the equations and/or thevalues of previous simulations to simulate thecurrent fault, following, however, different ap-proaches than those used in [7, 8, 9]. Otherreports of efficient fault simulation are based

on high level fault simulation, but the accu-racy of this option has been questioned [10](the same fault produced quite different out-puts at different simulation levels, even usingthe same simulator). The reported efficiency inthese works, compared with serial simulation,is variable, going from almost no efficiency tomore than two orders of magnitude. Anotherapproach that speeds-up fault simulation con-sists in distributing simulations by several par-allel processors or networked computers [11].

In [7, 8, 9] was presented a methodologyfor fault simulation in linear and nonlinearcircuits, called Fault Rubber Stamps (FRS),which is based on a modification of the tri-angular (or LU) factors of the nominal circuitmatrix. The simulation of a single fault is doneby appending one additional equation and oneadditional variable to the nominal system ofequations in such a way that the nominal Land U factors are used without modification.The technique has been developed with resis-tive linear circuits in mind, but afterwards itwas extended, with success, to DC nonlinearcircuits: it has been inserted into a Newton-Raphson (NR) solver that supports commonelectronic devices [7, 8]. It was also applied totime-domain simulation of linear circuits in [9].

In this paper we apply the FRS techniqueto AC simulation. A prototype simulatorwas built in Ruby, and fault simulation inMixed-Test benchmark circuits validated theapproach. The results are presented in section

1

51

5. In the next sections we describe, briefly,the algorithms behind AC circuit simulation,the techniques developed for achieving efficientfault simulation and, finally, we present the re-sults and the conclusions.

2 AC Simulation of LinearCircuits

The AC analysis of linear circuits requires thesolution of a complex system of equations writ-ten, in matrix form, as:

([G] + jω[C])x = s (1)

where [G] and [C] are circuit matrices. [G]is due to circuit elements with real parameters(e.g., resistors and controlled sources) while [C]is due to the presence of reactive elements (ca-pacitors, inductors and transformers). x ands are vectors of complex circuit variables andindependent sources, respectively.

The matrices [G] and [C] are filled by apply-ing Modified Nodal Analysis (MNA) to the cir-cuit, using the rubber stamps of the elementsmethodology [12, 4]. At present, the proto-type simulator supports resistors, capacitors,inductors, independent current and voltagesources, voltage amplifiers (voltage-controlledvoltage sources) and transconductance ampli-fiers (voltage-controlled current sources).

Although [G], [C] and s are filled only once forsimulating the nominal and the faulty circuits,equation (1) has to be solved for each simula-tion frequency. For a given frequency, say ω1,equation (1) becomes:

([G] + jω1[C])x = [M(ω1)]x = s (2)

where [M(ω1)] shows this dependency of thefrequency ω1. The system (2) is solved throughLU decomposition (or LU factorization) [4, 13],that is, [M(ω1)] is written as the product of

a lower triangular matrix [L(ω1)] with uni-tary diagonal, and an upper triangular matrix[U(ω1)].

The Sherman-Morrison-Woodbury formula isused with inverse matrices. However, in al-most all circuit simulators the circuit’s systemof equations is solved by decomposing the cir-cuit matrix and, due to this fact, the FRS tech-nique is tied to the LU decomposition.

LU decomposition is a time consuming opera-tion and it is imperative to optimize it. Oneway of achieving this goal is to take advantageof the sparsity of the matrix [M(ω1)]. In orderto ’transfer’ the sparsity of [M ] to [L] and [U ],the matrix is reordered before decomposition.A simple reordering algorithm is implementedin our simulator:

1. lines/columns with only one non-zero ele-ment – singleton – are swapped up/left inthe matrix in such a way that the single-ton goes to a pivot position;

2. the remaining lines and columns are re-ordered by growing number of non-zeroelements, but preventing the appearanceof zeros in the diagonal.

In this approach, the lines and the columnswith larger number of non-zero elements willmove to the lower and right positions in thematrix, thus minimizing the number of fill-insin LU factorization and keeping the sparsityof the matrices [L(ω1)] and [U(ω1)]. Noticethat more complex (and efficient) reorderingalgorithms can be used (see [4] which providesa very good exposition on these issues).

3 Fault simulation with FaultRubber Stamps

A fault in one element is a modification of itsnominal value. Analog circuits can have an in-

2

52

finite number of faults (the circuit parametersare continous), unlike digital circuits where thecircuit variables and the values in fault modelsonly have a small number of discrete values. Inanalog circuits tolerances in the element valuesare defined: an element is considered faulty ifit is outside the tolerance range.

Under the FRS aproach, to model a fault in oneadmittance with nominal value Y , for instance,an admittance of value ζ is tied in parallel withthe nominal one, such that the total faulty ad-mittance has a value of Y + ζ. The FRS mod-els for other circuit elements are similar (see[7, 8, 9] for details about the FRS model).

In serial fault simulation the solution of eachfaulty circuit would require a new LU decom-position, so that the serial simulation of Nfaults would take N times the time needed tosolve the nominal circuit. Serial fault simula-tion is very time consuming and impracticalwhen it is required to simulate a large numberof faults.

FRS provides a more efficient way to solvefaulty circuits. Going back to the admittanceexample, the presence of the extra element ζ,that causes the fault, manifests itself in thefaulty circuit equation by adding a new line(equation) and a new column (fault variable)to the nominal [M ] in (2). The faulty circuitequation is then:[

M w

v −1/ζ

] [x

xζ

]=

[s

0

](3)

where [M ], x and s are the same as in (2), vand w are vectors describing the nodes whereζ is inserted, ζ is the fault value and xζ is thefault variable. These last three items consist inthe Fault Rubber Stamp of the faulty element[7, 8, 9]. The matrix depends on the particularsimulation frequency, ω, which, in typical ACsimulations, spans several decades and consistsin tens or hundreds of discrete values.

The LU decomposition of the matrix leads to[L 0` 1

] [U u

0 α

] [x

xζ

]=

[s

0

]

The Crout1 algorithm used in the simulator de-composes [M ] from the upper-left part of thematrix to the lower right part. This meansthat the solution of the system, for a singlefault, requires (only) the factorization of thelast line and column (vectors v, w and scalar−1/ζ, leading to vectors ` and u and to scalarα). In fact, [L(ω1)] and [U(ω1)] are always thesame in nominal and in faulty circuits simula-tion at frequency ω1.

The nominal equations (2) are solved first andthe [M ] = [L][U ] factorization is done. Foreach faulty element the vectors `, u and thescalar α are calculated. When simulating sev-eral fault values in the same element, only αneeds to be recalculated, what makes fault sim-ulation even faster in this case. A top-leveldescription of the complete algorithm will bepresented in section 4. This approach leads toa substantial decrease in the simulation timeof one fault when compared to the time spentin simulating the nominal circuit. This is dis-cussed with detail below.

Fault Rubber Stamps could be used to sim-ulate multiple faults (that is, faults in morethan one element) simultaneously: for eachfault, a new line and column would be ap-pended to (2). For a large number of simul-taneous faults, this technique is not effectivebecause, as the number of faults increases, sothe does the dimension of system matrix. Usu-ally, multiple faults are not simulated, or diag-nosed, in analog circuits because the combina-torial expansion of multiple fault values in pro-hibitive. Even in digital circuits, where faultmodels have a small number of faulty states(e.g, stuck-at-0 or stuck-at-1), multiple faults

1Doolitle algorithm could also be used.

3

53

Figure 1: Leap-frog filter

Figure 2: State variable filter

are not commonly simulated.

4 The Fault Simulator

The simulator supports single faults.

Because analog fault values are infinite (section3), faults are discretized in an interval definedby the user (see figure 4). The fault simulationcommand is ‘.fault element lf% hf% N ’, whereelement is the element name, lf% and hf% arethe limits of the fault interval in percentageof the nominal value, and N is the number offaults to simulate in that interval. Opens andshorts can be simulated. The input files aresimilar to those of Spice.

Figure 3: Low-pass ladder with n stages.

The simulator algorithm can be described as:

• Read and parse the input file• Create a list with frequencies• Fill the nominal matrix [M ] with MNA• Reorder the matrix [M ]For each frequency:

• LU decomposition of [M ]• Solve the system [M ]x = sFor each faulty element:

• Update last line/column withFRS• Decompose these line and columnFor each fault value:

• Update −1/ζ in the matrix• Factorize appended value• Solve the faulty system

EndEnd

End

Note that in the simulation algorithm the outercycle is in frequency, because the nominal sys-tem of equations varies with ω and only af-ter the LU decomposition, done in the nominalsimulation, the FRS approach can be appliedto simulate the faults.

5 Simulation Results

The simulator was written in Ruby, a maturescripting language. Ruby programs are slowerto execute than programs written in compiledlanguages, such as C or Pascal, but Rubyprovides powerful native dynamic data struc-tures, libraries, and automatic garbage collec-tion, what allows for a very fast developement

4

54

Figure 4: Simulator output after simulating 10faults in C2, in the state variable filter, rangingfrom 20% to 180% of the nominal C2 value.

and debugging of the code.

For benchmarking purposes and validation ofthe algorithm, the circuits in figures 1, 2 and3 where used [1]. In the first two circuitsthe OPAMPs were modeled by linear voltage-controlled amplifiers with a gain of 105. Thethird circuit is a ”low-pass” ladder with 100stages (with Rj = 1KΩ and Cj = 1µF ).

Circuit State var. Leapfrog Laddern vars 12 20 102

Nominal 1.08 2.84 85.3100 faults 16.5 26.9 205Speed-up 6.50 10.6 41.6

Table 1: Times (in seconds) and speed-upwhen simulating the nominal circuit and 100faults in the state variable, leap-frog and lad-der circuits, at 61 frequencies.

In table 1 are the results of fault simulation inthe three benchmark circuits. All were simu-lated from 10Hz to 10MHz, with 10 points perdecade. The nominal and the faulty circuits’simulation times are in seconds. The speed-upis the relation between the simulation time ofthe nominal circuit and of the simulation timeof one fault. n vars is the number of variables

in each circuit.

The results show that fault simulation usingFRS is faster than the simulation of the nomi-nal circuit (the speed-up factor iis always largerthan 1).

The efficiency increases with the number ofvariables. This can be explained by the num-ber of operations in factorization. The simula-tion of a fault requires the factorization of onlyone line and column, while that of the nomi-nal circuit requires the factoriztion of all thematrix.

If full matrices (i.e., matrices without zeros)are considered, as the number of circuit vari-ables, n, increases so does the relation betweenthe number of elements in the nominal matrix(grows with n2) and the number of elementsin the extra fault line and column (grows onlywith n). The matrix factorization grows withn3 while the extra line and column factoriza-tion grows only with n2: this means there isa gain of 1 in the exponent of the polynomialcomplexity of the algorithm when simulatingone fault.

Although the circuit matrices are sparse, whatmeans the above complexity results cannot beapplied directly, a similar speed-up has beenobserved in practice: if the nominal circuit sim-ulation time grows with nm that of fault simu-lation grows approximately with nm−1 [7, 8, 9].

Figure 4 shows the fault simulation results ob-tained when simulating the state variable cir-cuit with 10 different fault values in the capac-itor C2. The graphical display of results wasdeveloped specifically for the simulator.

6 Conclusions

An efficient AC fault simulator was presentedin this paper. The algorithms used to achievethe efficiency were described. The main tech-

5

55

nique behind this efficiency, called Fault Rub-ber Stamps, reuses the LU factors of the nom-inal circuit matrix in fault simulation. Thefault simulation speed-up increases with in-creased circuit complexity. This increasedspeed-up is explained by considering the algo-rithms involved in the simulation of the nom-inal and of the faulty circuits. A substantialreduction (at least by a factor of 10) in abso-lute simulation times (not in speed-up factors)is expected if the simulator is implemented ina compiled language (e.g. in C).

References

[1] http://faculty.washington.edu/ mani-soma/madtest/ benchmarks/index.htm

[2] M. Abramovici, M. Breuer, A. Friedman,”Digital Systems Testing and TestableDesign”, IEEE Press, 1990.

[3] J. W. Bandler and A. E. Salama, ”Faultdiagnosis of analog circuits”, Proceedingsof the IEEE, vol. 73,8, Aug., 1985.

[4] J. Vlach and K. Singhal, Computer Meth-ods for Circuit Analysis and Design, VanNostrand Reinhold, second edition, 1994.

[5] M. Wong, M. Worsman, ”DC Nonlin-ear Circuit Fault Simulation With LargeChange Sensitivity”, 7th. Asian TestSymposium, 1998.

[6] M. Tian, C.-J. Shi, ”Efficient DC FaultSimulation of Nonlinear Analog Circuits”,Design Automation and Test in Europe(DATE ’98), Paris, 1998

[7] paper from the authors at Int. Mixed Sig-nal Test. Workshop, The Hague, Nether-lands 1998.

[8] paper from the authors at VLSI’99 (XIEEE International Conference on VeryLarge Scale Integration, L. Silveira etal. (eds.) ”VLSI: Systems on a Chip”,Kluwer), Lisboa, Portugal, 1999.

[9] paper from the authors at European TestWorkshop, Capri, Greece, 2002.

[10] B. Straube, W. Vermeiren and U.Namyslo. ”On Problems with Hierarchi-cal Analogue Fault Simulation”, EuropeanTest Workshop (ETW97) Proc., Cagliari,Italy, 1997.

[11] C. Sebeke and M. Ohletz. ”AnalogueFault Simulation”, CAVE WORKSHOP,Dresden, Germany, 1993.

[12] C.-W. Ho, P. A. Brennan andA. E. Ruehli, ”The modified nodalapproach to network analysis”, IEEETransactions on Circuits and Systems,CAS-22, pp. 504-509, 1975.

[13] A. L. Sangiovanni-Vincentelli, ”Computerdesign aids for VLSI circuits - Circuit sim-ulation”, NATO Advanced Study Insti-tute, Italy, 1980.

6

56