In  His  Name  

ECEN  654  Lab  2  Filter  Design  

Materials:  • Using Matlab FDA tool to parameterize infinite impulse response (IIR)

coefficients • Safe scaling – Parasitic oscillation effects • Hardware implementation and test of digital filters – fully combinational

method

Objectives:  In this lab you will implement a filter, whose characteristics are given. During

the implementation, you will experience using Matlab FDA tool to parameterize filter coefficients. And do quantize the filter in Matlab and understand how quantization affects a DSP design. Finally, you will design your filter using Verilog code and verify it with a self-diagnostic test bench that obtains its data from Simulink model.

Filter  Target  Characteristics:  

Filter:  • Rp = 1db, Rs = 60db, Fs = 44100Hz, Fp = 3400Hz, Order=6. • Quantization signal-to-noise ratio (SNR) >= 35 dB

Input:  • Sample voice signal which is normalized to the (-1, +1) amplitudes with sample

frequency equal to 44100.

Directions:  1. Launch Matlab Log in to the serve by using your NETID. Open the terminal and type below

to open .tschrc file. gedit ./.tschrc

Add following line into the file: alias matlab ‘/softwares/Linux/matlab2012b/bin/matlab’

Save the file and quit to terminal. By typing following command, validate the shortcut for matlab

source ./.tschrc

Then type ‘matlab’ in terminal to launch Matlab 2. Parameterize the IIR by using FDA tool After launching the Matlab, create a directory where you want to save all stuff

in this lab and change the path to the created directory. Then by typing ‘fdatool’ in the console window of matlab, you can launch the FDA tool. Set the characteristics as given before and click design filter, as shown in Figure 1.

After designing filter, click the ‘realize model’ label, the fourth label in the left bar. Check the option ‘Build model using basic elements’ and press ‘Realize Model’ as shown in Figure 2. Then the IIR filter will be automatically parameterized in a Simulink model in Figure 3. In the Simulink window, click File-> Save to save the model in the local folder. If you double click the filter, you can see the internal structure of the filter.

Figure 2

Figure 3

Next step, we will quantize and simulate the parameterized the IIR filter.

3. Quantizing the filter to target performance In this section, we will quantize the coefficients in the IIR filter. First of all, we

will set up the quantized model based on the floating-point filter model. Then we will simulate the quantized model and see how the quantization affects the performance. Finally, we can determine how we quantize the model with acceptable degradation in performance.

Before simulating the quantization, go to lab webpage to download the test wave file, ‘test.mat’ to local directory. This file will be used as signal source.

3.1 Quantize the Coefficients Double click the quantized filter model. And check the swings of all

coefficients. So that you can determine how many bits are necessary for the integer part.

Next step we need do experiments to examine how many bits necessary for precision. Open the coefficients gains. And edit the gain as shown in Figure 4, where ck is the precision bit length for quantized coefficients. Doing this modification on all coefficients so that all of them are quantized. Next step, we need port out ck value setting from this model. In the top model, right click the ‘quantized filter’ model and click mask->create mask. And add parameter as shown in figure 5.

Now you can change the value of ck easily from top model by double-click the ‘quantized model’.

Figure 4

Figure 5

After adding those quantization blocks, we now start to find best quantization. Click View->Library Browser to launch the library browser, you can find any

blocks you need by typing name to search. Use the library browser to add block of band-limited white noise, mux and

spectrum scope as shown in Figure 6.

Figure 6

Double click the band-limited white noise, replace the default value of 0.1 with 1. And set the sample time is 1/44100.

Double click the spectrum scope and set it as shown in Figure 7.

Figure 7

Then run the Simulink. You will see the spectrum from floating-point model and fixed-point model. Change the quantization to make sure the difference in pass band less than 0.1 dB and less than 1 dB in stop band as shown in Figure 8.

Figure 8

3.2 Quantize the Input and Output Double click the saved model. Once you open the model, click View->Library Browser to launch the library

browser. Type ‘From file’ to search for the source block and drag the block into model. Double click the model and select ‘test.mat’ as the source file and type 1/44100 in the sample time, since our filter is designed for fs = 44100Hz.

Duplicate the IIR filter in the same model, and rename the duplicated model as ‘Quantized Model’:

Add other blocks as shown in Figure 9. All blocks could be found in Library Browser. After adding RMS block, double click it check ‘running rms’ and choose sample based input processing.

Figure 9

If you run the Simulink now, you could find the SNR is infinite because two filters are exactly same and product same results.

To quantize the I/O, firstly we need know the swing of I/O. We using ‘to work space’ block to acquire the input and output from the Simulink as shown in Figure 10.

Figure 10

By doing this we can know the magnitude of input and output. Now, we start

quantizing the I/O. Double click the quantized model, add quantization part after input and before output. Quantization segment consists of three components: gain, round, saturation. The quantization part looks as below:

Figure 11

The first gain blocks increase the values to make precision reserved. The corresponding gain should be 2^(k-1), where k is the precision.

The round block truncates redundant precision. The saturation part prevent overflow from designed swing amplitude. The

value of saturation should be 2^(k+s-1)-1 for upper bound, -2^(k+s-1) for lower bound, where s is number of assigned bits for swing.

The second gain block decrease the values to approach the quantized value. The corresponding gain should be 1/(2^(k-1)).

By adding quantization section in input and output, we can do safe quantization for input and output.

By applying different values of k, SNR will differ. Choose the minimum k which makes SNR larger than 35 dB. At this point, we finish quantizing the I/O. Now you can start the Bus Quantization by the same method we used in I/O quantization.

3.3 Quantize the Bus Repeat the way we quantized the I/O to determine the bus width in every node.

In this case, you need make sure that the quantization will not degrade the SNR lower than 35 dB.

4. Implementation After quantization of the filter you need to extract the data from Simulink

model to be used in verification part. The implementation of the hardware is described as flows: Design:  After extracting the real implementation parameters of the system properly, you would be able to model the system (one of the biquads of 6 ordered IIR filter) using HDL languages (Verilog in this case). For this purpose, design two basic modules named “mult_sr” and “add_s” for bit-true multiplication and addition respectively. Verify these modules for proper operation. The length of inputs and outputs for these modules were the same as you extracted in your former experiences. Consider these two modules as basic functions and model the entire biquad filter. In this part, consider the state variables (register outputs) and also input/output values. The sample biquad module should be able to compute the filtering operation for an instance of input data. Verification: After completing the design phase of your sample biquad filter, you should verify the design using proper input and output samples. Applying input samples, updating the state variables and dumping the output results to output file are performed in the biquad testbench. For better understanding of how to write a proper Self-diagnostic testbench, consider that the verification part consists of three following phases:

• Test data generat ion: Monitor the input and output lines of the samples biquad filter in your MATLAB model during a complete simulation cycle. For this, apply a sample input to the filter (6th otdered) and send the input and output lines of the sample biquad part to the workspace. Then, write the extracted test data from workspace to standard files (“mat_data_in.dat” and “mat_data_out.dat”) regarding the extracted bit-length parameters.

• Apply ing t es t data : In this phase, generated test data are automatically applied to the verilog biquad module. For this, write a testbench over the designed module. The testbench do the following operations at each positive clock edge: read the data from Matlab Input data file and apply them to the Verilog module.

• Automati c ver i f i cat ion: In this phase, the Verilog model is verified using the generated samples from MATLAB model. For this, read samples from Matlab output data file and compare that with Verilog output data. In this part, any existing inconsistency demonstrates the fault in your design process and should be removed.

Deliverables:  • Compare SNR degradation after data bus quantization for different structures. • Report appropriate additional word length for precision adjustment of internal

nodes in swing measurement and safe scaling method. • Verilog models (both design and testbench) • Extracted test data and test extraction program for MATLAB • A complete description about the test data generation, HDL design and

modeling, and verification strategy.

Helpful  Hints:  • 𝐼𝑛𝑡𝑒𝑟𝑚𝑒𝑑𝑖𝑎𝑡𝑒𝑊𝐿 = 𝑙𝑜𝑔!   ℎ 𝑛 + 𝑖𝑛𝑝𝑢𝑡𝑊𝐿!

!!! , Where h is the impulse response from the input to node (safe scaling).

• For writing the generated test data into standard IO files, you may use fprintf and fopen commands.

• For writing the self-diagnostic testbench you may use $fopen and $readmemb ($readmemh).

• Xilinx ISE can not synthesis the multipliers use one of the structures presented here: http://fpga-guru.com/multipli.htm

Figure 1- The structure of a simple filter at left and warp around adder at right.

Figure 2- The three different inputs from left to right a, b, and c.

Figure 3- The block diagram of the system to be implemented in Simulink.