ecen 665 (ess) : rf communication circuits and systemss-sanchez/heng_lna.pdf · ecen 665 (ess) : rf...

11

ECEN 665 (ESS) : RF Communication Circuits and Systems

Low Noise Amplifiers

Prepared by: Heng Zhang

Analog and Mixed-Signal Center, TAMU

Part of the material here provided is based on Dr. ChunyuXin’s and Dr. Xiaohua Fan’s dissertation

22

What is an LNA?

Amplifier S matrix:

Source reflection coefficient:

Load reflection coefficient:

Input reflection coefficient:

Output reflection coefficient:

LΓ

SΓ

12 2111

221L

inL

s sssΓ

Γ = +− Γ

12 2122

111S

outS

s sssΓ

Γ = +− Γ

[ ] 11 21

12 22

s sS

s s⎛ ⎞

= ⎜ ⎟⎝ ⎠


33

LNA RequirementsGain(10-20dB)

to amplify the received signal;to reduce the input referred noise of the subsequent stages

Good linearity Handling large undesired signals without much distortion

Low noise for high sensitivity

Input matchingMax power gainPreceding filters require 50Ω termination for proper operationCan route the LNA to the antenna which is located an unknown distance away without worrying about the length of the transmission line


44

LNA Metrics: GainDefines small signal amplification capability of LNAFor IC implementation, LNA input is interfaced off-chip and usually matched to specific impedance (50Ω or 75Ω). Its output is not necessary matched if directly drive the on-chip block such as mixer. This is characterizedby voltage gain or transducer power gain by knowing the load impedance level.Transducer power gain: Power delivered to the load divided by power available from source.

For unilateral device:(i.e. s12 = 0)

2 22

212 211 22

1 11 1

S LT

S L

G ss s− Γ − Γ

=− Γ − Γ


55

LNA Metrics: Nonlinearity Model

Output signal spectrum with f1 and f2

Usually distortion term: 2f1-f2, 2f2-f1 fall in band. This is characterized by 3rd order non-linearity.

Large in-band blocker can desensitize the circuit. It is measured by 1-dB compression point.

f

off-bandsignal

f 1 f 2

2f2 f1 in-bandsignal

f

f 1 f2+

f12 f22

f1 f2

f1 f2-2 f2 f1-2f1 f2-

2 30 1 2 3t t t tY a a X a X a X= + + +

Two tone input signal:Nonlinear System (up to 3rd order):

1 2cos( ) cos( )tX A w t A w t= +


66

LNA Metrics: Linearity measurement

1dB compression:Measure gain compression for large

input signal

IIP3/IIP2:Measure inter-modulation behavior

Relationship between IIP3 and P1dB:For one tone test: IIP3-P1dB=10dBFor two tone test: IIP3-P1dB=15dB


77

LNA Metrics: Noise FigureNoise factor is defined by the ratio of output SNR and input SNR. Noise figure is the dB form of noise factor.Noise figure shows the degradation of signal’s SNR due to the circuits that the signal passes.

Noise factor of cascaded system:

LNA’s noise factor directly appears in the total noise factor of the system.LNA’s gain suppress the noise coming from following stages

174 10log

( ) tot

dBm BW

Sensitivity Noisefloor dBm SNR NF− +

= + +1442443


88

MOS Amp Noise Figure Calculation

the current gain of the MOS amp is given by:

( ) ( )

11

; 1

so m gs m

gss g

gs

m m ms s T

gsgs s g gs s g

vi g v gj CR R

j C

g g gv vCj C R R j C R R

ωω

ωω ω

⎛ ⎞= = ⎜ ⎟⎜ ⎟

⎝ ⎠+ +

= ≈ =+ + +


99

Noise Figure by Current Gain

( )o m si G vω= ( ) 1Tm

s g

G jR R

ωωω

= −+

the total output noise current is given by:

( )2 2 2 2 2,o T m g s di G v v i= + +

the noise figure can be easily computed:22 2 2

, ,

2 2 2 2 2 21 ,go T o T d

o m s s m s

vi i iFi G v v G v

= = = + +


2 2 24 , 4 , 4g g s s d mv kTR v kTR i kT gγα

= = =

1010

Noise Figure Calculation(cont.)Substitution of the the various noise sources leads to :

( )2

2

2

1

1

mg

s gs s T

gm s

s T

gRF R R

R R

Rg R

R

γωαω

γ ωα ω

⎛ ⎞⎜ ⎟ ⎛ ⎞⎝ ⎠= + + +⎜ ⎟

⎝ ⎠

⎛ ⎞⎛ ⎞≈ + + ⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

This expression contains both the channel noise and the gate induced noise

is a good approximation 15g poly

m

R Rg

= +


1111

Minimum Noise for MOS Ampthe optimal value of Rs :

2

2 0gm

s s T

RF gR R

γ ωα ω

⎛ ⎞∂ ⎛ ⎞= − + =⎜ ⎟⎜ ⎟∂ ⎝ ⎠ ⎝ ⎠

Thus the minimum Noise Figure is:

,gT

s opt s

m

RR R

g

ωγωα

= =⎛ ⎞⎜ ⎟⎝ ⎠

min 1 2 m gT

F g Rω γω α⎛ ⎞ ⎛ ⎞= + ⎜ ⎟ ⎜ ⎟

⎝ ⎠⎝ ⎠


1212

F vs. RsFor an LNA operating at 5.2GHz in 0.18 μm CMOS process, according to experience and published literatures, we can choose Rg = 2Ω, γ = 3, α = 0.75, ωT = 2π*56GHz, gm = 50mA/V and plot F vs. Rs:

2

1 gm s

s T

RF g R

Rγ ωα ω

⎛ ⎞⎛ ⎞= + + ⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠


1313

MOS Amp ExampleFind for a typical amplifier. Assume

, is minimized by proper layout,thus intrinsic gate resistance is given by:

To make the noise contribution from this term 0.1:

1 15 5g poly

m m

R Rg g

= + ≅

,s optR 75Tf GHz=

( )5 , 2f GHz γ α= = polyR


, min100.1 40 119 , 1.08 5

gm s opt

s s

Rg mS R F

R R= ⇒ = = ⇒ ≈ Ω =

In practice, it’ll be difficult to get such a low Noise figure and get useful gain with the simple common source due to the bad power match

Conflict of minimum noise vs. optimum matchingThat’s why we need input matching schemes for LNA!

1414

LNA Metrics: Input MatchingWhy do we need it?We have learned how to choose optimum source

impedance for minimum noise figureOne important requirement for LNA is 50 ohm matchingThe input of a common source amplifier is primarily

capacitive and provides very poor power match!Maximum power transfer:

What should we do to have both good NF and good power match?

*sin ZZ =

( )2 22

1_ _ max 2 2 Re( ) 2

s in s inin LNA

in sin s

V Z V PVPZ ZZ Z

= = = =+


1515

LNA Input Matching TopologiesWideband LNA:

Resistive terminationCommon Gate Resistive shunt-feedback

Narrowband LNA: Inductive degeneratedResistive terminated


Resistive Termination LNA

Since the input of a CS MOS devices is primarily capacitive then we can

terminate the input with a resistor Rm=Rsto match the input (at low frequencies)

It can be used in both narrowband and the wideband application. But its highNF(usually NF>6dB) characteristic limits its application.

bV

outV

DR

inVmR

sR

inZ

1M

2M

dcI

VDD

outZ

16Analog and Mixed-Signal Center, TAMU

Noise Analysis

gs1C

+

-

V1g12 ro1

gs2C

outV

m1g V1

+

-

Vgs2

m2g Vxn,M22ro2 -

i

i

n,M12i

Zout

inV

mR

sR

inZ

DR

*n,s

2V

* n,m2V

* n,D2V

Output noise due to source resistor Rs: 2 2 2, 1( )n s s v s m DV KTR A KTR g R= =

1v m DA g R≅ D outR Z<<where and

Output noise due to matching resistor Rm(=Rs):2 2, 1( )n m s m DV KTR g R=

Output noise due to thermal noise of M1:2, 1 14n m mi KT gγ

α=

Output noise due to the load resistor, RD: 2,n s DV KTR=

Output noise due to thermal noise of M2: 2 2

2 22 2 2, 2 2 , 1

2 2 1 2 2

4 gs gsmn m m n m

m gs m m gs

sC sCgi KT g ig sC g g sC

γα

⎛ ⎞ ⎛ ⎞= =⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟+ +⎝ ⎠ ⎝ ⎠


Noise AnalysisThe noise factor of the LNA is:

2 2 2 2 2, , , 1 , , 2

2,

total output noise noise due to the source resistor

n s n m n m n D n m

n s

V V V V VF

V+ + + +

= ≥

Noise from RD is attenuated by LNA gain. The noise transfer function of M2 is smaller due to source degeneration. Both are ignored for simplicity:

2

21 1

4 41 2m

s m s m s

RFR g R g R

γ γα α

= + + = +

Therefore, even when gmRs>>4γ, Fmin>2 (NF>3dB)Resistor termination provides a good power match but greatly degrades the NF

The terminating resistor adds its own noiseIt also drops the gain by 6dB (compared to CS with no termination). As a

result the input referred noise of the device and those of the following stages increase by the same factor


Common Gate(CG) LNA Input impedance:

1in

m gs

Zg j Cω

=+

1if mgs m T in

gs m

gC g ZC g

ω ω ω ω<< ⇒ << ⇒ << ⇒ ≈

Noise Figure: ignoring poly gate resistance, gate noise, and ro, the output current noise is:

2 2 2, , sno no ind no Ri i i= +

2, drain current noise: no indi

2, output noise current due to source resistance:

sno Ri

( )

222 2

, 2 1s

ns mno R ns

m ss in

e gi eg RR R

⎛ ⎞= = ⎜ ⎟++ ⎝ ⎠


Noise Analysis

Notice that if gm=1/Rs (power match) then only half of drain current noise goes to the output

( )1

o nd m gs

nd sgs nd m gs gs gs s gs

m gs gs gs

i i g v

i Rv i g v j C v R vg v j C v

ωω

= + ⎫⎪⇒⎬= − + + ⇒ = − ⎪+ + ⎭

( )1 1 , assume 11 1

gs so nd nd gs s

m gs gs s m s

j C Ri i i C R

g v j C R g Rω

ωω

+= ≈ <<

+ + +


Noise Analysis

Under the input matching condition: Rs=1/gm we have:

22

02 2

2

11

1 1

1

ndm s d

m smns

m s

ig R gF

g Rgeg R

γ⎛ ⎞⎜ ⎟+⎝ ⎠= + = +⎛ ⎞⎜ ⎟+⎝ ⎠

Noise Factor:

05 2.2 Long channel

1 1 33 4.8 Short channel

d

m

dBgFg dB

γ γα

⎧ =⎪= + = + = ⎨⎪≥ =⎩


Resistive Shunt-feedback LNA

Voltage gain:

Input impedance:

( )11L m fv

f L

R g RA

R R−

=+

1 1

1/ /1

f Lin

m L gs

R RZ

g R sC+

=+

Output impedance: 1

/ /1

s fout L

m s

R RZ R

g R+

=+

The negative feedback network is used to implement the input matchingThe input impedance is determined by open loop gain and the resistor values (Rf, RL), which are easily controlled.The resistor is a noise component and the LNA has moderate noise performance.

1MinV

LR

fR

fCSR

Zin

outV

Zout

gs1C


Noise Analysis

Noise Factor: 22 2 2 2 2

12 2 2 2 2, , ,

2 2 2

1 1

1 1 1

4 4 412

1 111 1 1

f L

s s s

R R outout s d out

vn R n R v n R v

f f s f sm s m

s m f s L m f s m f

i i ZZ R i ZFAV V A V A

R R R R Rg R gR g R R R g R R g R

γα

× × ⋅⎛ ⎞ × ⋅= + − + +⎜ ⎟

⋅ ⋅⎝ ⎠

⎛ ⎞ ⎛ ⎞ ⎛ ⎞+ ++= + + +⎜ ⎟ ⎜ ⎟ ⎜ ⎟⎜ ⎟ ⎜ ⎟ ⎜ ⎟− − −⎝ ⎠ ⎝ ⎠ ⎝ ⎠


Inductive degenerated LNA

( ) 1 m sin g s

gs gs

g LZ s L LsC C

= + + +

Input impedance behaves like a series RLC circuit, gate inductor Lg is added to tune the resonant frequency to align with the operating frequency:

Matching occurs when: ( )0in sZ j Rω =

( )2 1 , and m so s T s

gsg s gs

g LR LCL L C

ω ω= = =+

ss

T

RLω

=Ls can be selected by:if this value is too small to be practical, a capacitor can be inserted in shunt with to artificially reducegsC Tω


Input impedance-non-idealities

( ) ,1 1

1in g s T s Lg g Ls g NQSgs

T Ls

Z s L L L R R R RsC s

R

ω

ω

= + + + + + + + +

( )0 ,in T s Lg g Ls g NQSZ j L R R R Rω ω= + + + +

,212

poly shg

R WR

n L=

Inductance loss RLg : offset Zin

RLs : offset Zin and w0

Gate resistance Rg : offset Zin

NQS gate resistance Rg,NQS : offset Zin

( )

1 1/ /

o

g s gsT Ls

L L CR

ω

ω

=⎛ ⎞

+ ⎜ ⎟⎝ ⎠

,1

5g NQSm

Rg

=


Q Boosting

( ) 0 0

1 12s s T gs s gs

QR L C R Cω ω ω

= =+

At resonance we get Q boosting effect:

gs sv Q v= ×

{0

12

m

m

Td m gs m s s

sG

G

i g v Qg v vR

ωω

⎛ ⎞= = = ⎜ ⎟

⎝ ⎠14243

Need to watch out for linearity as vgs is Q times larger than the input signalShort channel devices operating in velocity saturation regime (i.e., large overdrive voltage) are more forgiving as their gm is relatively constant.


Equivalent input networkFrom the source, the amplifier input(ignoring Cgd) is equivalent to:

At resonance, the complete circuit is as follows:


Noise Analysis

The output noise current due to Rs and Rg is simply calculated by multiplying the voltage noise sources by GmThe calculation of output noise current due to drain noise is more involved: flows partly into the source of the device, it activates the gm of the transistor which produces a correlated noise in shunt with

Output noise current:

2di

2di


( )2 2 2 2 2,

1 , 2s g

Tno m R R d out m

s o

i G v v i GR

ωω

⎛ ⎞= + + = ⎜ ⎟

⎝ ⎠

Noise Analysis: Drain NoiseThe noise component flowing into the source is given by the current divider:


( )

( )

11

1 (at resonance) 2

sgs m gs d

gss g s

gs

s dm gs d m gs

s gs

j Lv g v ij Cj L j L R

j C

j L ig v i g vR j C

ωωω ω

ω

ωω

= − + × ×+ + +

= − + × × ⇒ = −

Note that we are not including Rg in the small signal model

Total Output NoiseLet’s first ignore the correlation of the gate noise and drain current noise. Notice only ¼ of the drain noise flows to output


( )2 2 2 2 21 1 4 2s g

Tno m R R d m

s o

i G v v i GR

ωω

⎛ ⎞= + + = ⎜ ⎟

⎝ ⎠

Note that the Noise figure at resonance is the same as CS amplifier w/o inductive degeneration. Inductive degeneration did not raise Fmin but matched the input !

22

2 21

s

gno om s

s Tm R

RiF g RRG v

ωγα ω

⎛ ⎞= = + + ⎜ ⎟

⎝ ⎠

Total Output Noise(cont.)If we consider the correlation of the gate noise and drain current noise then one can show (*)


2

1 g om s

s T

RF g R

Rωγ χ

α ω⎛ ⎞

= + + ⎜ ⎟⎝ ⎠

( )2 2

21 2 15 5L Lc Q Qδα δαχγ γ

= + + +

( )1gs

o g sL C

o s gs s

L LQ Q

R C Rω

ω+

= = =

Optimal Noise figure happens for a particular QL. Possible to obtain a noise and power match

* D.K. Shaeffer, T.H. Lee, “A 1.5V 1.5GHz CMOS Low Noise Amplifier”, JSSC, Vol. 32, No. 5. May 1997

Optimal QL

If we try to optimize the noise figure while power dissipation is kept constant then:

QL,opt will be independent from the frequency and

around 4.5

Fmin is not too sensitive to QL and only changes by less than 0.1dB for QL between 3.5 and 5.5

Smaller QL results in larger bandwidth and smaller inductors, while a larger QL results in narrower bandwidth and larger inductors


Linearity

IIP3 is independent of W


( )( )23,

4 82 13 3

eff effIIP strong MOS eff eff

V VV V Vθ θ

θ θ= + + >

1 eff gs thsat

V V VE L

θ= − =

Esat ~ 1V/μm for L~0.35 μm-0.18 μm

MOS transistor’s IIP3 v.s. gate drive voltage

( ) ( )32

2 23, 2 2

16 12 13

DIIP LNA

o

PV VP

ρθ ρ

⎛ ⎞= + +⎜ ⎟

⎝ ⎠3 2

sat sateff o DD

o s

v EV P VR

ρ θω

= =

Linearity of a MOS transistor in saturation region:

Design Recipe for Inductive degenerated LNA

Analog and Mixed-Signal Center, TAMU 34

Step 1: Choose QL for optimal NF⇒ Cgs

⇒ Width(W)

Step 2: Determine the current(Id) from power budget

Step 3: From W & Id ⇒ gm and Veff

Step 4: From gm and Veff ⇒ ωT and Fmin

Step 5: Select Ls and Lg for the input network

( )1L o s gsQ R Cω=

s s TL R ω= ( )21/g o gs sL C Lω= −

Design Recipe: Iterations


NF is not low enough?Increase ωT by increasing Id (with fixed device size)For fixed current density, increasing Q will reduce device size thus reduce total power - NF will increase

Linearity doesn’t meet spec?Reduce Q (in short channel devices the improvement is limited)Burn more current (not gaining much due to velocity saturation)Apply proper linearization techniques

Need to increase gain?Larger QL

Larger gm

Larger Load(ZL)

Design Example:


Specs:

Frequency 2.4GHzS11 <-10dBS21 >15dBNF <2dBIIP3 >-10dBmCurrent <10mASupply 1.8VProcess 0.18μm

CMOS

Step 1: Choose QL = 4.5. then

Choose minimum length L = 0.18μmW = 110μm

Step 2: Choose the current Id = 9mAStep 3: From W & Id gm = 52mA/VStep 4: From gm and Cgs fT = 56GHzStep 5: Select Ls and Lg for the input network:

Step 6: S21 requirement ZL = 24Ω

1 2 147gs L o sC Q R fFω= =

0.14s s TL R nHω= =21 31g o gs sL C L nHω= − =

Simulation Results: S21, S11, NF


Simulation Results: IIP3


Summary:


Parameters:

Calculated SimulatedM1 110μm/0.18

μm110μm/0.18μmM2 110μm/0.18

μm110μm/0.18μmLg 31nH 20nH

Ls 0.14nH 0.28nHId 9mA 8.6mAZL 24Ω 26Ω

Performance:

Specs SimulationFrequency 2.4GHz 2.4GHzS11 <-10dB -32dBS21 >15dB 15.7dBNF <2dB ~0.62dBIIP3 >-10dBm -6.85dBmCurrent <10mA 8.6mASupply 1.8V 1.8V

Effect of RL on input matchWe ignored the effect of load impedance on input impedance in previous derivations. Let’s revisit it:It can be shown that:

RL can be large and it can drop the real part of the input impedance when we use resonators at outputNotice that the output impedance influenced the input impedance even in the absence of Cgd!


( )

[ ]

21

1

soin s s T

gs o L s o

os s T

gs o L

LrZ jL LjC r R jL r

rjL LjC r R

ωω ω

ω ω

ω ωω

⎡ ⎤= + + +⎢ ⎥

+ + ⎢ ⎥⎣ ⎦

≈ + ++

Differential v.s. Single-ended LNA

reject common mode noiseand interferer

shield the bond wire

x double area and current

x need balun at input

x common-mode stability

x linearity limited by bias current


Differential

compact layout sizeless power for same NF

and linearity

x susceptive to bond wire

and PCB trace

x drive single-balance mixer; or

use output balun to drive double-

balance mixer

Single-ended

Differential LNA Common-mode Stability Issue


Typical differential LNA Common-mode half circuit

, 21 2

1min com s

gR LC Cω

⎛ ⎞= −⎜ ⎟

⎝ ⎠Real part:

For passive termination, the real part of the source impedance will always be positive. IF Rin,com happens to be negative and cancel the real part of source impedance, oscillation MAY occur.

( ) 1 2,

1 2

21 1 2

in com g s

m s m

C CZ j L Lj C C

g L gC C C

ωω

ω

+= + +

+ −

Variant of Inductive Degenerated LNA


nMOS-pMOS shunt input

Current reuse to save power

Larger area due to two degeneration on chip inductor

NF: 2dB, Power gain: 17.5dB, IIP3: -6dBm, Id: 8mA from 2.7V power supply

Single-ended version of current reuse LNA (bias not shown)

F. Gatta, E. Sacchi, et al, “A 2-dB Noise Figure 900MHz Differential CMOS LNA,” IJSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452

Variant of Inductive Degenerated LNA


Inter-stage inductor with parasitic capacitance form impedance match network between input stage and cascoded stage boost gain lower noise figure.

Input match condition will beaffected

Single-ended version of current reuse LNA (bias not shown)

Chunyu Xin, and Edgar Sánchez-Sinencio, “A GSM LNA Using Mutual-Coupled Degeneration”, IEEE Microwave and Wireless Components Letters, VOL. 15, NO. 2, Feb 2005

Comparison of LNA Architectures


Resistive Termination

Common Gate

Shunt Feedback

Inductive Degeneration

Noise Figure >6dB 3~5dB 2.8~5dB ~2dB

Gain 10~20dB 10~20dB 10~20dB 15~25dB

Sensitivity to Parasitic

Less Less Less Large

Input Matching Easy Easy Easy Complex

Linearity -10~10dBm -5~5dBm -5~5dBm -10~0dBm

Power 1~50mW ~5mW >15mW >10mW

Highlight Effortless input matching

Easy input matching

Broadband input/out matching

Good narrowband Matching, small NF

Drawback Large NF Large NF Stability Large area

Substrate NoiseA MOS device is in fact a 4 terminal device. The 4th terminal is the substrate.The bulk-source potential modulates the drain current with a transconductance of gmb which has the same polarity as gm(i.e., increasing the bulk potential increases the drain current)The substrate has a finite (nonzero) resistance and therefore has thermal noiseTo reduce Rsub we should put many substrate contacts close to the device

Substrate noise characterization: John T. Colvin et.al: “Effects of Substrate Resistances on LNA Performance and a Bondpad”, JSSC Sep. 1999


( )2 2

, 2

41

subno sub mb

sub b

kTRi f gR Cω

= Δ ⋅+

Substrate Noise(cont.)

Solution: Place as many substrate contact as possible! Pros:

Reduces possibility of latch up issuesLowers Rsub and its associated noise(Impacts LNA through backgate effect (gmb) Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA

Cons: takes up a bit extra area Analog and Mixed-Signal Center, TAMU 47

Package Parasitics

As interface to the external world, the LNA must transit from the silicon chip to the package and board environment, which involves bondwires, package leads, and PCB trace.


Package Parasitics(cont.)

Two effects from bondwire and package inductance:Value of degeneration inductor is alteredNoise from other circuits couples into LNA


Package Parasitics(cont.)Some or all of the degeneration inductor Ls can be absorbed into the bondwire inductanceThese parasitics must be absorbed into the LNA design.This requires a good model for the package and bondwires. It should be noted that the inductance of the input loop depends on the arrangement of the bondwires, and hence die size and pad locations.Many designs also require ESD protection, which manifests as increased capacitance on the pads.For more details, please read:

1. B. Razavi, “Design of Analog CMOS Integrated Circuits (chapter 18) ” McGraw-Hill, New York 2001.

2. Andrzej Szymañski et.al: “Effects of package and process variation on 2.4 GHz analog integrated circuits”, Microelectronics and Reliability, Jan. 2006


Cadence Simulation for LNA


Characterization of the major Figure of merit of an LNA in Cadence

S-parameter simulationinput and output matchnoise figuregain

Periodic steady state (pss) simulation/SPSSIIP2/IIP3, 1dB point

Please refer to Lab 3 manual

LNA Testing: S parameter


Before doing the measurement:

Calibrate two lines.

Adjust the power level

LNA Testing: Linearity(IIP3/IIP2)


Output Signal

RF IN

LNA Testing: Noise Figure


Spectrum Analyzer

Noise Source

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