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ECE65 Course Summary

ECE 65, Winter2013, F. Najmabadi

Devices

Diode iv characteristics equation

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (3/40)

IS : Reverse Saturation Current (10-9 to 10-18 A)

VT : Volt-equivalent temperature (= 26 mV at room temperature)

n: Emission coefficient (1 ≤ n ≤ 2 for Si ICs)

( )1 / −= TD nVvSD eIi

:bias Reverse :bias Forward

3 ||For /

SD

nVvSD

TD

IieIi

nVvTD

−≈≈

≥

For derivation of diode iv equation, see Sedra & Smith Sec. 3

Sensitive to temperature:

IS doubles for every 7oC increase

VT = T(k) /11,600

Diode piecewise-linear model: Diode iv is approximated by two lines


Constant Voltage Model

Sifor V 7.06.0 voltage,in"-cut" and 0 :OFF Diode

0 and :ON Diode

0

0

0

−=<=≥=

D

DDD

DDD

VVvi

iVv

Circuit Models: ON: OFF:

Diode ON

Diode OFF

VD0

Zener Diode piecewise-linear model


0 and : Zener and 0 :OFF Diode

0 and :ON Diode

0

0

≤−=<<−=

≥=

DZD

DDZD

DDD

iVvVvVi

iVv

Diode ON

Diode OFF

VD0

Zener

Circuit Models: ON: OFF: Zener:

Recipe for solving diode circuits


Recipe:

1. Draw a circuit for each state of diode(s).

2. Solve each circuit with its corresponding diode equation.

3. Use the inequality for that diode state (“range of validity”) to check

o if the solution is valid if circuit parameters are all known.

o to find the range of circuit “variable” which leads to that state.

Accuracy of Constant-Voltage Model


Constant Voltage Model Diode ON

Diode OFF

VD0

Diode can be in forward bias with vD as small as 0.4 V when iD is small (Lab 4)

In forward bias, “cut-in” voltage (VD0) can vary between 0.6 & 0.8 V (± 0.1 V)

In forward bias, diode voltage changes slightly as current changes (discussed later in small signal model)

BJT iv characteristics includes four parameters


Two transistor parameters can be written in terms of the other four:

BJT iv characteristics equations are:

NPN transistor

CEBEBC

BCE

vvviii−=

+= :KVL

:KCL

Cut-off : BE is reverse biased Active: BE is forward biased BC is reverse biased (Deep) Saturation: BE is forward biased BC is foward biased

0 ,0 == CB ii

+=

==

A

CEVvSC

VvSCB

VveIi

eIii

TBE

TBE

1/

/

ββ

BCsatCE

VvSB

iiVv

eIi TBE

,

/

ββ

<≈

=

),( )(

CEBC

BEB

vi givfi

==

Transistor operates like a “valve:” iC & vCE are controlled by iB


Controller part: Circuit connected to BE sets iB

Controlled part: iC & vCE are set by transistor state (& outside circuit)

BJT Linear Model

Cut-off (iB = 0, vBE < VD0): Valve Closed iC = 0,

Active (iB > 0, vBE = VD0): Valve partially open iC = β iB, vCE > VD0

Saturation (iB > 0 , vBE = VD0): Valve open iC < β iB, vCE = Vsat

For PNP transistor, replace vBE with vEB and replace vCE with vEC in the above.

V 2.0 ,V 7.0 Si,For 0 == satD VV

* BJT Linear model is based on a diode “constant-voltage” model for the BE junction and ignores Early effect.

Recipe for solving BJT circuits (State of BJT is unknown before solving the circuit)


1. Write down BE-KVL and CE-KVL:

2. Assume BJT is OFF, Use BE-KVL to check: a. BJT OFF: Set iC = 0, use CE-KVL to find vCE (Done!)

b. BJT ON: Compute iB

3. Assume BJT in active. Set iC = β iB . Use CE-KVL to find vCE . If vCE ≥ VD0 , Assumption Correct, otherwise in saturation:

4. BJT in Saturation. Set vCE = Vsat . Use CE-KVL to find iC . (Double-check iC < β iB )

NOTE: o For circuits with RE , both BE-KVL & CE-KVL have to be solved

simultaneously.

MOS i-v Characteristics Equations

NMOS (VOV = vGS – Vtn)

o For PMOS set VOV = vSG – |Vtp| & replace vDS with vSD in the above


[ ]

[ ]DSOVoxnDOVDSOV

DSDSOVoxnDOVDSOV

DOV

vVL

WCiVvV

vvVL

WCiVvV

iV

λµ

µ

+=≥≥

−=≤≥

=≤

1 5.0 and 0 :Saturation

2 5.0 and 0 :Triode

0 0 :Off-Cut

2

2

PMOS NMOS

MOS operation is “Conceptually” similar to a BJT -- iD & vDS are controlled by vGS


Controller part: Circuit connected to GS sets vGS (or VOV )

Controlled part: iD & vDS are set by transistor state (& outside circuit)

A similar solution method to BJT:

o Write down GS-KVL and DS-KVL, assume MOS is in a particular state, solve with the corresponding MOS equation and validate the assumption.

MOS circuits are simpler to solve because iG = 0 ! o However, we get a quadratic equation to solve if MOS in triode (check MOS in

saturation first!)

Foundation of Transistor Amplifiers


MOS is always in saturation (BJT in active)

Input to transistor is made of a constant bias part (VGS ) and a signal (vgs): vGS = VGS + vgs

Response (vo = vDS ) is also made of a constant part (VDS ) and a signal response part (vds): vDS = VDS + vds

VDS , is ONLY related to VGS : o i.e., if vgs = 0, then vds = 0

The response to the signal is linear, i.e., vds / vgs = const. But o vGS / vDS is NOT a constant! o VGS / VDS is NOT a constant!

Issues in developing a transistor amplifier:


1. Find the iv characteristics of the elements for the signal (which can be different than their characteristics equation for bias). o This will lead to different circuit configurations for bias versus signal

2. Compute circuit response to the signal o Focus on fundamental transistor amplifier configurations

3. How to establish a Bias point (bias is the state of the system when there is no signal). o Stable and robust bias point should be resilient to variations in

µnCox (W/L),Vt (or β for BJT) due to temperature and/or manufacturing variability.

o Bias point details impact small signal response (e.g., gain of the amplifier).

Summary of signal circuit elements


Resistors& capacitors: The Same o Capacitor act as open circuit in the bias circuit.

Independent voltage source (e.g., VDD) : Effectively grounded

Independent current source: Effectively open circuit

Dependent sources: The Same

Non-linear Elements: Different! o Diodes & transistors ?

Diode Small Signal Model vd

id rd = nVT/ID

vD

iD

Transistor Small Signal Models


1 2 D

oOV

Dm I

rV

Ig⋅

≈⋅

=λ

Comparison of MOS and BJT small-signal circuit models: 1. MOS has an infinite resistor in the input (vgs) while BJT has a finite resistor, rπ

(typically several kΩ).

2. BJT gm is substantially larger than that of a MOS (BJT has a much higher gain).

3. ro values are typically similar (10s of kΩ). gm ro >> 1 for both.

NMOS/PMOS

C

Ao

T

Cm

B

T

IVr

rVIg

IVr ≈===

ππ

β

NPN/PNP BJT

Transistor Biasing


To make bias point independent of changes in transistor parameters (e.g. β,) the bias circuit should “set” IC and NOT IB !

Emitter Degeneration (BJT):

Requires a resistor in the emitter circuit. Requirements:

1.

2.

V 1 ≥EE RI

)1( min EB RR +<< β

Current source:

Source Degeneration (MOS):

Requires a resistor in the source circuit. Requirement:

1.

GSDS VIR >

Emitter-degeneration bias circuits


Basic Arrangement

Bias with one power supply

(voltage divider)

Bias with two power supplies

MOS source-degeneration bias circuits are identical

To solve circuits with voltage divider bias: 1. BJT: replace voltage divider with its Thevenin equivalent.

2. MOS: Since iG = 0, calculate VG directly.

BJT Current Mirrors are based on two identical transistor with vBE,ref = vBE1


Identical BJTs Qref is always in active since

Identical BJTs and vBE,ref = vBE1

o BJTs will have the same iB and the same iC (ignoring Early effect)

0,,

, 0

DrefBErefCE

refC

VVVi

==

>

βC

CBrefCrefiiiiI 22 :KCL , +=+=

/21

1 refref

C II

iI ≈+

==β

For the current mirror to work, Q1 should be in active:

011 DEECCE VVVV ≥+= Since I1 = const. regardless of

VC1 , this is a current source!

MOS Current-Steering Circuit are based on two identical transistor with vov,ref = vov1


Qref is always in saturation since

OVOVrefOV

GSGSrefGS

trefGSrefGSrefDS

VVVVVV

VVVV

==

==

−>=

1,

1,

,,,

2111

2,

)/(5.0

)/(5.0

OVoxnD

OVrefoxnrefDref

VLWCiI

VLWCiI

µ

µ

==

==

( )( )refref LW

LWII

// 11 =

For the current steering circuit to work, Q1 should be in saturation:

tGSOVDS VVVV −=>1

Identical MOS: Same µCox and Vt

Since I1 = const. regardless of VD1 , this is a current source!

How to add signal to the bias


Bias & Signal vGS = VGS + vgs

Bias & Signal vDS = VDS + vds

1. Direct Coupling

Use bias with 2 voltage supplies o For the first stage, bias such that

VGS = 0 o For follow-up stages, match bias

voltages between stages

Difficult biasing problem

Used in ICs

Amplifies “DC” signals!

2. Capacitive Coupling

Use a capacitor to separate bias voltage from the signal.

Simplified biasing problem.

Used in discrete circuits

Only amplifies “AC” signals

Discrete CE and CS Amplifiers


||

)||||(

oDo

Gi

LDomi

o

rRRRR

RRrgvv

==

−=

i

o

sigi

i

sig

o

vv

RRR

vv

×+

=

|| ||

)||||(

oCo

Bi

LComi

o

rRRrRR

RRrgvv

==

−=

π

∞→ πr

Discrete CE and CS Amplifiers with RE / RS


[ ] )1( ||

/)||( 1

)||(

SmoDo

Gi

oLDSm

LDm

i

o

RgrRRRR

rRRRgRRg

vv

+==

++−=

i

o

sigi

i

sig

o

vv

RRR

vv

×+

=

+++=

+

++=

+++−=

sigBE

EoCo

oLC

EEBi

EoLCEm

LCm

i

o

RRRrRrRR

rRRRRrRR

rRrRRRgRRg

vv

||1 ||

]/)||[(1 ||

)/1](/)||[(1)||(

π

π

π

β

β

Discrete CB and CG Amplifiers

F. Najmabadi, ECE65, Winter 2013, Course Summary for Final (24/40) i

o

sigi

i

sig

o

vv

RRR

vv

×+

=

)]||||(1[ || 1

)||( ||||

)||||(

sigEmoCo

om

LCoEi

LComi

o

RRrgrRRrgRRrrRR

RRrgvv

π

π

+=

+

+=

+=

)]||(1[ || 1

)||( ||

)||||(

sigSmoDo

om

LDoSi

LDomi

o

RRgrRRrgRRrRR

RRrgvv

+=

+

+=

+=

∞→ πr

Discrete CC and CD Amplifiers


1 ||

)||||(1

)||||(

mSo

Gi

LSom

LSom

i

o

gRR

RRRRrg

RRrgvv

=

=+

=

i

o

sigi

i

sig

o

vv

RRR

vv

×+

=

[ ]

||||

||

)||||( || )||||(1

)||||(

osigB

Eo

LEoBi

LEom

LEom

i

o

rRRr

RR

RRrrRRRRrg

RRrgvv

β

β

π

π

+≈

+=+

=

Gain of a multi-stage amplifier


Example: A 3-stage amplifier

2,

3,

1,

2,

1,

1,

1,

3,

1,

o

o

o

o

i

o

i

o

i

o

vv

vv

vv

vv

vv

××== ... 321 ××××

+= vvv

sigi

i

sig

o AAARR

Rvv

But we need to know RL,1, RL,2, RL,3, … in order to find AM s.

2,1, io vv = 3,2, io vv = 3,oo vv =1,1,

1,1, , iisigi

i

sig

i

sig

i RRRR

Rvv

vv

=+

==3,oo RR =

3213,

3,

2,

2,

1,

1,

1,

vvvi

o

i

o

i

o

i

o AAAvv

vv

vv

vv

××=××=

21 io vv = 32 io vv =

What are RL and Rsig for each stage?


Amp Model for Stage j-1

1,, −= jojsig RR1,, += jijL RR

RL for each stage is the input resistance of the following stage.

Rsig for each stage is the output resistance of the previous stage.

Amp Model for Stage j+1

Procedure for Solving multi-stage Amplifiers


Gain & Ri:

1. Start from the load side (nth stage),

o Find the gain Av,n = (vo/vi)n and Ri,n .

2. For (n-1)th stage, set RL,n-1 = Ri,n

o Find the gain Av,n-1 = (vo/vi)n-1 and Ri ,n-1 .

3. Repeat until reaching to the first stage. Then,

Ro:

1. Start from the source side (1st stage). Find Ro,1 .

2. Go to the second stage. Set Rsig,2 = Ro,1 . Find Ro,2

3. Continue to the last stage (nth stage). Then, Ro = Ro,n

... 3211, ××××+

== vvvsigi

i

sig

oii AAA

RRR

vvRR

Cut-off frequency of a multi-stage amplifier


Similar to a single-stage amplifier, each capacitor introduces a pole:

1) Coupling capacitor at the input:

2) Coupling capacitor at the output:

3) Coupling capacitor between stages j-1 and j

4) By-pass capacitors for stage j (if exists)

5) Then:

11 )(2

1

csigip CRR

f+

=π

passbypassbybypassp CR

f−−

= 2

1, π

coLopo CRR

f)(2

1+

=π

cjjojipj CRR

f)(2

1

1,, −+=

π

... 21 ++≈ ppp fff

Diode Functional Circuits

Rectifier & Clipper Circuits


Half-wave rectifier

OFF) (Diode 0 ,For ON) (Diode ,For

0

00

=<−=≥

oDi

DioDi

vVvVvvVv

Clipper

OFF) Diode( ,For ON) Diode( ,For

0

00

ioDi

DoDi

vvVvVvVv

=<=≥

“Clipping” voltage can be adjusted


vo limited to ≤ VD0 + VZ vo limited to ≤ VD0 + VDC

vo limited to ≥ − VD0 − VDC vo limited ≥ − VD0 −VZ

Both top & bottom portions of the signal can be clipped simultaneously


vo limited to ≤ VD0 + VDC1 and ≥ − VD0 − VDC2

vo limited to ≤ VD0 + VZ1 and ≥ − VD0 − VZ2

Peak Detector Circuit

Peak Detector & Clamp Circuits


Clamp Circuit

vo is equal to vi but shifted “downward” by − (V + − VD0)

“ideal” peak detector: τ/T → ∞

“Good” peak detector: τ/T >> 1

vo shifted “downward”

Voltage shift in a clamp circuit can be adjusted!


)( 0DZio VVVvv −−−= + )( 0DDCio VVVvv −−−= +

vo shifted “upward”

)( 0DZio VVVvv −−+= − )( 0DDCio VVVvv −−+= −

BJT as a switch


Use: Logic gate can turn loads ON (BJT in saturation) or OFF (BJT in cut-off)

ic is uniquely set by CE circuit (as vce = Vsat)

RB is chosen such that BJT is in deep saturation with a wide margin (e.g., iB = 0.2 ic /β)

*Lab 4 circuit Solved in Lecture notes (problems 12 & 13)

Load is placed in collector circuit

BJT as a Digital Gate


Other variants: Diode-transistor logic (DTL) and transistor-transistor logic (TTL)

BJT logic gates are not used anymore except for high-speed emitter-coupled logic circuits because of o Low speed (switching to saturation is quite slow). o Large space and power requirements on ICs

RTL NOT gate (VL = Vsat , VH = VCC)

Resistor-Transistor logic (RTL)

RTL NOR gate* RTL NAND gate*

*Solved in Lecture notes (problems 14 & 15)

NMOS Functional circuits


Similar to a BJTs in the active mode, NMOS behaves rather “linearly” in the saturation region (we discuss NMOS amplifiers later)

Transition from cut-off to triode can be used to build NMOS switch circuits. o Voltage at point C (see graph)

depends on NMOS parameters and the circuit (in BJT vo = Vsat)!

We can also built NMOS logic gate similar to a RTL. But there is are much better gates based on CMOS technology!

Complementary MOS (CMOS) is based on NMOS/PMOS pairs


Maximum signal swing: Low State: 0, High State: VDD

o Independent of MOS device parameters!

Zero “static” power dissipation (iD = 0 in each state).

o It uses the fact that if a MOS is ON and iD = 0 only if MOS is in triode and vDS = 0

CMOS Inverter CMOS NAND Gate

How to Solve Problems


1. What is Known? (comes from problem description.)

2. What is the aim? (Indentify circuit parameters that has to be calculated.) 3. How to get there?

(use recipes!)

First, write down all equations that govern the circuit.

Make sure that you have enough equations to solve for the unknowns.

Make sure that you the solution will give you the answer to the problem.

Only the, start solving the equations.

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