ece243-final-2012-nej-4exams.skule.ca/exams/ece243h1_20121_631461601472final... · 2018. 2. 3. ·...

16
Student # (use if pages get separated) ____________________________ ECE243 Computer Organization Pg 1 of 16 Winter 2012 UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING FINAL EXAMINATION, APRIL 2012 Second Year ECE243H1 S – COMPUTER ORGANIZATION Exam Type: D Examiner – P. Anderson, N. Enright Jerger, A. Moshovos Instructions This is a type D exam. You are allowed to use any printed/hand-written material including your course notes. Last Name (Print Clearly): __________________ First Name: ________________________ Student Number: ___________________ ___________________________________________________________________________________________________ Question 1 20 Question 2 20 Question 3 15 Question 4 20 Question 5 30 Question 6 20 Question 7 15 Total 140 General Instructions: State your assumptions. Show your work. Comment your code. Solutions that are judged significantly inefficient will lose some marks. The exam is printed on two sides of the page. The last pages and the back of this one are blank and can be used for answers or calculations. Make your answers clear. There are 7 questions and a total of 140 marks. There are 8 pieces of paper in the exam, this one included, printed both sides. The page numbering is 1-16.

Upload: others

Post on 16-Feb-2021

1 views

Category:

Documents


0 download

TRANSCRIPT

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 1 of 16 Winter 2012

    UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING

    FINAL EXAMINATION, APRIL 2012

    Second Year

    ECE243H1 S – COMPUTER ORGANIZATION Exam Type: D

    Examiner – P. Anderson, N. Enright Jerger, A. Moshovos

    Instructions

    This is a type D exam. You are allowed to use any printed/hand-written material including your course notes.

    Last Name (Print Clearly): __________________

    First Name: ________________________ Student Number: ___________________ ___________________________________________________________________________________________________

    Question 1 20 Question 2 20 Question 3 15 Question 4 20 Question 5 30 Question 6 20 Question 7 15

    Total 140

    General Instructions: State your assumptions. Show your work. Comment your code. Solutions that are judged significantly inefficient will lose some marks. The exam is printed on two sides of the page. The last pages and the back of this one are blank and can be used for answers or calculations. Make your answers clear.

    There are 7 questions and a total of 140 marks. There are 8 pieces of paper in the exam, this one included, printed both sides. The page numbering is 1-16.

    seguljacText BoxANSWER KEY

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 2 of 16 Winter 2012

    Question 1 – Basic Understanding of Assembly [20 Marks] a) Write a sequence of NIOS II instructions that uses two unsigned integer values stored in registers r8 and r9 and stores the maximum of the two in r10: b) A device register has 32 bits in total and is accessed via address 0x8000 0010. Bits 15 through 20 form a 6 bit counter (we count bits starting from 0). Write a NIOS II code sequence that reads the register, increments the aforementioned counter by 1, and writes the updated value back into the register. The rest of the word must remain unchanged. c) Write a NIOS-II assembly function that returns the absolute value of a 32-bit signed integer.

    seguljacText Boxbgtu r8, r9, max_r8 // if (r8 > r9) goto max_r8mov r10, r9 // r10 = r9br done // goto donemax_r8:mov r10, r8 // r10 = r8done:

    seguljacText Boxmovia r8, 0x80000010 // r8 holds the device register addressmovi r9, 0x3fslli r9, r9, 15 // r9 is a mask with bits 20..15 being 1 ldwio r11, 0(r8) // r11 holds the register valueand r12, r11, r9 // r12 will be counter, isolate the counter bitsxor r11, r11, r12 // clear the counter bits movui r10, 0x8000 // 0x8000 is out of range for a signed imm16add r12, r12, r10 // increment the counterand r12, r12, r9 // protect against overflowor r11, r11, r12 // set the counter bitsstwio r11, 0(r8) // write back

    seguljacText Boxabs:bgt r4, r0, positive // if (r4 > 0) goto positivesub r2, r0, r4 // r2 = -r4ret positive:mov r2, r4 // r2 = r4ret

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 3 of 16 Winter 2012

    (d) The single precision floating point representation uses 1 bit for the sign (S), 8 bits for the exponent (S) and 23 bits for the mantissa (M). Let’s call that an S8E23M format. The number represented is:

    (-1)^S x 2^(E-127) x 1.M Given two numbers A and B, in this S8E23M format, what should the output format be so that the following operations do not result in data loss? Briefly explain your answers. (d.1) A + B S_____E______M (d.2) A x B S______E_______M

    seguljacText BoxFor exponent: - we need at least one additional exponent bit (to be able to add two max S8E23M numbers)For mantissa: - lets write numbers like 2^(E-127-23)x1M (we can ignore sign) - 2^(E_1-150)x1M_1 + 2^(E_2-150)x1M_2 = 2^(E_1-150)x[1M_1 + 1M_2 x 2^(E_2-E_1)] - in the worst case E_1=255 and E_2=0, and then the number in the square bracket is 1M_1.000...0001M_2, where we have (255-24) zeroes - this number has (255+24)=279 digits - hence, mantisa needs to be 278 digits

    seguljacText Box278

    seguljacText Box9

    seguljacText Box10

    seguljacText Box 47

    seguljacText BoxFor exponent: - worst case is two maximum numbers, then we need two more exponent bits (one cause exponent overflows, one cause 1.1111111 x 1.111111 = 11.xxxxxx)For mantissa: - 2^(E_1-150)x1M_1 x 2^(E_2-150)x1M_2 = 2^(E_1+E_2-300)x1M_1x1M_2 - 1M_1x1M_2 can have 24+24=48 digits - hence, mantisa needs to be 47 digits

    seguljacText BoxASSUMPTION: No subnormal numbers, no NaN values. That is, the provided formula is valid for ALL values E

    seguljacLine

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 4 of 16 Winter 2012

    Question 2 – C To Assembly [20 Marks] Implement the following C code fragments in NIOS II assembly. If need be you can use the stack which you can assume has been initialized. (a) wow (wow(10, 20), wow (30, 40)); Assume a label “wow:” has been declared somewhere in the same file and that function “wow” returns an integer. (b) struct t_t { int a; int b; int c; } d[1024]; struct s_t {char a; char b; char c} e[2048]; d[e[10].b].c++; Assume that d and e have been allocated in memory and that the labels “d:” and “e:” have been declared previously in the same assembly file.

    seguljacText Boxmovi r4, 10movi r5, 20call wow mov r16, r2 // save the return valuemovi r4, 30movi r5, 40call wowmov r4, r16 mov r5, r2call wow

    seguljacText Boxmovia r8, dmovia r9, eldb r10, 31(r9) // &(e[10].b)= addr(e)+ // 10*sizeof(struct s_t)+ // 1*sizeof(char)muli r10, r10, 12 // &(d[X].c])= addr(d)+add r10, r10, r8 // X*sizeof(struct t_t)+ // 2*sizeof(int)ldw r11, 8(r10)addi r11, r11, 1stw r11, 8(r10)

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 5 of 16 Winter 2012

    (c) int a[256], b[256][128], c[64], d, e, f; boo (a, &b[1], c+4, &d, &e, &f); Assume that a through f have been allocated in memory and that the labels “a:” through “f:” and “boo” have been declared previously in the same assembly file.

    seguljacText Boxmovia r4, amovia r5, baddi r5, r5, 512 //&b[1] = addr(b)+ // 128*sizeof(int)movia r6, caddi r6, r6, 16 // c+4 = c+4*sizeof(int)movia r7, dmovia r2, eaddi sp, sp, -8stw r2, 0(sp)movia r2, fstw r2, 4(sp)call booaddi sp, sp, 8

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 6 of 16 Winter 2012

    Question 3 – Instruction Encoding [15 Marks] In the simple processor we described in our lectures each instruction is encoded using 8 bits. The following instructions were defined:

    Instruction encoding – Bits 7 - 0 Instruction 7 6 5 4 3 2 1 0 Load R1 (R2) R1 R2 0 0 0 0 STORE R1 (R2) R1 R2 0 0 1 0

    ADD R1 R2 R1 R2 1 0 0 0 SUB R1 R2 R1 R2 0 1 1 0 NAND R1 R2 R1 R2 1 0 0 0 ORI Imm5 Imm5 1 1 1

    SHIFT R1 L/R Imm2 R1 L/R Imm2 0 1 1 BZ Imm4 Imm4 0 1 0 1 BNZ Imm4 Imm4 1 0 0 1 BPZ Imm4 Imm4 1 1 0 1

    You have to introduce a new instruction “LOADi R1 Imm3” which does the following: R1 = Mem[K1 + Sign-Extend(Imm3)]; PC = PC + 1 (a) For each of the following instruction encodings, which would be valid? Mark with an

    “X” under the appropriate column. 7 6 5 4 3 2 1 0   VALID   INVALID    

    Encoding (1) R1 Imm3 1 1 0        Encoding (2) Imm3 R1 1 1 0        Encoding (3) R1 Imm3 1 0 1        Encoding (4) Imm3 R1 0 0 0        Encoding (5) R1 Imm3 1 0 0        Encoding (6) Imm3 R1 1 0 0         For those encodings that are invalid, briefly explain why: (b) Out of the ones that are valid, if any, which one(s) you would prefer given the

    implementation we presented during the lectures and why?

    seguljacText Boxx

    seguljacText Boxx

    seguljacText Boxx

    seguljacText Boxx

    seguljacText Boxx

    seguljacText Boxx

    seguljacText BoxOpcode already used

    seguljacText BoxPrefer (5) since datapath already contains paths IR7..6 to RFin and IR5..3 to ALU (although not SE)

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 7 of 16 Winter 2012

    Question 4 – Interrupts [20 Marks] You work for “Jigger, Hertner and Associates”, an engineering firm specializing in embedded systems. A major client of yours is having problems with an orange juice pipeline that runs from Florida to Toronto. One of the valve control systems stops working at random times leaving the pipeline open or closed. All mechanical and electrical systems have been tested and are fine. The prime suspect is the software. The system is NIOS-II based. Here’s a code excerpt that you find suspicious:

    section .exceptions handler: addi sp, sp, -4 stw r15, 0(sp) rdctl r15, ctl3 beq r15, r0, seeya // handle interrupts seeya: ldw r15, 0(sp) addi sp, sp, 4 eret .section .text .start: … // setup interrupts and stack pointer fever: addi sp, sp, -2 sth r15, 0(sp) addi sp, sp, -2 sth r16, 0(sp) call psit ldhu r16, 0(sp) addi sp, sp, 2 ldhu r15, 0(sp) addi sp, sp, 2 // some other processing

    br fever (a) What might be the reason the system malfunctions?

    seguljacText Box1) misaligned (stack) accesses in handler2) skipping interrupted instructions due to not properly subtracting 4 from ea before returning from handler

    HenryCross-Out

    HenryTypewriterctl4

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 8 of 16 Winter 2012

    (b) After successfully solving the previous challenge, a competing firm, “Near Dolphins Unlimited”, made you an offer you couldn’t refuse. You are now asked to solve a similar problem at a water tank valve installation that is based on NIOS-II. You see this suspicious code:

    section .exceptions handler: addi sp, sp, -4 stw r15, 0(sp) rdctl r15, ctl3 beq r15, r0, seeya // handle interrupts seeya: ldw r15, 0(sp) addi sp, sp, 4 eret .section .text .start: … // setup interrupts and stack pointer fever: stw r15, -4(sp) addi sp, sp, -4 call boing addi sp, sp, 4 ldw r15, -4(sp) // some other processing

    br fever What could be going wrong here?

    seguljacText Box1) handler can overwrite r15 stored on stack, if/when interrupt occurs between (1)r15 store and sp decrement and (2) sp increment and r15 load 2) skipping interrupted instructions due to not properly subtracting 4 from ea before returning from handler

    HenryTypewriterctl4

    HenryCross-Out

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 9 of 16 Winter 2012

    Question 5 -- Caches [30 Marks] For this question assume a 4GB byte-addressable address space and a memory interconnect that exposes all 32 address bits. This is different than the NIOS II memory interconnect which only exposes the upper 30 address bits. a) A 64Kbyte, write-through, 2-way set associative data cache has 32-byte blocks. Show how this cache will be indexed:

    TAG SET OFF

    bits = __________ __________ ___________

    b) A 2-way set-associative NIOS II cache is indexed as follows:

    Bits 31 – 16 Bits 15 - 7 Bits 6 - 0 TAG SET OFF

    What is the block size? How many blocks does the cache have? c) A 8MB writeback cache is 8-way set-associative with 128Bytes per block, uses LRU replacement. Calculate how many bits are needed in total for the various parts of the whole cache: DATA bits = _________ TAG bits = __________ Valid bits = __________ Replacement Bits = __________ Dirty Bits = __________ Other bits = __________

    seguljacText Box5

    seguljacText Box10

    seguljacText Box17

    seguljacText Box2^7=128

    seguljacText Box#sets x #ways = 2^9x2=1024

    seguljacText Box8Mx8= 2^26

    seguljacText BoxTAG = 12 bits | SET = 13 bits | OFFSET = 7 bits

    seguljacText Box#blocks = 8MB/128B = 2^16

    seguljacText Box#sets = 2^16/8 = 2^13

    seguljacText Box#blocks = 64KB/32 = 2^11

    seguljacText Box#sets = 2^11/2 = 2^10

    seguljacText Box#blocks x TAG width = 2^16x12

    seguljacText Box#blocks = 2^16

    seguljacText Box#blocks = 2^16

    seguljacText Box#blocks x TAG width = 2^16x12

    seguljacText Box#sets x lg(ways!)=2^13xlg(8!)

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 10 of 16 Winter 2012

    d) A NIOS-II system has a 32 byte direct-mapped instruction cache with 8 byte blocks. In the following NIOS II program ”start:” is mapped to address 0x100. start: I0: movia r8, 0x8000 I1: movia r9, 0x10 I2: add r10, r0, r0 loop: I3: bgt r10, r9, after I4: ldw r11, 0(r8) I5: add r12, r12, r11 I6: slli r11, r11, 3 I7: add r12, r12, r11 I8: slli r11, r11, 2 I9: add r12, r12, r11 I10: addi r10, r10, 1 I11: br loop after: (d.1) If the cache’s blocks are numbered starting from 0 which cache block each instruction maps to? Inst. Cache

    Block it maps to

    Inst. Cache Block it maps to

    Inst. Cache Block it maps to

    I0 I4 I8 I1 I5 I9 I2 I6 I10 I3 I7 I11 (d.2) How many instructions will execute when the above program runs up to but not including the instruction at ”after:”: Instructions executed: _______________ (d.3) How many instruction cache hits and misses will occur then? Hits ________________ Misses _________________ (d.4) How many misses cannot be avoided by simply increasing the cache size?

    seguljacText Box0

    seguljacText Box0

    seguljacText Box1

    seguljacText Box1

    seguljacText Box2

    seguljacText Box2

    seguljacText Box3

    seguljacText Box3

    seguljacText Box0

    seguljacText Box0

    seguljacText Box1

    seguljacText Box1

    seguljacText Box3+17x9+1

    seguljacText Box6+16x7

    seguljacText Box6+16x2+1

    seguljacText BoxI0-I2 + first loop iteration = 6 hits and 6 misses Other iterations=7 hits and 2 missesLast iteration (I3) = 1 miss

    seguljacText Box6

    HenryCross-Out

    HenryCross-Out

    HenryTypewritermovui

    HenryTypewritermovui

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 11 of 16 Winter 2012

    Question 6 – Processor Implementation [20 Marks] The year is 12012, the sun is shining, and you are a renowned computer archeologist. You were working on a recent dig at 43.6617° N, 79.3951° W were you have recently uncovered an engineering handbook labeled “Sally10K”. It describes a multicycle processor implementation. On the very last pages there were notes on how to upgrade the processor design to include one more instruction. It has been a long day as you pored over page after page, and you were just about to start reading the notes on the instruction extension. You remembered that you have to go home to feed Sander and have something to eat as well. Being the workaholic you are, you took the precious notebook with you. That would prove to be a great idea. After finishing preparing dinner, you went to check on Sander and saw this:

    All the wondrous secrets from the notebook are now Sander’s dinner. Or are they? Fortunately, the following survived as shown on the next page: (1) a drawing of the datapath, and (2) a drawing of the control finite state machine for the new instruction. Can you decipher them and reveal what the instruction was? Complete the table below with the RTL statements (the “what is done”) for every cycle using the control information from the datapath drawing on the next page: CYCLE  0   CYCLE  1   CYCLE  2   CYCLE  3   CYCLE  4  PC  =  PC  +  1  IR  =  Mem[PC]              

     

           

    seguljacText BoxR1= RF[IR7,6]

    seguljacText BoxR2= RF[IR5,4]

    seguljacText BoxALUout= R2-1

    seguljacText BoxMDR= MEM[ALUout]

    seguljacText BoxRF[IR5,4]= ALUout

    seguljacText BoxRF[IR7,6]= MDR

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 12 of 16 Winter 2012

    1

    ADD

    0

    X

    X

    X

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 13 of 16 Winter 2012

    QUESTION 7 – Memory System Design [15 Marks] (a) What is the capacity in bytes of the following memory chip? (b) You just ran out of memory while developing your application for an embedded system based on NIOS II. You need to extend your system that currently has 1GB with another 1GB of memory. It’s a holiday and all stores are closed but you need a working system by tomorrow morning. You open your cupboard and you find a 256M x 16 bits chip and two 128M x 16 bits chips. You also have a drawer full of gates, wires, multiplexers, flip-flops, registers, tri-state buffers, and “match” circuits that accept an N-bit input and produce 1 if the input matches a pre-specified number. Use what you have to add 1GB of memory starting at address 0x4000 0000. Assume the NIOS II memory bus discussed in class (given on the next page). Your memory system needs only to support word and half word reads and writes. Your program will never read or write a byte from this memory.

    Complete the diagram on the next page.

    17

    seguljacText Box2^17x4/8B = 2^16B

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 14 of 16 Winter 2012

    seguljacText BoxA29-A2

    seguljacText BoxA28-A2

    seguljacText BoxA28-A2

    seguljacText BoxR/W!

    seguljacText BoxR/W!

    seguljacText BoxR/W!

    seguljacText Box(A31,A30,BE0,BE1,ME)==(0,1,1,1,1)

    seguljacText Box(A31,A30,A29,BE2,BE3,ME)==(0,1,0,1,1,1)

    seguljacText Box(A31,A30,A29,BE2,BE3,ME)==(0,1,1,1,1,1)

    seguljacLine

    seguljacLine

    seguljacLine

    seguljacText BoxANDgates

    seguljacText Box3-state buffer

    seguljacLine

    seguljacLine

    seguljacLine

    seguljacLine

    seguljacLine

    seguljacText BoxR/W!

    seguljacLine

    seguljacText BoxE1

    seguljacLine

    seguljacText BoxE1

    seguljacText BoxE2

    seguljacText BoxE3

    seguljacText BoxDin15..0

    seguljacText BoxDout15..0

    seguljacStamp

    seguljacStamp

    seguljacText BoxE2

    seguljacText BoxE3

    seguljacText BoxDout31..16

    seguljacText BoxDin31..16

    seguljacText BoxDin31..16

    seguljacText BoxDout31..16

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 15 of 16 Winter 2012

    This page is intentionally left blank.

  • Student # (use if pages get separated) ____________________________

    ECE243 Computer Organization Pg 16 of 16 Winter 2012

    This page is intentionally left blank.