ece2030 introduction to computer engineering lecture 16: finite state machines prof. hsien-hsin sean...
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ECE2030 Introduction to Computer Engineering
Lecture 16: Finite State Machines
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean Lee
School of Electrical and Computer EngineeringSchool of Electrical and Computer Engineering
Georgia TechGeorgia Tech
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Mealy and Moore Machines
Combinationalcircuits
Inputs X(t) Outputs Z(t)
StorageElement
S(t)
MEALY MACHINE
Z(t) = {S(t), X(t)}
Combinationalcircuits
Inputs X(t)
Outputs Z(t)
StorageElement
S(t)
MOORE MACHINE
Z(t) = {S(t)}
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State and State Diagram
• A state represents the machine snapshot at a given clock period
• A clock is typically used to synchronize the state transition
• A graph consists of a set of– Circles:
• Each represents a state • Use double circle to represent the initial state
– Directed arc: each represents a state transition– Inputs/outputs
• Mealy machine: – Label input/output along each arc
• Moore machine: – Label input along each arc– Label output inside the circle (i.e. state)
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State Diagrams
Example:State: S(t) {Sk, Sj}
Inputs: X(t) {a, b}Outputs: Z(t) {p, q}Initial state: S(0) = Sk
A Mealy machine example A Moore machine example
Sk Sj
a/p
b/q
b/p a/q
a
b
Sk/p Sj/q
b
a
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State Diagram Examples (Mealy)
S0 S1
0/0
1/1
1/0 0/0
S0S1
0/0, 1/1
0/0
1/0
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State Diagram Examples (Moore)
S0/1 S1/0
0
1
1 0
0, 1
0
1
S0/0 S1/1
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Design Example: Sequence Recognizer
• A sequential circuit that recognizes the occurrence of a particular bit sequence
• Input: X(t) {0, 1}• Output: Z(t) {0, 1}
Otherwise 0,
1101t)3,X(t if1,Z(t)
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Sequence Recognizer
Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16X(t) 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Z(t) 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1
Otherwise 0,
1101t)3,X(t if 1,Z(t)
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Sequence Recognizer
Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16X(t) 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Z(t) 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1
S0 S1
1/0
Otherwise 0,
1101t)3,X(t if 1,Z(t)
0/0 0/0
S2
1/0
S3
0/0
1/0
0/0
1/1
A Meanly Machine
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State Table
00
1/0
0/0 0/0
1/0 0/0
1/0
0/0
1/1
01 10 11
Present StatePresent State Input Input
XXNext StateNext State OutpuOutpu
tt
ZZP1P1 P0P0 N1N1 N0N0
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 1 1
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Logic Circuits Design Steps
• Generate a Boolean function for – Each external output – Each state encoded bit
• Simplify the Boolean functions• Draw a D F/F (or register) for each state
encoded bit• Draw logic circuits for
– External outputs– Each inputs of state encoded bits – Input of state encoded bits = the next state– Output of state encoded bits = the current state
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Logic Circuits Design
Present Present StateState XX
Next StateNext State
ZZ
P1P1 P0P0 N1N1 N0N0
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 1 1 0
1 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 1 1
00 01 11 10
0 0 0 0 1
1 0 1 0 1
XP1P0 N1N1
0101 PPPPXN1
00 01 11 10
0 0 0 0 1
1 1 0 1 0
XP1P0 N0N0
01
010101
PPX)P0P1X(
PPXPXPPPXN0
01PXPZ
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Logic Circuits Design
0101 PPPPXN1 01PPX)P0P1X(N0 01PXPZ
D0F/F
1 2
P0N0
D1F/F
1 2
P1N1
Z
D0F/F
1 2
P0N0
XX
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Example 2
• Input: X(t) {a, b, c}• Output: Z(t) {q, p}
Otherwise p,
sb' of #odd and sa' of #even
has sequence input whenq,
Z(t)
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State Diagram
Otherwise p,
sb' of #odd and sa' of #even
has sequence input whenq,
Z(t)
SEO/q
A Moore Machine
b
SEE/p SOO/p SOE/p
a
ac
b
c
a
C
b
a
bc
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State Table
01/q
b
00/p 10/p 11/p
a
ac
b
c
a
C
b
a
bc
Present State Input (a, b, c) Next State Output
P1 P0 X1 X0 N1 N0 Z
0 0 0 0 1 1 0
0 0 0 1 0 1 0
0 0 1 0 0 0 0
0 1 0 0 1 0 1
0 1 0 1 0 0 1
0 1 1 0 0 1 1
1 0 0 0 0 1 0
1 0 0 1 1 1 0
1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 0 1 1 0 0
1 1 1 0 1 1 0
SEE = 00SEO = 01SOO = 10SOE = 11
a = 00 b = 01 c = 10
p = 0 q = 1
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Logic Circuit Design
Present State
Input Next State Output
P1 P0 X1 X0 N1 N0 Z
0 0 0 0 1 1 0
0 0 0 1 0 1 0
0 0 1 0 0 0 0
0 1 0 0 1 0 1
0 1 0 1 0 0 1
0 1 1 0 0 1 1
1 0 0 0 0 1 0
1 0 0 1 1 1 0
1 0 1 0 1 0 0
1 1 0 0 0 0 0
1 1 0 1 1 0 0
1 1 1 0 1 1 0
X0)(X1P1
X1)P1(X0)X0X1(P1
P1X1P1X0X0X1P1N1
00 01 11 10
00 1 0 X 0
01 1 0 X 0
11 0 1 X 1
10 0 1 X 1
P1P0X1X0 N1
X1P0
P0X1X1P0N0
00 01 11 10
00 1 1 X 0
01 0 0 X 1
11 0 0 X 1
10 1 1 X 0
P1P0X1X0 N0
P0P1Z 00 01 11 10
00 0 0 X 0
01 1 1 X 1
11 0 0 X 0
10 0 0 X 0
P1P0X1X0 Z
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Logic Circuit Design
X0)(X1P1N1 P0P1Z
D1F/F
1 2
P1N1
D0F/F
1 2
P0N0X1
X0
Z
X1P0N0
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Vending Machine State Machine• Dispense a Coke when depositing 15
¢• Inputs
– 5 = a nickel– 10 = a dime– BC = bad coin (including quarters in this
example)• Outputs
– R = reject– C = coke– N = no coke
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State Diagram
0 ¢
BC/R
5 ¢
5/N
10 ¢
10/N
5/C
10/C
5/N
BC/R
10/C
BC/R
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State Table
0 ¢(00)
BC/R5/N
10/N
5/C
10/C
5/N
BC/R
10/C
BC/R
Present State (0¢, 5¢, 10¢)
Input (5¢, 10¢ ,
BC)
Next State (0¢, 5¢, 10¢)
Output (C, N, R)
P1 P0 X1 X0 N1 N0 C1 C0
0 0 0 0 0 1 0 0
0 0 0 1 1 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 1 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 1 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 1 0 1
1 0 1 0 1 0 1 0
X X 1 1 X X X X
1 1 X X X X X X
5 ¢(01)
10 ¢(10)
5: 0010: 01BC: 10
N: 00C: 01 R: 10
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Logic Circuits Design
Present State
Input Next State
Output
P1 P0 X1 X0 N1 N0 C1 C0
0 0 0 0 0 1 0 0
0 0 0 1 1 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 1 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 1 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 1 0 1
1 0 1 0 1 0 1 0
X X 1 1 X X X X
1 1 X X X X X X
11001010N1 XPXPPXXP
00 01 11 10
00 0 1 X 0
01 1 0 X 0
11 X X X X
10 0 0 X 1
P1P0X1X0 N1
10010101N0 XPXPXXPP
00 01 11 10
00 1 0 X 0
01 0 0 X 1
11 X X X X
10 0 1 X 0
P1P0X1X0 N0
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Logic Circuits Design
Present State
Input Next State
Output
P1 P0 X1 X0 N1 N0 C1 C0
0 0 0 0 0 1 0 0
0 0 0 1 1 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 1 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 1 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 1 0 1
1 0 1 0 1 0 1 0
X X 1 1 X X X X
1 1 X X X X X X
X1C1
00 01 11 10
00 0 0 X 1
01 0 0 X 1
11 X X X X
10 0 0 X 1
P1P0X1X0 C1
P0X0X1P1C0
00 01 11 10
00 0 0 X 0
01 0 1 X 0
11 X X X X
10 1 1 X 0
P1P0X1X0 C0
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Logic Circuits of the Vending Machine
X1C1P0X0X1P1C0
P1X1X0P0P1X0X1P0N1 P0X1P1X0X0X1P0P1N0
D1F/F
1 2
P1N1
D0F/F
1 2
P0N0
X1 X0 P0P1
C0
C1