ece102 f11 summary highlights

7/25/2019 ECE102 F11 Summary Highlights

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ECE102: Summary & Highlights

Focusing on Concepts!

ECE 102, Fall 2011, F. Najmabadi


2/24

MOS i-v Characteristics Equations

NMOS (VOV= vGS Vt,n)

[ ]

[ ]DSOVoxnDOVDSOV

DSDSOVoxnDOVDSOV

DOV

vVLWCiVvV

vvVL

WCiVvV

iV

+=

=

=

15.0and0:Saturation

25.0and0:Triode

00:Off-Cut

2

2

PMOS (VOV= vSG |Vt,p|)*

[ ]

[ ]SDOVoxpDOVSDOV

SDSDOVoxpDOVSDOV

DOV

vVL

WCiVvV

vvVL

WCiVvV

iV

+=

=

=

15.0and0:Saturation

25.0and0:Triode

00:Off-Cut

2

2

*Note: S&S defines |VOV|= vSG |Vt,p|and uses |VOV|in the PMOS formulas.


3/24

The response to a combination of VGSand vgs(signal) can be found from the transfer function

Response to the signal appears to be linear!


4/24

Although the overall response is non-linear, the

transfer function for the signal only is linear!

vgs

vds

vGS= VGS+ vgs

vDS= VDS+ vds

iD = IDS + id

Signal and

response

Constant:

Bias

Non-linearrelationship among

these parameters

Linear

relationship amongthese parameters

Bias is the state of the system when there is no signal.


5/24

Bias with Source Degeneration (Discrete circuits)

Basic Arrangement

DSGGS IRVV =

Bias with one power supply

DSGGS IRVV =

)00:(KVL SSDSGSG VIRVR ++=

DSSSGS IRVV =

Bias with two power supply


6/24

Biasing in ICs

Resistors take too much space on the chip. So, source degeneration with

RSis NOT implemented in ICs.

Recall that the goal of a good bias is to ensure IDand VDS that do not

change. One can force ID to be constant using a current source.

1) Current source forces:

IID=

4)GSGSGS VVVV ==

3) VGSis set by

2)(5.0 tGSoxnD VVLWCI =

2)DDDDD IRVV =

5) SDDS VVV =


7/24

Current Mirrors (or Current Steering Circuits)

are used as current sources for biasing ICs

Circuit works as long as Q2 is in

saturation:

Identical MOS:

Same Cox andVt

Q1 is always in saturation since

OVOVOV

GSGSGS

tGSGSDS

VVV

VVV

VVVV

==

==

>=

21

21

111

2

2

2

2

1

1

5.0

5.0

OVoxnDo

OVoxnDref

VL

WCII

VL

WCII

==

==

( )( )1

2

/

/

LW

LW

I

I

ref

o =

tGSOVDS VVVV =>2


8/24

NMOS (or PMOS) small signal circuit model

and0o

ds

gsmdgr

v

vgii +==

D

oI

r

1

OV

Dm

V

Ig

=2

122

>>==

OV

A

OV

omV

V

Vrg

idStatement of KCL

Two elements in parallelInput open circuit


9/24

MOS Amplifier Fundamental Configurations(PMOS circuits are identical)

Common Source with RS

oLSm

Lmv

rRRg

RgA

/1 ++

=

Common Drain/Source Follower

)||(1

)||(

Lom

Lomv

Rrg

RrgA

+

=

Common Source

)||( Lomv RrgA =

Common Gate

)||( Lomv RrgA =


10/24

Elementary Configurations for MOS resistance(PMOS circuits are identical)

Input resistance

of CS Amp

Above configurations are for Small Signal. Typically one or both grounds

are connected to bias voltage sources to ensure that MOS is in saturation!

Output resistance

of CS Amp with Rs

)1(

)1(

Rgr

RRgr

mo

mo

+

++

Input resistance

of CG Amp

ommom

o

rg

R

grg

Rr+

+

+ 1

1

Diode-connected

Transistor

Always in saturation!mo

m gr

g

1||1

or


11/24

MOS as a resistor

MOS acts as a real resistor with its

conductivity controlled byVOV (or vGS).

VL

WCgvgi OVoxnDSDSDSD with ==

MOS acts as a resistor for

signal only.

D

oI

r

1


12/24

Summary of Current Mirrors

Bias Model Small Signal Model

refo

ILW

LWI

1

2

)/(

)/(=

Bias current

goes through

this leg

Signal current

goes through

this leg

(capacitor)

Any circuit that

fixesIref

Equivalent circuit


13/24

Single-transistor MOS amplifiers

with active load/current source

NMOS CS Amp PMOS CS Amp NMOS CD Amp PMOS CD Amp


14/24

4433 )1( oomo rrgr ++

Gain of a Cascode amplifier with a

cascode current mirror/active load

Cascode amplifier: A two-stage, CS-CG circuit

A high gain,Av 0 5g

mro)2, high gain-bandwidth circuit.

Cascode

amplifier

Cascode

current mirror

222212 )||(/ omLomov rgRrgvvA =

22

433

22

4433221

1

)1(

om

oom

om

oomooiL

rg

rrg

rg

rrgrrRR

+

+++==

)||(/22

4331111

om

oomomiv

rg

rrgrgvvA ==

433212

4321321

21 oomoom

oooommm

vvv rrgrrg

rrrrgggAAA

+

==

Value for the

samegmand ro

omv rgA 2

oiL rRR = 21

omv rgA 5.01 =

2)(5.0 omv rgA =


15/24

Summary of Differential Amplifiers

Common-Mode and Differential Signal/Gain and CMRR

Differential amplifier

Concept of half-circuit

Why differential amplifiers are popular

o Large CMRR with a slight mis-match

o Less difficult biasing

Cascode differential amplifiers

Differential amplifiers in ICs

o Biasing

o Current-source active load for two-output Amp.

o Asymmetric active load for one-ended output


16/24

Concept of Half Circuit

Common Mode Differential Mode

For a symmetric circuit, differential- and common-mode

analysis can be performed using half-circuits.


17/24

Common-Mode Half Circuit

id id

id id

0

Common Mode Half-circuit

1. Currents about symmetry line are equal.

2. Voltages about the symmetry line are equal (e.g., vo1= vo2)

3. No current crosses the symmetry line.

21 oo vv =

Common Mode circuit

21 ss vv =


18/24

Differential-Mode Half Circuit

Differential Mode circuit

Differential Mode Half-circuit

1. Currents about the symmetry line are equal in value and opposite in sign.

2. Voltages about the symmetry line are equal in value and opposite in sign.

3. Voltage at the summery line is zero

21 oo vv =

021 == ss vv

id id

id id


19/24

Replacing biasing resistor Rsswith

a current mirror helps in getting a high CMRR

Current mirror is in

the Source Circuit

Analyzed before

(replaceRSSwith ro3)

Small Signal

ro3does not affect the differential gain

ro3 is large and leads to a large CMRR

for slightly mis-matched circuits (recall

we wanted large Rss)

l i l d i


20/24

Replacing load resistors, RD,

with current-source active load

For NMOS difference amplifier, we need PMOS load (similar to a CS amplifier) as

Q1 should see the drain of Q3 in order to see a large R (for signal) and achieve

a high differential gain.

Bias current should flow into the drain of Q1 (and thus out of drain of Q3)

Q3 and Q4 identical

Small

signal


21/24

Typical Frequency response of an Amplifier

Up to now we have ignored the capacitors. To include the capacitors, we

need to solve the circuit in the frequency domain (or use Phasors).o Lower cut-off frequency:fLo Upper cut-off frequency:fHo Band-width:B = fHfL


22/24

Impact of various capacitors depend on the

frequency of interest

f All Caps are short.

Used to find high-

frequency C.

f 0All Caps are open.

Used this to find

low-frequency C.

Mid-band:

High-fcaps are open

Low-fcaps are short.

ComputingfH :

High-f caps are included.

Low-f caps are short

ComputingfL:

High-fcaps are open.

Low-fcaps included.

Impendence of capacitors (1/C)


23/24

MOS high-frequency small signal model

For source connected to body

(used by S&S)

Accurate Model

(we use this model here)

Generally, transistor internal capacitances are

shown outside the transistor so that we can use

results from the mid-band calculations.


24/24

Summary of frequency response

Procedure (low-frequency):

1. Set vsig=0

2. Consider each capacitor separately, e.g., Cn

(assume others are short circuit!)

3. Find the total resistance seen between the

terminals of the capacitor, e.g., Rn(treatground as a regular node).

4. The pole associated with that capacitor is

5. Lower-cut-off frequency can be found from

fLfp1+ fp2+ fp3+

nn

pnCR

f2

1

=

Procedure (high-frequency)

1. Include internal-capacitances of NMOS and

simplify the circuit.

2. Use Millers approximation for Miller

capacitors in configurations with large (andnegative) A.

3. Use time-constant method to findfHa. Set vsig=0

b. Consider each capacitor separately, e.g.,

Cj(assume others are open circuit!)

c. Find the total resistance seen betweenthe terminals of the capacitor, e.g., Rj

(treat ground as a regular node).

4. Do not forget about zeros in CS and CD

configurations.

jj

n

j

H

CRbf

112

1=

==

Identify which capacitors contribute to low-f and which to high-f

ece102 f11 summary highlights

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