ece 683 project report - electrical and computer …bibyk/ee683/bkklfinrep.pdf · ·...

ECE 683 Project Report

Winter 2006

Professor Steven Bibyk

Team Members

Saniya Bhome

Mayank Katyal

Daniel King

Gavin Lim

Abstract

This report describes the use of Cadence software to simulate logic circuits to generate

propagation delay characteristics. The results are tabulated and a general delay

equation is generated for each cell. The equations can then be used to calculate delays

necessary for integrating the cells into larger VLSI cell networks.

1. Executive Summary

1.1 Introduction

This project brings cell designs from ECE 582 and focuses on analyzing delay characteristics

of the cells selected. Such propagation delays define the dynamic performance and cascading

capabilities of logic cells. Multiple load capacitances will be analyzed to create a table of

delay results to generate linearly approximated equations per cell.

1.2 Background Research

Dynamic performance of logic cells can be defined in terms of propagation delays between

the input and output. A shorter delay would mean faster performance of the cell.

1.3 Design Work

Design and simulation work was performed on Cadence design toolkit available at the

Electrical Engineering computer labs. The choice of Cadence is determined by the use of the

software in most colleges and microelectronics manufacturers in the United States. The

operating base for Cadence is UNIX and Windows based software are used extensively for

the report and presentation components.

1.4 Design Approach

Three cells, the AO3111, AO22 and the OA21 have been analyzed for their timing

characteristics in this report. The AO3111 and the AO22 use the pure CCMOS methodology

in which the PMOS is the pull up side and the NMOS is the pull down side. For the OA21, an

inverter gate has been applied along with the basic CCMOS method.

For AO3111, to measure the value of the capacitor rise/fall time, one input, input F has been

pulsed keeping the rest of the inputs at zero volts. This input is the one that affects the output

and gives a discharging curve of the output capacitance. The time taken to discharge from

90% to 10% of the peak value has been taken as the input slope and is applied as the rise time

of the pulsed inputs to get the delay of the cell.

1

For AO21, the similar approach as above is followed and the pulsed inputs are A and B. This

cell gives a discharging output curve also.

In the cell OA21, the inputs A and B are pulsed to give a charging output curve and the

corresponding delays.

1.5 Resources

Personnel were assigned specific tasks for the project to complete and schedule of work was

created for project management. The North Carolina State University Cadence design toolkit

for MOSIS SCMOS processes was utilized for cell components used for the project cell

designs and reference to textbooks used in VLSI courses were referenced as well.

1.6 Schedule and Costs

The time frame assigned for the project is ten weeks during Winter Quarter 2006. A history

of work is chronologically tabulated and no cost to the team was involved since facilities and

equipment were provided in house at OSU.

1.7 Design Review Discussion

The work assigned and accomplished are detailed in the review summary. The intend of the

project was changed from ECE 582 from creating layouts to generating propagation delay

tables. The project is broken down to cell selection and creation, simulations and gathering of

delay results followed by tabulation and calculations. Equations were created for reference to

future user of the cells.

2

Table of Contents

1. Executive Summary 1

2. Table of Contents and List of Tables and Figures 3

3. Introduction 5

3.1 Purpose 5

3.2 Problem Statement 5

3.3 Scope 5

4. Background Research 5

5. Design Work 7

5.1 Design Tools 7

6. Design Approach 8

6.1 Detail Design Work 8

6.2 Selective Analysis 16

6.3 Method of finding Cell Equations 20

7. Resources 22

7.1 Personnel 22

7.2 Facilities and Equipment 22

8. Schedule of Work 23

8.1 Flow Chart 23

8.2 History of Work 23

9. Design Review Strategy 24

10. References 25

Appendix 26

3

List of Tables and Figures

1. Executive Summary 1

2. Table of Contents and List of Tables and Figures

Table of Contents 3

List of Tables and Figures 4

3. Introduction

4. Background Research

Figure 4.1 Propagation Delay Curves 6

5. Design Work

6. Design Approach

Figure 6.1 Analog Environment 11

Figure 6.2 Stimuli 12

Figure 6.3 Setting Input Values 13

Figure 6.4 Analysis Window 14

Table 6.5 Cells Selected 15

Figure 6.6 Cell Logic Selected for Analysis 16

Table 6.7 Truth Table for Selected Cell 16

Figure 6.8 Cell Schematic Design 17

Figure 6.9 Standard Transient Response 17

Figure 6.10 Input Slope Determination 18

Figure 6.11 Output Delay Determination 19

Table 6.12 Delay tables and equations 19

7. Statement of Work

Table 7.1 Personnel Duties and Responsibilities 22

4

3. Introduction

3.1 Purpose

This document proposes a project to generate cell delay tables based on logic cell schematics

generated in ECE 582. With delay tables generated, cell performance and propagation delay

buffers can be optimally implemented during future use of the cells that will be part of the

Digital Cell Library at The Ohio State University Department of Electrical and Computer

Engineering (ECE).

3.2 Problem Statement

In ECE 582, teams were assigned cells to add into the existing OSU digital cell library. With

the foundation of additional cells, studies of delay of cells will enhance the cell library for

future users to incorporate into VLSI projects.

3.3 Scope

The project will have three cells selected to study propagation delay characteristics, standard

input delays are determined and simulated with the cells to generate tables of delay values.

Multiples of a chosen base load capacitances are used during the simulation to generate a

trend in the delays generated to be analyzed.

4. Background Research

Dynamic performance of logic cells are characterized in terms of time delay between the

switching of the inputs and corresponding change in the outputs. The time delay is also

known as a propagation delay of the cell. A short propagation delay would mean a faster

performance of the cell. [1]

5

A delay for a logic cell can be viewed from two perspectives. A rising delay if the signal

from the output pin is rising and vice versa. Propagation delays can be determined by plotting

input and output curves and computing from the time delay between 50% of the input

magnitude and 50% of the output magnitude. (Fig. 4.1)

Figure 4.1 Propagation delay curves [2]

Delay models are useful to determine performance parameters and take into consideration

losses within the circuitry, such as: [2]

1) Cell propagation delay between input and output through interconnects and resistance and

capacitances.

2) Interconnection wire delay across metal wires.

3) Timing requirements such as recovery time, pulse widths, etc.

4) Derating factors such as junction temperature, power supply voltages, and process

variations

6

5. Design Work

The task of ECE 683 is to make use of cells created in ECE 582 and generate standard delay

tables from simulating the cells with various load capacitances using Cadence. From the

delay tables the propagation delay of each cell can be analyzed for implementation to larger

VLSI circuits with more accurately calculated buffers.

5.1 Design Tools

The Cadence toolset is a complete microchip EDA system, which is intended to develop

professional, full-scale, mixed-signal microchips and breadboards. The modules included in

the toolset are for schematic entry, design simulation, data analysis, physical layout, and final

verification. The Cadence tools at Ohio State University are the same as those at most every

professional mixed-signal microelectronics company in the United States. The strength of

the Cadence tools is in its analog design/simulation/layout and mixed-signal verification and

is often used in tandem with other tools for RF and/or digital design/simulation/layout, where

complete top-level verification is done in the Cadence tools. [3]

Another important concept is that the Cadence tools only provide a framework for doing

design. Without a foundry-provided design kit, no design can be done.

All equipment and facilities for this project will be provided by the Ohio State University

Electrical and Computer Engineering Department. The facility that will be used extensively

will be the OSU’s Electrical Engineering Dreese UNIX lab and the Windows PC lab

connected remotely to the UNIX stations through XWin32. All the computer work will be

done in Cadence, Microsoft Word, and Microsoft Paint.

7

6. Design Approach

The combination of group members from different teams from ECE 582 expands the cell

logic concepts used in schematic design. Two main ideas of cell designs were taken from

previously created cells, namely using complementary CMOS logic and pull-up/pull-down

technique incorporating DeMorgan’s Theorem.

The systems designed using complementary CMOS logic gates, also called static CMOS

gates. In general, a fully complementary CMOS gate has a nMOS pull-down network to

connect the output ‘0’ (GND) and pMOS pull-up network to connect the output to ‘1’ (Vdd).

This is because a nMOS transistor is an almost perfect switch when passing a ‘0’ and thus it

is said that it passes a strong ‘0’, however it passes a degraded or weak ‘1’. Vice versa is true

for pMOS and hence it is necessary to have a pull-down and pull-up network. The networks

are arranged such that one is ON and the other is OFF for any input pattern.

The standard set of CMOS cells will be used, which are NANDs, NORs, and Inverters. An

OR gate will be represented by placing a NOR gate in series with an inverter to compliment

the output of the NOR gate, and an AND gate will be represented by placing a NAND gate in

series with an inverter to compliment the output of the NAND gate.

6.1 Detailed Design Work

Three cells have been analyzed for their timing characteristics namely, the AO3111, AO22

and the OA21. The AO22 which was designed during the course of ECE 683 by a team

member who was not in VLSI in ECE 582, AO3111and OA21 have been carried forward

from the ECE 582 VLSI project work.

The basic design approach for the AO22 and the AO3111 has been the CCMOS methodology

which consists of the pull-up and the pull-down sides while laying out the schematic. The

pull-up side has the PMOS transistors and the pull-down side has the NMOS transistors. Both

8

the sides are designed with the AND gate as series transistors and OR gate as the parallel

transistors. The pull-down side has a property of inversing the input and hence making the

AND gate a NAND gate and the OR gate into a NOR .In this method, the cell’s original logic

equation is either applied to the pull-up or the pull down depending on which is more

convenient. The other side is then the De- Morgan’s compliment of the cell equation.

For the OA21 cell, use of inverters in combination with complimentary logic is employed.

Since negative logic is favored in VLSI design, using inverters to generate the AND output

require will result in faster switch timing compared to a regular AND gate logic.

PMOS widths are sized double of NMOS width due to the inherently slower performance of

PMOS. Increasing the widths will increase the current carrying capacity and therefore

matching the PMOS performance with the NMOS performance.

Once the schematics of the cells are ready, the timing characteristics are studied by applying

four different load capacitances at the output. The base capacitor load value is 7f F and the

following quantities are 4x, 10x and 50x the base value.

On the schematic, the capacitor is attached at the output and to get the rise time/ fall time of

the cell through a transient analysis. For calculating the rise/fall time of the circuit, the analog

environment (Fig. 6.1) is used to set the variable values in the stimuli (Fig. 6.2) option under

the Setup menu item. Only those inputs are pulsed which are directly influencing the output.

The rest of the inputs are left at zero volts. At this moment all the inputs have an infinite

slope. The ground and the VDD are given a voltage DC value of 0 and 5 volts respectively.

In the analysis (Fig. 6.3) option, a stop time is fed in after clicking on ‘trans’ for the transient

analysis. Under the output option in the main window, select to be plotted on the

schematic. On the schematic choose the Vout line. On the main window again, under

simulation, choose netlist and run to get the transient plot. On the plot, the crosshair markers

A and B will be used to mark and measure the time between the 5% and 90 % of the peak

9

value of the transient. This is in accordance to the definition of the rise time given by

McGraw-Hill Dictionary of Scientific and Technical Terms, 5th Edition, Sybil P. Parker,

editor, McGraw-Hill, New York, 1994, which states; the time required for the output of a

system to change from a specified small percentage (usually 5 or 10 percent) of its steady-

state increment to a specified large percentage (usually 90 or 95 percent)

For the AO3111 cell, only the input F is pulsed with the output. Also, as seen from the cell’s

logic diagram, pulsing F will generate a low output which in turn implies that the capacitor

tends to discharge.

For the AO22 cell, both inputs A and B are pulsed with the output which again gives a low

output and hence the capacitor discharges.

For the OA21 cell, both inputs A and B are pulsed with the output which gives a high output

and hence the capacitor charges.

The delay time are measured by taking the time difference between the input and output

slopes at 50% magnitude.

10

Figure 6.1 Analog Environment

11

Figure 6.2 Stimuli

Setting Vdd magnitude

12

Figure 6.3 Setting input values

Input parameters

Low to high input pulse

13

Figure 6.4 Analysis Window

14

Table 6.5 Cells selected

Cells types

2 input OR into a 2 input NAND (OA21)

Two 2 input AND into a 2 input NOR (AO22)

3 input AND into a 4 input NOR (AO3111)

15

6.2 Selective analysis

Below is one selected cell used for analysis within the report, the cell logic, design and

simulations are presented. One set of output plots is presented for demonstration purposes

together with delay tables and equations for all three cells. Delay slope and output plots for

the rest of the cell and load conditions are presented in the Appendix section.

Figure 6.6 Cell logic selected for analysis

Two 2 input AND into a 2 input NOR (AO22)

Table 6.7 Truth Table for selected cell

The indicated input parameters were used in the simulations. “X” are “don’t care” conditions

which are left to a value of 0 in the simulations.

16

Figure 6.8 Cell schematic design

Figure 6.9 Standard Transient response

17

Figure 6.10 Input slope determination

Parameters used:

Load Capacitance = 7f F

Delay (10% - 90%) = 716 ps

18

Figure 6.11 Output delay determination

Delay at 50% output magnitude = 539 ps

Table 6.12 Delay tables and equations

AO22 (Rising input ramp)

capacitance slope 7f F 28f F 70f F 350f F

716.99ps 538.88ps 791.64ps 1259.30ps 4284.38ps 1194.60ps 621.92ps 870.54ps 1338.29ps 4368.67ps 2151.64ps 760.23ps 1040.35ps 1502.71ps 4522.84ps 8564.46ps 1089.27ps 1590.61ps 2364.71ps 5665.20ps

Delay, d = Cout * 12.6307 + Slopein * 0.11953 +365.5

19

AO3111 (Rising input ramp)

capacitance slope

7f F 28f F 70f F 350f F

253.68ps 187.94ps 316.24ps 573.97ps 2289.88ps

516.50ps 229.48ps 360.27ps 617.55ps 2332.07ps

1042.75ps 265.65ps 440.79ps 703.11ps 2420.59ps

4551.94ps 52.48ps 449.66ps 983.36ps 2975.30ps

Delay, d = Cout * 6.63 + Slopein * 0.125 + 103

OA21 (Falling input ramp)

capacitance slope 7f F 28f F 70f F 350f F

214.30ps 133.26ps 215.41ps 369.86ps 916.14ps

356.24ps 154.88ps 237.83ps 387.21ps 931.20ps

525.29ps 172.63ps 265.07ps 409.44ps 950.52ps

1620.71ps 219.64ps 364.66ps 525.40ps 1069.52ps

Delay, d = Cout * 2.204 + Slopein * 0.094 + 143.123

6.3 Method of finding the cell equation:

The cell equation as given below takes into account the unknowns, the capacitance Cout and

the input slope Sin and the constants connected to the two variables.

Delay, d = Cout * dt/dc + Slopein * dslope/dt + K

The first approach of finding the equation took into account only the changing capacitance

Cout. The constant of Cout was calculated by:

• The slope of the dt/dc is calculated for all the four input slopes and averaged out. This

is done by graphing the four delay values versus the capacitance at four different

20

input slopes. This means that there are four graphs generated for each input slope to

get four dt/dc values.

• The above step however, takes into account only the Cout variable. The changing

input slope has to be incorporated in the equation too. To find the input slope

constant, four graphs were generated for the input slope versus the delay values at

each of the capacitance values. Again, there were four graphs generated for each

capacitance to get four dSlopein/dt values. The average of the four slope values was

the Slopein constant.

• The next task was to calculate the constant K. By feeding the constant values in the

equation along with a particular capacitance and corresponding input slope value, the

constant k is calculated by subtracting the actual delay corresponding to the input

slope and the capacitance from the constant calculated by feeding the values.

d – Cout*dt/dc – Slopein*dSlopein/dt = K

• This equation was applied to all the Cout and the Slopein values to get an averaged

value for k which worked for the equation.

21

7. Resources

7.1 Personnel

Table 7.1 Personnel Duties and Responsibilities

Saniya Bhome Cell design and Cadence simulations

Results analysis

Mayank Katyal Cell design and Cadence simulations

Results analysis

Daniel King Schedule of work

Gavin Lim Cell design and Cadence simulations

Logistics

7.2 Facilities and Equipment

The software program that will be used in creating the schematics and layout for each cell

will be Cadence. The North Carolina State University cadence website containing tutorials

for the setup of Cadence and sample project was utilized in the setting up and simulation of

the logic cells selected. Utilizing the Cadence Design Kit for the MOSIS SCMOS processes

(Cadence ICFB) developed by NCSU to create the cell schematic, parts for the cells are take

from the NCSU analog parts library. Virtuoso will be used in testing the circuits for

optimized performance. The reference textbook that will be used will be CMOS VLSI

Design: A Circuits and Systems Perspective by Neil H.E. Weste and David Harris as well as

Microelectronic Circuits by Sedra and Smith. Some of the information provided by the

authors on their textbook website will also be used.

22

8. Schedule of Work

The time frame allowed for the completion of the simulation, calculations and report writing

will be ten weeks from the start of Winter Quarter 2006. A final presentation and report

submission will be completed by the end of the quarter.

8.1 Flow Chart

8.2 History of work

Week Work Performed

Week 1 Review of ECE 582

Week 2 Review of cell logic and Cadence

Week 3 Meeting and task details

Week 4 Begin cell simulations

Week 5 Individual Midterm Reports

Week 6 Simulation result tabulation and calculation

Week 7 Begin final report preparation

Week 8 Plot captures and final report preparation

Week 9 Final Report/Presentation Preparation

Week 10 and 11 Presentation and wrap up

23

9. Design Review Discussion

The focus of ECE 683 was initially thought of as a continuation of the work done in ECE 582

where cells designed will be future developed into a working layout and eventually tested

before fabrication.

The project direction was shifted to more in depth analysis of the cell design to focus on

digital timing and create a set of delay tables for future synthesis. The first step undertaken

was to review Tanner’s standard AMI 0.5 cell library and review the timing characteristics

and equations derived for their cell library. It was determined that the delay was to be

somewhat linear and some approximations will be taken with the simulated results.

The determination of the input delay was derived from applying an infinite step input to the

logic circuit to get the delay timing, then applying the delay timing as an input slope into the

same circuit for the delayed outputs. From the output delay, it was determined that the delay

time should be recorded as a difference between the time when the input and output reaches

50% of the maximum magnitude. This method was kept consistent through all three circuits

used to create delay tables for this project.

Graphs are created based on the delay results and using straight line approximations,

constants for the equation desired was determined by averaging constants for each delay

result. The equations derived allows users to mathematically compute output delay for each

cell with load capacitance and input slope (delay) values.

24

10. References [1] A. Sedra & K. Smith. Microelectronic Circuits. Oxford University Press. 2004. [2] Samsung ASIC. STD90/MDL90 documentation. [3] OSU ECE. Cadence Central. Web documentation. http://www.ece.osu.edu/cadence/

25

http://www.ece.osu.edu/cadence/

Appendix

AO3111 SCHEMATIC:

26

AO3111 DISCHARGE PLOTS & TIMES FOR DIFFERENT CAPACITANCES:

Discharge time with 7f F: 253.68ps

27



28


29

AO3111 DELAY PLOTS AND TIMES WITH DIFFERENT SLOPES:

Delay when 253.68ps slope is applied to the input with 7f F at the output: 187.94ps


30



31



32



33



34



35



36



37

38

AO22 SCHEMATIC:

AO22 DELAY PLOTS AND TIMES WITH DIFFERENT SLOPES:



39



40



41



42



43



44

45

OA21 SCHEMATIC:

OA21 DELAY SLOPES WITH INFINITE PULSE INPUT

Delay for 7f F: 214 ps

Delay for 28 fF: 356 ps

46



47

OA21 DELAY PLOTS AND TIMES WITH DIFFERENT SLOPES:

Delay when 214 ps slope is applied to the input with 7f F at the output: 133 ps

48



49


50



51


52



53


54



55



56



57

ece 683 project report - electrical and computer …bibyk/ee683/bkklfinrep.pdf · ·...

Documents