ece 555 design project – phase 2: cell...

April 11, 2002

ECE 555 DESIGN PROJECT – Phase 2: Cell Design

Charles R. Kime Dept. of Electrical and Computer EngineeringUniversity of Wisconsin – Madison

Due: Tuesday, April 30 – No Grace Period; 150 points

Reminder: Only one Phase 2 project report is to be submitted by each team. Duties are tobe shared equitably among team members; each team member is to review the work of theothers for correctness and design quality to insure good results. This review which is to bedone in detail has two goals: 1) to improve the quality of the project and 2) to make surethat all team members are familiar with all aspects of the material the project. Team contri-butions to this phase are to be detailed on the form provided at the end of this report. Shar-ing of designs between teams is NOT permitted.

In this phase, you are to: 1) Select the best inverter from Phase 1 among those designed by the team members - bestimplies: 1) meets specifications, 2) has minimum area, and 3) consumes minimum power.2) Review the inverter design and simulations for correctness and to see if it can beimproved. 3) Design and simulate six standard cells as specified. Some of these cells are standardstatic gates, but others are to use transmission gates in their implementation. All logicdesigned is to be static logic, not dynamic logic.4) The standard cell functions selected are targeted specifically for implementation of anadd-and-shift multiplier in Phase 3. The cell symbols will be entered into a Mentor Graph-ics da schematic with automatic place and route of the layout in Mentor Graphics ic andverification and characterization of the multiplier from the layout using HSpice simula-tion.

SPECIFICATIONS AND PARAMETERS

The following specifications and parameters apply to all gates and to static standard cellsunless specified otherwise (which frequently happens!).

1

LAYOUT SPECIFICATIONS

Specifications Ptotal (evaluated at fminimum) = the minimum possible while meeting other specs.

Area A (bounding box area) (bounding box − a box just large enough to contain the entirecell - be very careful in measuring it with the cursor!) = minimum.

Any standard cell must be able to be placed adjacent to itself and to any other standard cellwithout any design rules violation.

The origin (0,0 point) is to be located at the lower left corner of the horizontal GND metal1in all cells. Instructions are provided in a tutorial for moving the origin to this location ifnecessary.

Process Parameters http://www.cae.wisc.edu/~kime/555/s02/technology/n96g-params.txt

SPICE model http://www.cae.wisc.edu/~kime/555/s01/technology/spice_models/TSM035.L49

Device Parameters for Manual Calculations

VT0,n = 0.3 V

Kn' = 50E-6 A/V2

VT0,p = -0.3V

Kp' = 20E-6 A/V2

LINTn = 0.016 µ and WINTn = 0.056 µ (for manual calculations)

LINTp = 0.0017 µ and WINTp = 0.050 µ (for manual calculations)

tox = 7.7 x 10-9 m(The above may appear strange, but match that actual IV characteristics well.)

Circuit Parameters VDD = 3.3 VCint, max = 100 fF (Represents a long interconnect not including FO loading) FO = 20 inverter equivalents

Layout Parameters λλλλ = 0.2 µ, λ/2λ/2λ/2λ/2 = 0.1µ (The smallest division for layout is λ/2.)λ/2.)λ/2.)λ/2.)Ldrawn,min = 0.4 µ and Wdrawn,min = 0.6 µLdrawn,max = 0.4 µCell Height − absolutely fixed at 100 λ; use of any other height will be severely penalized. Cell Width − as wide as necessary to meet delay goals.

LAYOUT SPECIFICATIONS

The layout style is to be a polycell (stacked standard cell) style in which there are rows oflogic gates with spaces between rows for routing interconnections between gates. Thesespaces are called routing channels. The general structure of the layout is shown below. Youwill be designing and laying out the standard cells and then, from a modified version ofyour logic diagram done in da, will use automatic place and route to produce your multi-

2 ECE 555 DESIGN PROJECT – Phase 2: Cell Design

http://www.cae.wisc.edu/~kime/555/s02/technology/n96g-params.txt

http://www.cae.wisc.edu/~kime/555/s02/technology/n99g-params.txt

http://www.cae.wisc.edu/~kime/555/s01/technology/spice_models/TSM035.L49

STANDARD CELL FUNCTION AND IMPLEMENTATION SPECIFICATIONS

plier layout. The design rules to be used are the submicron (SUBM) rules given in theTechnology folder on the course website.

A typical gate cell should take the form of Figures 7.14 and 7.15 in the text. The MetalVDD and GND ‘‘rails’’ are 10 λ wide and have their center lines spaced 90 λ apart givinga total height of 100 λ for our technology. Metal 1 will be used within the cells where itcan be used for either horizontal or vertical connections. Metal 1 be used outside of thecells for horizontal connections. Metal 2 will be used only outside of the cells for verticalconnections. It should be used in standard cells only for ports. Cells should be designedso that they can be butted against adjacent cells of any kind on the left and the right with-out design rule violations. There is to be one substrate contact per each pair of nFETs andone well contact for each pair of pFETs. All signal inputs and outputs should be near thevertical center of the cell and all ports to connect to the cell should be Metal 2. Portsshould be located so that all of them can be simultaneously reached by Metal 2 intercon-nect from both the top and bottom of the cells without design rule violations. The origin ofa cell is to be at the lower left corner of the GND metal 1.


This section contains the general functional specification and the design ground rules foreach of the standard cells. Note that the design done for some of the standard cells isusable by “copy and paste” in the design of other standard cells. Potential uses of thedesign of a cell internals in other cells are represented in the following graph; this graphrepresents dependencies that heavily effect the scheduling of team tasks. Also, a roughorder of difficulty (OD) is assigned to each of the cells to assist in distributing effortequally across the team.

Metal 2 direction

Metal 1 direction

Standard cells

VDD

GND

90 λ

VDD

GND

Standard Cell

Ports

ECE 555 DESIGN PROJECT – Phase 2: Cell Design 3


2-input NAND gate The two-input NAND gate is to be a standard full CMOS implementation with the initialdesign done using the “n-times” method on the inverter NFETS. It is to meet the samespecifications as the inverter if possible. OD = 1.

3-input NAND gate The three-input NAND gate is to be a standard full CMOS implementation with the initialdesign done using the “n-times” method on the inverter NFETS. It is to meet the samespecifications as the inverter if possible. OD = 1.

Transmission gate multiplexer, TG_MUX

The transmission gate multiplexer, TG_MUX is to be designed to have tp no greater than

0.70 ns. The TG_MUX layout is the most heavily used layout in designing other cells. TheTG_MUX has an output that is from the transmission gates, so TG_MUX’s can be cas-caded only two deep to avoid excessive delay growth. OD = 2.

XOR gate The XOR gate is to be designed to have tp no greater that 1.0 ns. OD = 2.

Static Manchester Carry Chain, SMCC

The 4-bit static Manchester carry chain, SMCC, is to be implemented using a technologythat is fast and does not heavily load the driving gates. The symbol for this circuit is givenbelow. The traditional Manchester carry chain is a dynamic circuit using precharge. Toavoid dynamic circuit design, we replace the NFETs in the Manchester carry chain withtransmission gates. Inputs consist of a carry input, Cin, four propagate functions, Pi, i = 0,..., 3, and four generate functions, Gi, i = 0, ... , 3. The outputs consist of four carry out-

puts, Ci, i = 1, ..., 4. The generate inputs are complemented in order to permit 2-inputNAND gates rather than AND gates to produce them. OD = 3.

D Flip-flop with reset The flip-flop is to be a positive edge-triggered D with an active-low direct reset R. OD = 3.

Inverter Trans. Gate MUX 2-NAND 3-NAND

CLA XOR D Flip-Flop

P0P1P2P3 G0G1G2G3

Cin

C1C2C3C4

CLA


Design and Simulation Details


For the smaller circuits (not the SMCC or the D flip-flop), pre-layout HSPICE simulationis not required. For the SMCC and the D flip-flop, pre-layout HSPICE simulation isoptional, but recommended to pre-size devices prior to layout. Copies of all tables to becompleted are given at the end of this write-up.

NAND gates 1. Initial Device Sizing. Find the device widths to be used in the layout by applying the “ntimes” method to the inverter for 2-input and 3-input NAND gates.

2. Simulation Environment.

Since the input load a gate presents is greater than one inverter equivalent (IE), the currentinto the gate cannot be simply multiplied by using a current generator to ground with again of FO – 1. The DRIVE subcircuit shown above gives the proper value of FO on theinputs to the gate. The fanout load on an input inverter consist of the actual load presentedby a gate input, the load of a single inverter and a load provided by a current generator thatis large enough to give a total of FO inverter loads. To produce your value of FO with thecircuit, the gain of the current generator should be:

GAIN = FO – 1 – (# of inverter equivalents for a gate input)

For NAND gates, the value in parentheses is:

Width of pFET + Width of nFET for the gateWidth of pFET + Width of nFET for the inverter

with the drawn widths adjusted for WINTp and WINTn respectively.

The LOAD subcircuit is the same as used for the inverter.

3. Cell Layout and Extraction. a) Lay out each of your two standard cells using ic. Eachcell must be able to abut edges with every cell type designed without design rule viola-tions.

b) For each cell, extract an HSPICE netlist and carefully edit the HSPICE file checking allconnections, eliminating incorrect or contradictory specifications. Note that interchange ofsource and drain on devices in extracted files is not a problem since HSPICE determineswhich is the source and which is the drain based on the voltage values during simulation.Add the simulation environment.

Vin

Cint

Cint

Cint(rise and fall times equal to τP)

Gate

Place DRIVE on each of these too! GAIN x IA

IA

(FO – 1) x IB

IB

Cint

LOADDRIVE

Model inverters with editedinverter netlistextracted



4. HSPICE Simulation. a) Use HSPICE to verify that all static and dynamic parameterspecifications are met using the guidelines listed in the tables on the next page. Also, thistime, you should do multiple simulations for different combinations of inputs changing.For example, for static parameters for a 3-input gate, you should do: 1) a VTC for allthree-inputs changing, 2) a VTC for the top input alone changing, 3) a VTC for the middleinput alone changing and 4) a VTC for the bottom input alone changing. All of these VTCshould be done with replicated circuits, drivers and loads with different inputs in a singlefile and should be displayed in a single plot. Each static parameter should be extracted torepresent the worst cases across all four VTCs. For dynamic parameters for a 3-inputNAND gate, simulate cases 1, 3 and 4 from the static cases with changes in both direc-tions.

5. Design iteration. If a cell does not meet specifications, if possible, modify, extract, andsimulate the layout until it does. If delays are better than the delay specifications, thenmodify the circuit to minimize the bounding box area (reduce the cell width without mov-ing the VDD and GND rails) and power consumption while just meeting the delay specifi-cations.

6. Cell Generation. Generate the cell symbol for use in Mentor Graphics da.

7. Submissions. For each of the two gate designs, submit the final layout, the netlist, thefinal combined VTC plot for all input cases, and the final worst case dynamic simula-tion plots after all iterations are complete. Characterize your gate cells by submitting thetwo tables containing final simulation-based values.



2-input NAND TABLE

* Worst case for all changes simulated

3-input NAND gate table


PARAMETERSPECIFI-CATION

2-inputNAND

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

Vth 1.65 ± 0.60 V

NMH ≥ 0.8V

NML ≥ 0.8V

(tPHL + tPLH)/2* ≤ 1.0 ns

Ptotal=Pdynamic Minimum


3-inputNAND

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

Vth 1.65 ± 0.60 V

NMH ≥ 0.8V

NML ≥ 0.8V





TG MUX (Transmission gate MUX)

1. Initial Design. The function of the TG MUX is:

OUT = S D1 + S D0

The TG MUX consists of an inverter and two transmission gates. The inverter generates Sfrom S. The first transmission gate with control S has D1 attached to one end and OUTattached to the other. The second transmission gate with control S has D0 attached to oneend and OUT attached to the other. The target worst case delay from any of the inputs tothe output has a target of tp = 0.70 ns. You are to attempt to reach this value by sizing thetwo devices in the transmission gates and by sizing the input inverter generating S.




For the TG MUX, the value in parentheses for the various inputs is estimated as:

1 for inputs D1 and D0

2 for input S.The LOAD subcircuit is the same as used for the inverter.

3. Cell Layout and Extraction. a) Lay out your TG MUX using ic. The cell must be ableto abut edges with every cell type designed without design rule violations.

b) For your cell, extract an HSPICE netlist and carefully edit the HSPICE file checking allconnections, eliminating incorrect or contradictory specifications. Note that interchange ofsource and drain on devices in extracted files is not a problem. Add the simulation envi-ronment.

4. HSPICE Simulation. a) Use HSPICE to verify the parameter specifications given for theTG_MUX in the table below. The following delay measurements should be made: 1)change in S in both directions with D1 = 1 and D0 = 0, 2) change in S in both directions

Vin

Cint

Cint


TGM

Place DRIVE on each of these too! GAIN x IA

IA

(FO – 1) x IB

IB

Cint

LOADDRIVE


S OD1D0



with D1 = 0 and D0 = 1, 3) change in D1 in both directions with S = 1, and 4) change inD0 in both directions with S = 0. From these, the worst case value of tp can be derived.

5. Design iteration. If a cell does not meet specifications, if possible, modify, extract, andsimulate the layout until it does. If delays are better than the delay specifications, thenmodify the cell to minimize the bounding box area (reduce the cell width without movingthe VDD and GND rails) and power consumption while just meeting the delay specifica-tions.

6. Cell generation. Generate the cell for use in Mentor Graphics da.

7. Submissions. For the TG_MUX design, submit the final layout, the netlist, the worstcase dynamic simulation output plots after all iterations are complete. Characterize yourgate cells by submitting the completed table based on the final simulation-based values.

TG_MUX Table

* Worst among each of the paths specified

XOR gate 1. Initial Design. The function of the XOR is:

OUT = A B + A B =

A low cost implementation of a XOR can be implemented by use of two inverters and aTG_MUX. The first inverter generates B. On the TG_MUX, A is attached to S, B isattached to D1 and B is attached to D0. The second inverter buffers the output. The worstcase delay from any of the inputs to the output has a target of tp = 1.0 ns. You are toattempt to reach this value by sizing the two devices in the transmission gates and by siz-

PARAMETERSPECIFI-CATION TG_MUX

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

NML None

NMH None

Vth None

(tPHL + tPLH)/2* ≤ 0.70 ns


AB AB+



ing the input inverter generating B. The output inverter must not be changed from theinverter design since it is to be able to drive the full specified LOAD.




For the XOR, the value in parentheses for the inputs is estimated as 2 for both A and B.The LOAD subcircuit is the same as used for the inverter.

3. Cell Layout and Extraction. a) Lay out your XOR using ic. The cell must be able toabut edges with every cell type designed without design rule violations.


4. HSPICE Simulation. a) Use HSPICE to verify the dynamic parameter specificationsgiven for the XOR. The following delay measurements should be made: 1) change in A inboth directions with B = 1 and B = 0, 2) change in B in both directions with A = 1 and A =0, From these, the worst case value of tp can be derived.

5. Design iteration. If a cell does not meet specifications, if possible, modify, extract, andsimulate the layout until it does. If delays are better than the delay specification, then mod-ify the cell to minimize the bounding box area (reduce the cell width without moving theVDD and GND rails) and power consumption while just meeting the delay specifications.


Vin

Cint

Cint


XOR

Place DRIVE on this too!GAIN x IA

IA

(FO – 1) x IB

IB

Cint

LOADDRIVE


A OB



7. Submissions. For each of the two gate designs, submit the final layout, the netlist, theworst case dynamic simulation plots after all iterations are complete. Characterize yourcell by submitting the completed table based on the final simulation-based values.

XOR Table


4-bit Static Manchester Carry Chain(SMCC)

It is suggested that the core of the SMCC unit consist of a series of transmission gate mul-tiplexers, TG_MUX’s, controlled by the propagate function inputs Pi,which implement Ci,i = 1, ..., 4. Inverters are placed internally on the carry input and on the carry outputs toprovide the inversions needed and adequate drive.

The worst case delay of the SMCC is evaluated from four delay pairs: 1) from Cin to C4with P0 = 1, 2) from G0 to C4 with P0 = 0, and 3) from P0 to C4 with Cin = 1 and G0 = 1and 4) from P0 to C4 with Cin = 0 and G0 = 0. For all of these cases P1, P2, and P3 areequal to 1.

The value tp for cases 1 and 2 is to be at most 1.5 ns. The value of tp for cases 3 and 4 is to

be at most 2.0 ns.

1. Initial Design. Use the TG_MUX and NOT layouts to initially size the devices in theSMCC for a pre-layout simulation (optional). Since this is a very specific use part, it needsFO equal to only 3 IE. Thus, all of the devices should be downsized as much as possible tominimize power and area while meeting the delay specifications. A possible approach is to“sweep” the devices widths for the pre-layout simulation.

PARAMETERSPECIFI-CATION XOR

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

NML None

NMH None

Vth None





2. Simulation Environment. Each input of the SMCC is to be driven by a DRIVER sub-circuit.



For the SMCC, the value in parentheses for the inputs is estimated as 2 for all Pi, 1 for Cin, and 1.5 for all Gi. The LOAD subcircuit is the same as used for the inverter, except that FO = 3 instead of 20.

3. Cell Layout and Extraction. a) Lay out your SMCC using ic. The cell must be able toabut edges with every cell type designed so far without design rule violations.

b) For your cell, extract an HSPICE netlist and carefully edit the HSPICE file checking allconnections, eliminating incorrect or contradictory specifications. Note that interchange ofsource and drain on devices in extracted files is not a problem. Add the simulation envi-ronment being sure to adjust FO in LOAD to 3.

4. HSPICE Simulation. a) Use HSPICE to verify the dynamic parameter specificationsgiven for the SMCC. The delay measurements to be done are spelled out above. Fromthese, the worst case values of tp from Cin and G0i and of tp from P0i, both to C4, can be

derived.

5. Design iteration. If a cell does not meet specifications, modify, extract, and simulatethe layout until it does. If delays are better than the delay specification, then modify thecell to minimize the bounding box area (reduce the cell width without moving the VDDand GND rails) and power consumption while just meeting the delay specifications.


7. Submissions. For the cell design, submit the final layout, the netlist, and the worstcase dynamic simulation output plots after all iterations are complete. Characterize yourcell by submitting the completed table based on the final simulation-based values.



SMCC Table

A Worst case for Cin and G0 to C4B Worst case for P0 to C4

D Flip-flop 1. Initial Design. The symbol for the D Flip-flop appear below. Note that there is a singleoutput Q and no Q.

The D flip-flop should be implemented in a way that reduces area, but must be a staticimplementation. The target delay tp for the flip-flop from the clock positive edge to the Qoutput is at most 1.5 ns (if possible). The target delay tPHL_R for reset using R is 1.0 ns (ifpossible). The output must be driven by an inverter or a gate that has the same propertiesas the original inverter. The implementation may use a variety of techniques, e. g., TGMUXs and inverters and gates, or complex gates, and internal devices can be downsized tominimize area and power while just meeting the delay specifications. However, the outputgate must provide full drive to the standard LOAD.

PARAMETERSPECIFI-CATION CMCC

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area Minimum

VOH ≥ 3.3 V

VOL ≤ 0.0 V

Vth None

NMH None

NML None

(tPHL+tPLH)/2 See A ≤ 1.5 ns

(tPHL+tPLH)/2 See B ≤ 2.5 ns


D Q

RC



It is recommended that a pre-layout HSPICE simulation be done using the normal devicedimensions for the layouts for subcomponents previously derived or newly derived com-plex gates using the “n-times” method for complex gates based on the original inverter.Then downsizing of devices can be done using HSPICE prior to layout, possibly exploringthe use of a sweep of widths.


Since the input load that D presents may be greater than one inverter equivalent (IE), thecurrent into the gate cannot be simply multiplied by using a current generator to groundwith a gain of FO – 1. The DRIVE subcircuit shown above gives the proper value of FO onthe inputs to the gate. The fanout load on an input inverter consist of the actual load pre-sented by a gate input, the load of a single inverter and a load provided by a current gener-ator that is large enough to give a total of FO inverter loads. To produce your value of FOwith the circuit, the gain of the current generator should be:


For the D flip-flop, the value in parentheses for the input D will lie across some range depending on the implementation. You will need to determine the value.

Note that in simulation, you will need to apply R = 0 at t = 0 to initialize the flip-flop or use a .IC statement.

3. Cell Layout and Extraction. a) Lay out your D flip-flop using ic. The cell must beable to abut edges with every cell type designed so far without design rule violations.


4. HSPICE Simulation. a) Use HSPICE to verify the dynamic parameter specificationsgiven for the DFF. The following delay measurements should be made: 1) change in Q inboth directions with the clock toggled, 2) change in Q to 0 by using R. From these, theworst case value of tp and tPHL_R can be derived.

5. Design iteration. If a cell does not meet specifications, if possible, modify, extract, andsimulate the layout until it does. If delays are better than the delay specification, then mod-

Vin

Cint

Cint


GAIN x IA

IA

(FO – 1) x IB

IB

Cint

LOADDRIVE


D Q

RCDrive directly with voltage generator with

0.25 ns rise and fall times.



ify the cell to minimize the bounding box area (reduce the cell width without moving theVDD and GND rails) and power consumption while just meeting the delay specifications.


7. Submissions. For the DFF cell design, submit the final layout, the netlist, the worstcase dynamic simulation output plots after all iterations are complete. Characterize yourcell by submitting the completed table based on the final simulation-based values.

D Flip-Flop Table

A From Clock input to Q outputB From Reset input to Q output


Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≥ 3.3 V

VOL ≤ 0.0 V

Vth None

NMH None

NML None

(tPHL + tPLH)/2

See A

≤ 1.5 ns

tPHL_R See B ≤ 1.0 ns



SUBMISSION AND GRADING

Team Contributions Summarize the contributions of each team member to each of the three project phases inthe table given on the last page of this writeup. In two columns, give the name and the per-centage contribution of each team member in performing each task. If there are other tasksthat you believe were important, add them in the Other section of the table. Give on theOVERALL line an estimate of the overall contribution of each team member. This infor-mation will be ignored unless highly imbalanced, in which case, team members will begiven different scores.


Be sure to submit all of the items requested including all of the following tables. Charac-terize your gates by completing all entries in the table and flag clearly all values that doNOT meet specifications. Your project will be graded based on completeness, correctnessand the meeting of the specifications plus the minimization of area and power. This phaseis worth 150 points.



2-input NAND TABLE


3-input NAND gate table



2-inputNAND

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

Vth 1.65 ± 0.60 V

NMH ≥ 0.8V

NML ≥ 0.8V




3-inputNAND

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

Vth 1.65 ± 0.60 V

NMH ≥ 0.8V

NML ≥ 0.8V





TG_MUX Table


XOR Table


PARAMETERSPECIFI-CATION TG_MUX

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

NML None

NMH None

Vth None

(tPHL + tPLH)/2* ≤ 0.70 ns



Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≈ 3.3 V

VOL ≈ 0.0 V

NML None

NMH None

Vth None





SMCC Table

A Worst case for Cin and G0 to C4B Worst case for P0 to C4

D Flip-Flop Table

A From Clock input to Q outputB From Reset input to Q output

PARAMETERSPECIFI-CATION CMCC

Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area Minimum

VOH ≥ 3.3 V

VOL ≤ 0.0 V

Vth None

NMH None

NML None

(tPHL+tPLH)/2 See A ≤ 1.5 ns

(tPHL+tPLH)/2 See B ≤ 2.5 ns



Ln ≥ 0.4 µ

Wn ≥ 0.6 µ

Lp ≥ 0.4µ

Wp ≥ 0.6 µ

Bounding Box Area

Minimum

VOH ≥ 3.3 V

VOL ≤ 0.0 V

Vth None

NMH None

NML None

(tPHL + tPLH)/2

See A

≤ 1.5 ns

tPHL See B ≤ 1.0 ns




TEAM EFFORT TABLE

Project TaskEffort % Name 1:___________________

Effort % Name 2:___________________

Effort % Name 3:___________________

Effort % Name 4:_______________

2-input NAND design

Layout

Simulation

Iteration

Result Preparation

3-input NAND design

Layout

Simulation

Iteration

Result Preparation

TG MUX design

Layout

Simulation

Iteration

Result Preparation

XOR design

Layout

Simulation

Iteration

Result Preparation

SMCC Design

Layout

Simulation

Iteration

Result Preparation

DFF Design

Layout

Simulation

Iteration

Result Preparation

OVERALL:


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