ece 4510/5530 microcontroller applications …bazuinb/ece4510/midtermreview.pdfece 4510/5530...
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ECE 4510/5530Microcontroller Applications
Midterm Review
Dr. Bradley J. BazuinAssociate Professor
Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences
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ECE 2510 2
Exam Composition
• HC12 Parallel Pin use for external components– Hardware design for: LED Bar, Dip switch, Keypad, 5x7 Display,
electro-mechanical relay, push-button interrupt
• HC12 Peripheral Components– Clock and Reset Generator (CRG), Enhanced Timer/Counter
(ECT), Pulse Width Modulator (PWM), Serial Communication Interface (SCI)
• Software– Software time delay– Code to generate parallel outputs in time– Peripheral initialization– Peripheral interrupts– Main programs to perform various operations
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Important Peripherals
3ECE 4510/5530
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Time Delay
• Software Approaches– Delay Loop– Software Delay Subroutine
• Hardware/Peripheral Based Approaches– Real-time interrupt (RTI) hardware in the CRG– Modulus Down Counter in the ECT– Output Compare Timer in the ECT
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ECE 2510 5
Program Execution Time
• Example: find delay created if E = 41.67ns = 1/24 MHz.ldx #$1234 ; 2E
Loop1:ldy #$ABCD ; 2E
Loop2: dbne Y, Loop2 ; 3E taken/3E notdbne X, Loop1 ; 3E taken/3E not
• Total time – Inner loop: (2 + Yreg-1)*3 + 3) E Cycles – IL approx. ≈ (Yreg*3)*41.67ns ≈ 43981*3/24 MHz
≈ 0.005497625 sec– Outer loop: (2+Xreg*IL+(Xreg-1)*3 +3) * 41.67ns– Total Exact = (Xreg*Yreg*3+Xreg*(3+2)+2) * 41.67ns– Total Approx.≈ (4660*(43981)*3) /24 MHz ≈ 25.629515 sec
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EXTERNAL HARDWARE
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MC7805CTG Linear Regulator
5V Positive Voltage Regulator• Output Current in Excess of 1.0 A• No External Components Required• Internal Thermal Overload Protection• Internal Short Circuit Current Limiting• Output Transistor Safe−Area
Compensation• Output Voltage Offered in 1.5%, 2% and
4% Tolerance• Available in Surface Mount D2PAK−3,
DPAK−3 and Standard 3−Lead Transistor Packages
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Data Sheet: MC7805CTG, ON Semiconductor
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ECE 2510 8
Lab LED and Light Bar Connections
• Buffer the HC12 port (!!!)– Inverting buffer ‘540– Non-inverting buffer ‘541– Provide current sinking for the
LED
• Resistor between +5 and LED– The resistor provides current
limiting
• Resistor Value– LED needs ~1.2 to 1.5 V drop– LED wants ~ 10 mA or more
30010
8.02.15mA
VVVR OL
I ~ from 8 to 12 mA
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ECE 2510 9
Lab Dip Switch Connections
• Buffer the HC12 port (!!!)– Inverting buffer ‘540– Non-inverting buffer ‘541– Provide isolation from switch
• Resistor between +5 and switch– If you short the switch while
probing, the resistor provides current limiting.
• Resistor Value– 330 ohms or greater
(10 kohm preferred)
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Class Keypads
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Driving a 5 x 7 LED Array
Lighting One LED• Source current to a row• Selectively sink current
from a column
Matrix Driving• Separately source all rows
where LEDs are to turn on in Column 1 AND sink current from only column 1.
• Do the next column … and repeat.ECE
4510/553011Lite-On Technology Corp. LTP-757G
20 mA, 2.1-2.6V80 mA, 3.0-3.7V
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Driving a 5 x 7 LED Array
• Source MIC5891• 5 x 7 LED Array• Sink ULN2803a• Sink Column Select
74HCT595 (not shown)
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Operating the MIC5891YN
A. Minimum data active time before clock pulse (data set-up time) 75nsB. Minimum data active time after clock pulse (data hold time) 75nsC. Minimum data pulse width .150nsD. Minimum clock pulse width 150nsE. Minimum time between clock activation and strobe 300nsF. Minimum strobe pulse width 100nsG. Typical time between strobe activation and output transition 1.0μs
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Lab 4 Relay Design
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Parts Kit RS-232 Transceiver ICMAX232IN• Meets or Exceeds TIA/EIA-232-F
and ITU• Recommendation V.28• Operates From a Single 5-V Power
Supply With 1.0-uF Charge-Pump Capacitors
• Operates Up To 120 kbit/s• Two Drivers and Two Receivers• ±30-V Input Levels• Low Supply Current . . . 8 mA
Typical• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
• Upgrade With Improved ESD (15-kV HBM) and 0.1-uF Charge-Pump Capacitors is
• Available With the MAX202• Applications
– TIA/EIA-232-F, Battery-Powered Systems,– Terminals, Modems, and Computers
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ECE 4510/5530
PS1/TxD
PS0/RxD
Note: Both CTS and RTS arejumpered to an I/O pin in casehardware handshake is needed
CTS*
RTS*
T1IN
T2IN
R1OUT
R2OUT
T1OUT
T2OUT
R1IN
R2IN
11
10
12
9
8
13
7
14
1
6
2
7
3
8
4
9
5
DCD
DSR
RxD
RTS
TxD
CTS
DTR
RI
GND
DB9 connector
DS14C232
Figure 9.19 Diagram of SCI and EIA232 DB9 connector wiring in SSE256 demo board
Interfacing with the Transceiver
• Interfacing the HCS12 SCI0 to the EIA-232 using the DS14C232 chip and implements the NULL modem connection so that this connection can talk to a PC directly.
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INTERNAL PERIPHERALS
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ECE 2510 18
VREG
Clock and ResetControl
Resetgenerator
Clock qualitychecker
COP RTI
Registers
SystemReset
Bus clock
Core clock
Oscillatorclock
Power onreset
RESETCM fail
Clockmonitor
OSC
PLL
OSCCLK
PLLCLK
XCLKS
EXTAL
XTAL
XFCVDDPLL
VSSPLL
CRG
Figure 6.4 Block diagram of CRG
Clock and Reset Generation Block (CRG)
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ECE 2510 19
Phaselockloop
1
0
1
0
Clockmonitor
Oscillator OSCCLK
PLLCLK
PLLSEL or SCM
SCM
clockphase
generator2
WAIT,STOP
wait(RTIWAI),stop(PSTP,PRE)
RTI enable
RTI
COP
wait (COPWAI),stop(PSTP, PCE)
COP enable
wait (SYSWAI),stop
stop (PSTP)
wait (CWAI,SYSWAI)stop
Coreclock
Busclock
oscillatorclock
oscillatorclock (pseudo stopmode)
extal
xtal
gatingcondition
= clock gate
Figure 6.15 HCS12 clock generation circuit
SYSCLK
Choice of Clock Source
E-Clock
Real Time Interrupt
Comp. Operating Properly
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ECE 2510 20
RTI Counter Chain
CRG Block User Guide V02.07, Doc. Number S12CRGV2/D
102112122132142152162
161 to
Note: OSCCLK not SYSCLK and not E-Clock
Key Registers:
• RTICTL
• CRGINT
• CRGFLG
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Enhanced Timer-Counter (ECT)
Key Registers:• TCNT• TSCR1• TSCR2• TIOS• TIE• TFLG1• TFLG2• TCTL1/2• TCTL3/4• TCx, x=0:7• MCCTL• MCCNT• MCFLG
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ECT Block Diagram (Queue Mode)
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Prescaler 16-bit free-runningmain timer
pin logic Delaycounter
comparator
TCx capture/compareregister
TCxH hold register
EDG x
Prescalerbus clock÷1, 4, 8, 16
÷1,2,...,128 16-bit load register
16-bit modulusdown counter
Figure 8.36 Enhanced Input capture function block diagram in Queue mode (channels IC0..IC3 block diagram)
to other IC channels
bus clock
PTxone IC channel
(IC0..IC3)
pin logicPTicomparator
TCx capture/compareregisterMUX
EDG i
EDG jj = 8 - i
one IC channel(IC4..IC7)
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Channel 7
Period and duty Counter
PWM Channels
Channel 6
Period and duty Counter
Channel 5
Period and duty Counter
Channel 4
Period and duty Counter
Channel 3
Period and duty Counter
Channel 2
Period and duty Counter
Channel 1
Period and duty Counter
Channel 0
Period and duty Counter
Clock select
Control
PWMclock
PWM Module
Enable
Polarity
Alignment
Bus clock
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Figure 8.38 HCS12 PWM block diagram
PWM Block Diagram
Key Registers:• PWMPRCLK• PWMSCLA• PWMSCLB• PWMCLK• PWME• PWMCNTx• PWMDTYx• PWMPERx• PWMPOL• PWMCAE• PWMCTL
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GATE8-bit counter
PWMCNTx
8-bit compare=
PWMDTYx
clocksource
8-bit compare=
PWMPERx
T Q
QR
MUX
T
R
CAExQ
Q
MUX
to pindriver
PPOLx
From port PTPdata register(clock edge sync)
PWMEx
up/down re
set
Figure 8.44 PWM channel block diagram
PWM Channel Block Diagram
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SCI data register
Receive shift register
Receive and wake up control
BAU
Dge
nera
tor
16 Data format control
Transmit control
Transmit shift register
SCI data register
Busclock
RxDInterrupt
generation
Interruptgeneration
IdleIRQ
RDRF/ORIRQ
TDREIRQ
TCIRQ
ORI
NG
IRQto CPU
TxD
Figure 9.8 HCS12 SCI block diagram
Status Register 1
Status Register 2
The HCS12 SCI Subsystem
Key Registers:• SCIxDRL• SCIxBD• SCIxCR1• SCIxCR2• SCIxSR1• SCIxSR2
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The EIA-232E Electrical Specifications
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Additional Software
• User inputs from and outputs to a PC terminal window• User inputs from a keypad and outputs to an LED matrix
display• Using text line buffers (sscanf and sprintf)• Time and calendar operations, with an alarm• Computing periodicity and duty cycle• Generating output waveforms (period and duty cycle)• Collecting and buffering results• IIR filter operation• Operating States and modes within the states
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