ece 448: spring 13 lab 3 sequential logic for synthesis simulation using modelsim
DESCRIPTION
ECE 448: Spring 13 Lab 3 Sequential Logic for Synthesis Simulation using ModelSim. Agenda for today. Part 1: Introduction to Lab 3 Top-level circuit LFSR MISR Debouncer Edge Detector Part 2: Hands-on Session: Simulation Using ModelSim Part 3: Demos of Lab 2. Part 1. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: ECE 448: Spring 13 Lab 3 Sequential Logic for Synthesis Simulation using ModelSim](https://reader036.vdocuments.site/reader036/viewer/2022062814/5681684b550346895dde3ed3/html5/thumbnails/1.jpg)
ECE 448: Spring 13Lab 3
Sequential Logic for Synthesis
Simulation using ModelSim
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Part 1: Introduction to Lab 3• Top-level circuit• LFSR• MISR• Debouncer• Edge Detector
Part 2: Hands-on Session: Simulation Using ModelSimPart 3: Demos of Lab 2
Agenda for today
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ECE 448 – FPGA and ASIC Design with VHDL
Part 1
Introduction to Lab 3
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Top-Level Circuit
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rstclkenCNTR
UP
rstclken
MISR
ldrst clk
enLFSR
X”00” 8
8
8
IVBloadB
rstOR
loadB
nexti
10cnz
ldrst clk
enLFSR
X”00” 8
8
8
IVAloadA
rstOR
loadA
10cnz
clkclk
LAB2
A B
X Y
sel
En ‘0’
8
clkrst
8
YSGN
nexti
nextrst
clken
MISR
8
clkrst
8
XSGN
next
10k
k9..8
2k7..0
8
≠ 0
cnz
= X”3FF”10
done
rstclk
next
OR
AND not donenext
step run
AND
cnz
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Used to enterIVA, IVB
Used to generateloadA, loadB,
step, run
Used to displayXSGN, YSGN
Source of Inputs & Display of Outputs (to be experimentally tested in Lab 4)
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Connection of Buttons to the Pins of FPGA
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RED = Rising Edge Detector
RESET
BTNL
BTNR
BTNU
BTNS
Debouncer RED loadA
Debouncer RED loadB
Debouncer RED step
rst
Debouncer RED
runD Q‘1’en
rst
clk
rst
clkrst
clk
rst
clkrst
clk
rst
clk
rst
clk
rst
clk
rst
clk
Generation of Inputs Using Buttons
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Pseudo-Random Number GeneratorsImplemented Using LFSRs
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PRNG• Generates a sequence of numbers that
approximates the properties of random numbers.
• The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG.• The period of the sequence may be made very
large (typically, 2n-1, where n is an internal state size)
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PRNG
• Random Numbers are often important– Testing of VLSI circuits– Cryptography– Monte Carlo simulations– Noise addition– Bit error detection, and many other applications
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Linear Feedback Shift Register (LFSR)
L, C(D)
Connection polynomial, C(D)
C(D) = 1 + c1D + c2D2 + . . . + cLDL
Length
Each stage = D flip-flop
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Initial state[sL-1, sL-2, . . . , s1, s0]
LSFR recursion:
sj = c1sj-1 c2sj-2 . . . cL-1sj-(L-1) cLsj-L
for j L
Sj-1 Sj-2 Sj-(L-1) Sj-L
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4, 1+D+D4
Connection polynomial, C(D)Length
Example of LFSR
c1=1 c2=0 c3=0 c4=1
C(D) = 1 + 1D + 0D2 + 0D3 + 1D4
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LFSR State Sequence
s4 = c1s3 c2s2 c3s1 c4s0 = s3 s0
s4 s3 s2 s1 s0
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8, 1+D4+D5+D6+D8
Connection polynomial, C(D)Length
LFSR to be used in Lab 3
Selected to make a period = 28-1 = 255
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Initializing Serial Shift Register with Parallel Load
D(3)
D Q
Clock
Enable
SinD(2)
D Q
D(1)
D Q
D(0)
D Q
Q(0)Q(1)Q(2)Q(3)
Load
Hint: Use similar technique for initializing LFSR
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Multiple Input Signature RegisterMISR
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AND
D Q
C7
en
rst
rst
en
D7
AND
D Q
C6
en
rst
rst
en
D6
AND
D Q
C5
en
rst
rst
en
D5
AND
D Q
C4
en
rst
rst
en
D4
AND
D Q
C3
en
rst
rst
en
D3
AND
D Q
C2
en
rst
rst
en
D2
AND
D Q
C1
en
rst
rst
en
D1
AND
D Q
C0
en
rst
rst
en
D0
MISR - Multiple Input Signature Register
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
C=C7..C0 should be declared as a generic in VHDL code
For the purpose of testing set C=X”B8”
MISR is used to compress multiple inputs D to a single signature Q
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Debouncer
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Debouncer
Capacitance in the button and contacts “bouncing” causes spurs that cause false positives.
A debouncing circuit removes these spurs.This graphs shows releasing a button.
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Debouncer
When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually in the order of ms.
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Debouncer
Debouncer
reset
input
clk
output
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Debouncer
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Rising Edge DetectorRED
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Rising Edge Detector - RED
• Turn a step function into an impulse• Allows a step to run a circuit for only one clock
cycle
Rising Edge Detector
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Rising Edge Detector
clk
input
output
input
clk
output
rising edge detector
reset
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ECE 448 – FPGA and ASIC Design with VHDL
Part 2
Hands-on SessionSimulation Using ModelSim
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Hands-on Sessionon ModelSim using
four_bit_counterbased on JK flip-flops
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ECE 448 – FPGA and ASIC Design with VHDL
Part 3Lab 2 Demos