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ECE 15B Computer OrganizationSpring 2010
Dmitri Strukov
Lecture 2: Overview of Computer Organization
Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy, and classes taught by Patterson at Berkeley, Ryan Kastner at UCSB and Mary Jane Irwin at Penn State
“Von‐Neumann” Computer
Store –programmed concept was not invented by John von Neumann onlyNeumann only
Other inventors Presper Eckert and John Mauchly ENIAC 1943Uni ersit of Pensil ania
Computer Keyboard, Mouse
University of Pensilvania
Processor
Control
Memory
(where
Devices
Input
Mouse
Disk(where programs
Datapath
programs, data live whenrunning)
Output
programs, data live whennot running)
Display, Printer
ECE 15B Spring 2010
Layers of Abstraction
A li ti ( b )
This class is aboutthis region
CompilerOperatingSystem(Mac OSX)
Application (ex: browser)
f
this region
I/O systemProcessor
(Mac OSX)
Instruction SetArchitectureMemoryHardware
Software Assembler
Digital Design
Circuit Design
Datapath & Control
transistors
Need Many Layers to Handle ComplexityECE 15B Spring 2010
Below the Programtemp = v[k];
$ ($ )
High Level Language Program (e.g., C)
Compiler
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)
Assembly Language Program (e.g.,MIPS)
Compiler
AssemblerMachine Language
Program (MIPS)
Assembler
Machine
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
Hardware Architecture Description (e.g., block diagrams)
Machine Interpretation
0101 1000 0000 1001 1100 0110 1010 1111
g )
Architecture Implementation
Logic Circuit Description(Circuit Schematic Diagrams)
Review: Unsigned Binary Representation
Hex Binary Decimal0x00000000 0…0000 00x00000001 0…0001 1 231 230 229 . . . 23 22 21 20 bit weight
0x00000002 0…0010 20x00000003 0…0011 30x00000004 0…0100 4 1 1 1 . . . 1 1 1 1 bit
31 30 29 . . . 3 2 1 0 bit position
g
0x00000004 0…0100 40x00000005 0…0101 50x00000006 0…0110 60x00000007 0 0111 7
1 0 0 0 . . . 0 0 0 0 ‐ 10x00000007 0…0111 70x00000008 0…1000 80x00000009 0…1001 9
232 ‐ 1…0xFFFFFFFC 1…11000xFFFFFFFD 1…11010 FFFFFFFE 1 1110 32
232 ‐ 3232 ‐ 4
0xFFFFFFFE 1…11100xFFFFFFFF 1…1111 232 ‐ 1
232 ‐ 2
ECE 15B Spring 2010
Data input: Analog Digital
• Real world is analog!• To import analogTo import analog information, we must do two things– Sample
• E.g., for a CD, every 44,100ths of a second, we ask a music signal how loud it is.
– Quantize• For every one of these samples, we figure out where, on a 16‐bit (65,536 tic‐mark) “yardstick” ittic‐mark) yardstick , it lies.
www.joshuadysart.com/journal/archives/digital_sampling.gifECE 15B Spring 2010
Logic Design BasicsLogic Design Basics
• Information encoded in binaryInformation encoded in binary– Low voltage = 0, High voltage = 1
One wire per bit– One wire per bit
– Multi‐bit data encoded on multi‐wire buses
ECE 15B Spring 2010
Why binary?Why binary?
O h l i l ll fOther logic styles allow for implementations of multilevel logic (e.g. threshold logic)
CMOS digital design style, which is the most power efficient and thereforemost power efficient and therefore currently dominating, enforces binary signal representationsignal representation
ECE 15B Spring 2010
How to build combinational elements?
• AND‐gate AY+
Adder– Y = A & B
AY
B
Y+ Y = A + B
BY
Multiplexer Arithmetic/Logic Unit
Multiplexer Y = S ? I1 : I0
A
Y = F(A, B)
I0I1
YMux B
YALU
S F
ECE 15B Spring 2010
Combinational logicCombinational logic
• Complex logic blocks are built from basic ANDComplex logic blocks are built from basic AND, OR, NOT building blocks we will see shortly
• A combinational logic block is one in which• A combinational logic block is one in which the output us a function only of its current inputinput
• Combination logic cannot have memory
ECE 15B Spring 2010
Sequential Elements• Flip flop: stores data in a circuit
Uses a clock signal to determine when to update– Uses a clock signal to determine when to update the stored value
– Edge‐triggered: update when Clk changes from 0Edge‐triggered: update when Clk changes from 0 to 1
D QClk
D
Clk
D
Q
ECE 15B Spring 2010
Sequential Elements
• Flip flop with write control– Only updates on clock edge when write control input is 1
– Used when stored value is required later
Clk
D Q Write
Clk
ClkWrite D
Q
ECE 15B Spring 2010
Clock + sequential logic = synchronous design
• Clock rate (clock cycles per second in MHz or GH ) i i f l k l ti ( l k i d)
design
GHz) is inverse of clock cycle time (clock period)CC = 1 / CR
one clock period
10 nsec clock cycle => 100 MHz clock rate10 nsec clock cycle 100 MHz clock rate
5 nsec clock cycle => 200 MHz clock rate
2 nsec clock cycle => 500 MHz clock rate
1 nsec (10‐9) clock cycle => 1 GHz (109) clock rate
500 psec clock cycle => 2 GHz clock rate
250 psec clock cycle > 4 GHz clock rate250 psec clock cycle => 4 GHz clock rate
200 psec clock cycle => 5 GHz clock rateECE 15B Spring 2010
Clocking Methodology• Combinational logic transforms data during clock cyclesy– Between clock edges– Input from state elements, output to state p , pelement
– Longest delay determines clock period
ECE 15B Spring 2010