ECAD & VLSI LABMANUAL FOR B.TECH ECE IV-1 SEMESTERBYSATHISH DADI M.TECH

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD IV Year B.Tech. ECE - I Sem L T/P/D C 0 -/3/- 2 E-CAD AND VLSI LAB

List of Experiments

Design and implementation of the following CMOS digital/analog circuits using Cadence / Mentor Graphics / Synopsys / Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools.

1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with parity) 4. Design of 8-to-1 multiplexer 5. Design of 4 bit binary to gray converter 6. Design of Multiplexer/ Demultiplexer,comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design

VLSI programs: 1. Introduction to layout design rules 2. Layout, physical verification, placement & route for complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following: Basic logic gates CMOS inverter CMOS NOR/ NAND gates CMOS XOR and MUX gates CMOS 1-bit full adder Static / Dynamic logic circuit (register cell) Latch Pass transistor 3. Layout of any combinational circuit (complex CMOS logic gate)- Learning about data paths 4. Introduction to SPICE simulation and coding of NMOS/CMOS circuit 5. SPICE simulation of basic analog circuits: Inverter / Differential amplifier 6. Analog Circuit simulation (AC analysis) CS & CD amplifier 7. System level design using PLL

Note: Any SIX of the above experiments from each part are to be conducted (Total 12)

EXPERIMENT -1Simulation using all the modeling styles and Synthesis of all the logic gates usingVerilog HDL---------------------------------------------------------------------------------------------------------------------Aim:Perform Zero Delay Simulation of all the logic gates written in behavioral, dataflow and structural modeling style in Verilog using a Test bench. Synthesize each one of them on two different EDA tools.Apparatus required:Electronics Design Automation Tools used:Xilinx Spartan 3E FPGA +CPLD Board Model Sim simulation tool or Xilinx ISE Simulator toolXilinx XST Synthesis tool or LeonardoSpectrum Synthesis Tool Xilinx Project Navigator 13.2 (Includes all the steps in the design flow fromSimulation to Implementation to download onto FPGA).JTAG cableAdator 5v/4A

Boolean equations:And Gate:Y = (A.B)Or Gate: Y = (A + B)Nand Gate: Y = (A.B) Nor Gate: Y = (A+B)Xor Gate: Y = A.B + A.BXnor Gate: Y = A.B + A.B

Block diagram:

Verilog program for AND gate:// And Gate (In Dataflow, behavioral Modeling):Module andg(a,b,c);input a,b;output c;assign c = a & b;endmodule

//behavioural modeling

Module andg1(a,b,c);input a,b;always(a,b)begin if (a==1b0 or b == 1b0)c = 1b0;else if (a==1b0 or b == 1b1)c = 1b0;else if (a==1b1 or b == 1b0)c = 1b0;else if (a==1b1 or b == 1b1)c = 1b1;endendmodule

Verilog program for OR gate:

//Or gate(Dataflow, behavioral modeling):Module org (a,b,c);input a,b;output c;assign c = a | b;endmodule

Verilog program for nand gate:// Nand Gate (In Dataflow modeling):Module nandg (a,b,c);input a,b;output c;assign c = ~(a & b);endmodule

Verilog program for NOR gate:// Nor Gate (In Dataflow modeling):Module norg (a,b,c);input a,b;output c;assign c = ~(a | b);endmodule

Verilog program for XOR gate:Xor gate(In Dataflow modeling):Module xorg (a,b,c);input a,b;output c;assign c = a ^ b;endmodule (or)Module xorg2 (a,b,c);input a,b;output c;assign c = (~a & b) | (a & ~b);endmodule

Verilog program for XNOR gate://Xnor Gate (In Dataflow modeling):Module xnorg (a,b,c);input a,b;output c;assign c = ~(a ^ b);endmodule

VHDL PROGRAM FOR ALL LOGIC GATES:library ieee;use ieee.std_logic_1164.all;entity digital_gates is port(x: in std_logic;y: in std_logic;sel:in std_logic_vector(1 downto 0);F: out std_logic);end digital_gates; architecture behav1 of digital_gates isbegin process(x, y, sel) begin if (sel = "00") then F [0|1|...|n-1] -> sOut begin sOut Help Topics.

To configure the device:

1. Click the "+" sign to expand the Generate Programming File processes.2. Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure Devices dialog box is displayed. 3. In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and click Next.4. Verify that Automatically connect to cable and identify Boundary-Scan chain is selected and clickFinish.5. If you get a message saying that there was one device found, click OK to continue.6. The iMPACT will now show the detected device, right click the device and select New Configuration File.7. The Assign New Configuration File dialog box appears. Assign a configuration file to each device in the JTAG chain. Select theandgate.jedfile and click Open.8. Right-click on the counter device image, and select Program... to open the Program Options dialog box.9. Click OK to program the device. ISE programs the device and displays Programming Succeeded if the operation was successful.10. Close iMPACT without saving.

VHDL CODE FOR FULL AADDER DATAA FLOW: Full Adder A B C Ci S Co 0 0 0 0 0 EXXPRESSIONS:0 0 1 1 0 0 1 0 1 0 B CiS == A 0 1 1 0 1 B)Ci + ABCOO = (A 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Libraary IEEE; use IEEE.STD_LOOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fa1 is Port ( a,b,ci : in STD_LOGIC; s,,co : out STD_LOGIC); end fa1; architecture Behavioral of fa1 is begin sstatestatestatestatenull; begin end case process(clk,rst) end if; begin end if; if (rst='0') then end process; div'0'); with state select elsif(clk'event and clk='1') then out_stm