early output logic and anti-tokens
DESCRIPTION
Early output logic and Anti-Tokens. Charlie Brej APT Group Manchester University. Overview. Synchronous Problems Asynchronous Logic Why? How? Solutions Early Output Anti-Tokens. Problems: Communication. Communication horizon - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/1.jpg)
1 2004 MAPLD: 153Brej
Early output logic and Anti-Tokens
Charlie Brej
APT Group
Manchester University
![Page 2: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/2.jpg)
2 2004 MAPLD: 153Brej
Overview
Synchronous ProblemsAsynchronous Logic
Why?How?
SolutionsEarly OutputAnti-Tokens
![Page 3: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/3.jpg)
3 2004 MAPLD: 153Brej
Problems: Communication
Communication horizon“For a 60 nanometer
process a signal can reach only 5% of the die’s length in a clock cycle” [D. Matzke,1997]
Clock distributed using wave pipelining
![Page 4: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/4.jpg)
4 2004 MAPLD: 153Brej
Problems: Performance
Cycletime
Unbalanced Stages
Clock Skew/Jitter
Transistor Variability
Signal Integrity
Worst – Averagecase performance
Real Computation
Clockoverheads
TimingAssumptionoverheads
![Page 5: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/5.jpg)
5 2004 MAPLD: 153Brej
Clock! What is it good for?
No arguing with the clock9am - 5pm. No excuses!
![Page 6: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/6.jpg)
6 2004 MAPLD: 153Brej
Bundled-Data
When you finish, do the next taskFlexitime
Request + Delay
Acknowledge
![Page 7: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/7.jpg)
7 2004 MAPLD: 153Brej
How do you know when you are finished?
Synchronous:EstimateGlobal timing reference
Asynchronous (bundled-data)EstimateLocal delay elements
Asynchronous (delay-insensitive)When the data arrivesIntrinsic
![Page 8: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/8.jpg)
8 2004 MAPLD: 153Brej
Becoming Delay Insensitive
Dual-RailTwo wires00 – NULL01 – Zero10 – One(11 – Not used)
Four Phase handshakeReturn to zero
R1
Ack
R0
![Page 9: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/9.jpg)
9 2004 MAPLD: 153Brej
Early Output Logic
Dual-Rail interfacesOutput generated as
early as possibleTwo Early output cases
If either input is ‘0’ then the output is ‘0’
![Page 10: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/10.jpg)
10 2004 MAPLD: 153Brej
Bit level pipelining
Forward completed parts of the resultPace workDon’t stall parts unless you have to
![Page 11: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/11.jpg)
11 2004 MAPLD: 153Brej
Bit level pipelining
Forward completed parts of the resultPace workDon’t stall parts unless you have to
![Page 12: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/12.jpg)
12 2004 MAPLD: 153Brej
Bit level pipelining
Forward completed parts of the resultPace workDon’t stall parts unless you have to
![Page 13: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/13.jpg)
13 2004 MAPLD: 153Brej
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Inputs Present
Pro
babi
lity
of O
utpu
t
Branch unitinc. Coproc.
Branch unit
CompareLT/GE 8bit
CompareEqual 8bit
Adder bit 8
Mux 8:1
Memoryshift unit
ALU Slice
16 inputAND
Early Output cases
![Page 14: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/14.jpg)
14 2004 MAPLD: 153Brej
Validity
Unnecessary late inputsMust be acknowledgedMust wait until they arrive
Validity signalLatch generatedReady to be acknowledged
Result before all inputs presentAcknowledge after all inputs present
![Page 15: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/15.jpg)
15 2004 MAPLD: 153Brej
Synchronisation Hurts
No need to wait before generating result
Need to wait for input in order to acknowledge it
Unnecessary stall
![Page 16: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/16.jpg)
16 2004 MAPLD: 153Brej
Anti-Tokens
Unnecessary late inputsStall the entire stage
Proactive approachSend a ‘cancel’ signal backward to the sourceAcknowledge before data arrives
Anti-Token latchesAssert validity early
![Page 17: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/17.jpg)
17 2004 MAPLD: 153Brej
Anti-token generation
0
1
C
![Page 18: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/18.jpg)
18 2004 MAPLD: 153Brej
Anti-token generation
0
A 1
C
![Page 19: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/19.jpg)
19 2004 MAPLD: 153Brej
Anti-token Propagation
1
C
A
![Page 20: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/20.jpg)
20 2004 MAPLD: 153Brej
Anti-token Propagation
1
C
AA
![Page 21: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/21.jpg)
21 2004 MAPLD: 153Brej
Anti-token Token collisions
1 1 A A
1 1 A A?
A?1
![Page 22: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/22.jpg)
22 2004 MAPLD: 153Brej
Anti-token Token collisions
1 1 A
1 1 A A1
A1
11
![Page 23: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/23.jpg)
23 2004 MAPLD: 153Brej
Remove Unnecessary computation
Cycletime
Unbalanced Stages
Clock Skew/Jitter
Transistor Variability
Signal Integrity
Worst – Averagecase performance
Real Computation
Clockoverheads
TimingAssumptionoverheads
Unnecessary Computation/Delays
![Page 24: Early output logic and Anti-Tokens](https://reader036.vdocuments.site/reader036/viewer/2022062500/5681520e550346895dc05091/html5/thumbnails/24.jpg)
24 2004 MAPLD: 153Brej
Summary
AsynchronousDelay Insensitive
Safe No timing assumptions
Average case performanceRemove unnecessary computationAnti-tokens without mutual exclusion units