dynamic scan

7/24/2019 Dynamic Scan

1/18

Dynamic ScanDriving Down the Cost of Test


2/18

Outline

Introduction

Current Scan Test Usage

Basis for Dynamic Scan

Dynamic Scan With Multiple Scan Chains

!perimental "esults


3/18

Introduction

The cost of semiconductor depends on twofactors

#$ The num%er of test patterns applied to each chip

&$ The time it ta'es to run each pattern typical semiconductor testing for each chip

involves a set of #())) to *())) test patterns

+ow a days the num%er of flip,flops per chipare in millions$


4/18

Introduction contd$$$

- small decrease in either the num%er ofpatterns or the time to e!ecute them canreduce cost across millions of fa%ricated chips

Dynamic scan can reduce the time spentapplying the test patterns %y a%out .) percent

Theoretical analysis shows the savings of as

much as /) percent$


5/18

Current Scan Test Usage

-T01 uses scan chain to control and o%serve the flip,flops$

Basic scan technology attempts to ma!imi2e thememory elements to %e scanned( which supports theverification of fa%rication chips

Total usage of scan chain is time consuming process

-T01 doesn3t need to scan all the memory elements

to attain the re4uired fault coverage


6/18

Current Scan Test Usage contd$$

The partial,scan techni4ue identifies a smallerset of memory elements( providing a singleconfiguration to attain re4uired fault coverage

-lthough the test must scan all memoryelements at least once to detect the faults( itneed not scan every element for every testpattern

The method of su%section creates pro%lem ofcomple!ity


7/18



8/18

5or the a%ove figure the test vectors and their

responses


9/18


We apply these test patterns in a three,step se4uence6

7 scan,in Tn ( scan,out Tn,#

7 stimulate inputs( measure outputs

7 pulse a capture cloc'$ "unning the entire test of four patterns consumes 8* 9

#: ; . 9 * < &= cycles

* cycles to scan in . test patterns and additional five

cycles to scan out the last pattern$# cycle for capturingresponse for each test pattern$


10/18


Scan chain with dynamic configuration


11/18

5lip,flops %loc'ed for a%ove configuration


12/18

Signals that control the multiple!ers let them either

%ypass or include a flip,flop in the scan chain - >,? signifies a value that was omitted from the

test pattern

T# uses scan cells c& and c@ Tests T& and T@ use scan cells c& ( c@ ( and c.

Test T. uses c) ( c# ( c& ( c@ (and c.

The total scan time for all test patterns is &9 @ 9 @9 * 9 & < #* cycles


13/18

Using Scan Segments

a practical implementation should use aminimum num%er of configurations

-n efficient implementation should order

multiple test patterns to use a singleconfiguration$ This ordering should alsoma!imi2e scan,in and scan,out overlap

Most test patterns should use short scan chainconfigurations


14/18

!ample

Aere scan chain with one configuration

The overall test time @9@9@9*9*


15/18

Dynamic Scan With Multiple ScanChains

One of the dynamic configuration with multiplescan chains


16/18

"esults

Circuits and num%er of test patterns


17/18

"esults contd$$

The results for a two,way split


18/18

TA-+ OU

dynamic scan

Documents