dynamic power noise analysis method for memory designs
DESCRIPTION
Dynamic Power Noise Analysis Method for Memory Designs. Chanseok Hwang , Changwoo Kang, Bosun Hwang Joonho Choi, Moonhyun Yoo CAE Team, Semiconductor Research Center Samsung Electronics. Outline. Memory Design Overview Memory Core Operations Our approach Memory Core Circuit Modeling - PowerPoint PPT PresentationTRANSCRIPT
Dynamic Power Noise Analysis Dynamic Power Noise Analysis Method for Memory DesignsMethod for Memory Designs
Chanseok HwangChanseok Hwang, Changwoo Kang, Bosun Hwang Joo, Changwoo Kang, Bosun Hwang Joonho Choi, Moonhyun Yoonho Choi, Moonhyun Yoo
CAE Team, Semiconductor Research Center CAE Team, Semiconductor Research Center Samsung ElectronicsSamsung Electronics
2/14
OutlineOutline
Memory Design OverviewMemory Design Overview Memory Core OperationsMemory Core Operations
Our approachOur approach Memory Core Circuit ModelingMemory Core Circuit Modeling
Power Grid Creation and ReductionPower Grid Creation and Reduction
Simulation ResultsSimulation Results
ConclusionsConclusions
3/14
Memory Design OverviewMemory Design Overview
Power noise increasingly affects circuit Power noise increasingly affects circuit robustnessrobustness Low VDD (< 1.0V), High Speed (>2GHz)Low VDD (< 1.0V), High Speed (>2GHz)
Challenges in power noise analysisChallenges in power noise analysis Modeling of huge power networkModeling of huge power network Long simulation timesLong simulation times
An Example of DRAM Fullchip Power Grid
4/14
DRAM Core OperationsDRAM Core Operations
Core AC parameters : Sensing/Restore TimeCore AC parameters : Sensing/Restore Time Highly sensitive to power noises : Voltage margin and Operation speedHighly sensitive to power noises : Voltage margin and Operation speed
VDD
VSS
Sense amplifiers with power networks Simulation waveforms of sensing operation
WLBL
BLB
VCELL
VBL=500mvVBL
LAB
VCELL = 1.125(90% VDD)
Sensing time
Restore time
LAB
LA
5/14
Our ApproachOur Approach
Current Source Model (CSM)Current Source Model (CSM) Core sub-array block is replaced by a current sourceCore sub-array block is replaced by a current source
Multi-banks operation can be simulated Multi-banks operation can be simulated
Power Network Generation & ReductionPower Network Generation & Reduction Memory core power network is generated Memory core power network is generated
automaticallyautomatically
MOR technique is adopted efficientlyMOR technique is adopted efficiently
6/14
Current Source ModelingCurrent Source Modeling
A C
B
GE
HD F
SA
SWD Conj
Hierarchical Memory Core Structure
Sub-Array BlockCore BankFullchip with 8 Banks SA
SWD Conj
Block with active WL
Block with inactive WL
Inactive blocks become decoupling caps
Active blocks become current sources
Active WL
7/14
Multiple-Bank OperationsMultiple-Bank Operations
: current sources
A C E G
B D F H
A C E G
B D F H
7ns
Activate Bank F Activate Bank H
A C E G
B D F H
A C E G
B D F H
10ns
Activate Bank B, C, F, G Activate Bank A, D, E, H
: circuits
8/14
Our ApproachOur Approach
Current Source Model (CSM)Current Source Model (CSM) Core sub-array block is replaced by a current sourceCore sub-array block is replaced by a current source
Multiple-Bank Operation ModelingMultiple-Bank Operation Modeling
Power Network Generation & ReductionPower Network Generation & Reduction Memory core power network is generated Memory core power network is generated
automatically in early design stagesautomatically in early design stages
MOR technique is adopted efficientlyMOR technique is adopted efficiently
9/14
Power Network Generation & ReductionPower Network Generation & Reduction
Power Network Generation GUI
Automatically Generated Power Network
Reduced Power Network
amp amp
amp amp amp ampamp amppad
amp amp
Coarse Grid
Coarse Grid
Fine Grid
Coarse Grid
10/14
Power Noise Verification FlowPower Noise Verification Flow
Circuit connection to power network
Circuit Simulation
Power Network Creation
A C
B
GE
HD F
+
Active Circuits Current Sources
VerificationFail
Voltage Drop Map Viewer
Simulation Waveform
11/14
Simulation ResultsSimulation Results
Example Circuit: 1G DRAMExample Circuit: 1G DRAM
Sensing & Restore Time ComparisonsSensing & Restore Time Comparisons Simulation Time and Accuracy for the Proposed Simulation Time and Accuracy for the Proposed
Power Network Model Power Network Model
Single Bank vs. Multiple Bank OperationsSingle Bank vs. Multiple Bank Operations
12/14
ResultsResults: : Analysis of different power networksAnalysis of different power networks
Original Power Network Modeling (OPN)
Proposed Power Network Modeling (CSM)
Rate(OPN/CSM)
Num. Resistor 2,316,868 493,943 4.69
Num. Capacitor 1,307,124 66,515 19.65
Run time (h) 35.3 2.3 15.35
Sensing time (ns)
1.059 1.053 1.01
Restore time (ns)
11.643 12.625 0.92
Run-Time: 15.3X reduction Accuracy Error: 1% in Sensing, 8% in Restore time
13/14
Simulation ResultsSimulation Results
0.0000.2000.4000.6000.8001.0001.2001.4001.600
Single-bankrow-active
Multi-bankRRD
4 bankrefresh
8 bankrefresh
Operation mode
Sens
ing
Tim
e (n
s)
0.000
5.000
10.000
15.000
20.000
Res
tore
Tim
e (n
s)
Sensing Time Restore Time
We could get this results by using the proposed method.
14/14
ConclusionsConclusions
Current Source-based Model is proposed for the power Current Source-based Model is proposed for the power
noise analysis of memory circuits.noise analysis of memory circuits. Based on the hierarchical memory core array structureBased on the hierarchical memory core array structure
The method of automatic generation and reduction of The method of automatic generation and reduction of
power networks at design early stage is suggested.power networks at design early stage is suggested.
In Simulation Results: 1G DRAMIn Simulation Results: 1G DRAM Simulation time reduction > 15XSimulation time reduction > 15X
Analysis error < 8%Analysis error < 8%
Due to the reduced complexity the simulation of Due to the reduced complexity the simulation of
multiple-bank operations was possible.multiple-bank operations was possible.
15/14
Thank You!