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Dynamic Combinational Circuits

• Dynamic circuits– Charge sharing, charge redistribution

• Domino logic

• np-CMOS (zipper CMOS)

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Dynamic Logic

• Dynamic gates use a clocked pMOS pullup

• Two modes: precharge and evaluate

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The Foot• What if pulldown network is ON during

precharge?

• Use series evaluation transistor to prevent fight.

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Dynamic Logic

Mp

Me

VDD

PDNIn1In2In3

OutMe

Mp

VDD

PUNIn1In2In3

Out

CL

CL

2 phase operation:• Evaluation

• Prechargen network p network

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Logical Effort

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Dynamic Logic

• N+2 transistors for N-input function– Better than 2N transistors for complementary static CMOS

– Comparable to N+1 for ratio-ed logic

• No static power dissipation– Better than ratio-ed logic

• Careful design, clock signal needed

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Dynamic Logic: Principles

Mp

Me

VDD

PDNIn1In2In3

Out

CL

• Precharge

= 0, Out is precharged to VDD by Mp.Me is turned off, no dc current flows(regardless of input values)

• Evaluation = 1, Me is turned on, Mp is turned off.

Output is pulled down to zero dependingon the values on the inputs. If not, precharged value remains on CL.

Important: Once Out is discharged, it cannot be charged again!Gate input can make only one transition during evaluation

• Minimum clock frequency must be maintained• Can Me be eliminated?

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Example

Mp

Me

VDD

Out

A

B

C

• Ratioles s

• No Static Power Cons umption

• Nois e Margins s mall (NML)

• Requires Clock

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Dynamic 4 Input NAND Gate

In1

In2

In3

In4

Out

VDD

GND

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Cascading Dynamic Gates

Mp

Me

VDD

Mp

Me

VDD

In

Out1 Out2

Internal nodes can only make 0-1 transitions during evaluation period

Out2

Out1

In

V

t

VTn

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Monotonicity• Dynamic gates require monotonically rising inputs

during evaluation– 0 -> 0

– 0 -> 1

– 1 -> 1

– But not 1 -> 0

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Monotonicity Woes• But dynamic gates produce monotonically falling

outputs during evaluation

• Illegal for one dynamic gate to drive another!

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Reliability Problems — Charge Leakage

Mp

Me

VDD

Out

ACL(1)

(2)

t

t

Vout

(b) Effect on waveforms(a) Leakage sources

precharge evaluate

Minimum Clock Frequency: > 1 MHz

A = 0

(1) Leakage through reverse-biased diode of the diffusion area(2) Subthreshold current from drain to source

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Leakage• Dynamic node floats high during evaluation

– Transistors are leaky (IOFF 0)

– Dynamic value will leak away over time

– Formerly miliseconds, now nanoseconds!

• Use keeper to hold dynamic node– Must be weak enough not to fight evaluation

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Charge Sharing (redistribution)

Mp

Me

VDD

Out

A

B = 0

CL

Ca

Cb

Ma

Mb

X

• Assume: during precharge, A and B are 0, Ca is discharged• During evaluation, B remains 0 and A rises to 1• Charge stored on CL is now redistributed over CL and Ca

CLVDD = CL Vout(t) + CaVX

VX = VDD - Vt, thereforeVout(t) = Vout(t) - VDD = (VDD-Vt)

CL

Ca

Desirable to keep the voltage drop below thresholdof pMOS transistor (why?) Ca/CL < 0.2

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Charge Sharing• Dynamic gates suffer from charge sharing

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Charge Redistribution - Solutions

Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl Mp

Me

VDD

Out

A

B

Ma

Mb

Mbl

(b) Precharge of internal nodes(a) Static bleeder

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Secondary Precharge• Solution: add secondary precharge transistors

– Typically need to precharge every other node

• Big load capacitance CY helps as well

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Domino Logic

Mp

Me

VDD

PDNIn1In2In3

Out1Mp

Me

VDD

PDNIn4

Out2

Mr

VDD

Static Inverterwith Level Restorer

Static invertersbetween dynamic stages

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Domino Gates• Follow dynamic stage with inverting static gate

– Dynamic / static pair is called domino gate

– Produces monotonic outputs

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Domino Logic - Characteristics

• O n l y n o n - i n v e r t i n g l o g i c

• V e r y f a s t - O n l y 1 - > 0 t r a n s i t i o n s a t i n p u t o f i n v e r t e r

• A d d i n g l e v e l r e s t o r e r r e d u c e s l e a k a g e a n d

c h a r g e r e d i s t r i b u t i o n p r o b l e m s

• O p t i m i z e i n v e r t e r f o r f a n - o u t

• Precharging makes pull-up very fast

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Domino Optimizations• Each domino gate triggers next one, like a string of

dominos toppling over

• Gates evaluate sequentially but precharge in parallel

• Thus evaluation is more critical than precharge

• HI-skewed static stages can perform logic

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Dual-Rail Domino• Domino only performs noninverting functions:

– AND, OR but not NAND, NOR, or XOR

• Dual-rail domino solves this problem– Takes true and complementary inputs

– Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged

0 1 ‘0’

1 0 ‘1’

1 1 invalid

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Example: AND/NAND• Given A_h, A_l, B_h, B_l

• Compute Y_h = A * B, Y_l = ~(A * B)

• Pulldown networks are conduction complements

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Example: XOR/XNOR

• Sometimes possible to share transistors

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Domino Summary

• Domino logic is attractive for high-speed circuits– 1.5 – 2x faster than static CMOS

– But many challenges:

• Monotonicity

• Leakage

• Charge sharing

• Noise

• Widely used in high-performance microprocessors

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np-CMOS (Zipper CMOS)

Mp

Me

VDD

PDNIn1In2In3

Me

Mp

VDD

PUNIn4

Out1

Out2

• Only 1-0 transitions allowed at inputs of PUN• Used a lot in the Alpha design

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np CMOS Adder

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CMOS Circuit Styles - Summary