dynamic combinational circuits - all...
TRANSCRIPT
James Morizio 1
Dynamic Combinational Circuits
• Dynamic circuits– Charge sharing, charge redistribution
• Domino logic• np-CMOS (zipper CMOS)
James Morizio 2
Dynamic Logic
• Dynamic gates use a clocked pMOS pullup• Two modes: precharge and evaluate
1
2A Y
4/3
2/3
AY
1
1
AY
φ
Static Pseudo-nMOS Dynamic
φ Precharge Evaluate
Y
Precharge
James Morizio 3
The Foot• What if pulldown network is ON during
precharge?• Use series evaluation transistor to prevent fight.
AY
φ
foot
precharge transistor φY
inputs
φY
inputs
footed unfooted
f f
James Morizio 4
Dynamic Logic
Mp
Me
VDD
PDNIn1In2In3
OutMe
Mp
VDD
PUNIn1In2In3
Out
CL
CL
2 phase operation:• Evaluation
• PrechargeΦ
Φ
Φ
n network Φp network
Φ
Φ
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Logical EffortInverter NAND2 NOR2
1
1
AY
2
2
1
B
AY
A B 11
1
gd = 1/3pd = 2/3
gd = 2/3pd = 3/3
gd = 1/3pd = 3/3
Yφ
φ
φ
2
1
AY
3
3
1
B
AY
A B 22
1
gd = 2/3pd = 3/3
gd = 3/3pd = 4/3
gd = 2/3pd = 5/3
Yφ
φ
φ
footed
unfooted
32 2
James Morizio 6
Dynamic Logic• N+2 transistors for N-input function
– Better than 2N transistors for complementary static CMOS – Comparable to N+1 for ratio-ed logic
• No static power dissipation– Better than ratio-ed logic
• Careful design, clock signal Φ needed
James Morizio 7
Dynamic Logic: Principles
Mp
Me
VDD
PDNIn1In2In3
Out
CL
Φ
Φ
• PrechargeΦ = 0, Out is precharged to VDD by Mp.Me is turned off, no dc current flows(regardless of input values)
• EvaluationΦ = 1, Me is turned on, Mp is turned off.Output is pulled down to zero dependingon the values on the inputs. If not, precharged value remains on CL.
Important: Once Out is discharged, it cannot be charged again!Gate input can make only one transition during evaluation
• Minimum clock frequency must be maintained• Can Me be eliminated?
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Example
Mp
Me
VDD
Out
A
B
C
• Ratio les s
• No Static Power Cons umption
• Nois e Margins s mall (NML)
• Requires Clock
Φ
Φ
James Morizio 9
Dynamic 4 Input NAND Gate
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James Morizio 10
Cascading Dynamic Gates
Mp
Me
VDD
Mp
Me
VDD
In
Out1 Out2Φ
Φ
Φ
Φ
Internal nodes can only make 0-1 transitions during evaluation period
Out2
Out1
In
V
t
VTn
Φ
James Morizio 11
Monotonicity• Dynamic gates require monotonically rising inputs
during evaluation– 0 -> 0– 0 -> 1– 1 -> 1– But not 1 -> 0
φ Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity during evaluation
A
φ
James Morizio 12
Monotonicity Woes• But dynamic gates produce monotonically falling
outputs during evaluation• Illegal for one dynamic gate to drive another!
A X
φY
φ Precharge Evaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
James Morizio 13
Reliability Problems — Charge Leakage
Mp
Me
VDD
Out
ACL
(1)
(2)
t
t
Vout
(b) Effect on waveforms(a) Leakage sources
precharge evaluate
Minimum Clock Frequency: > 1 MHz
A = 0
Φ
ΦΦ
(1) Leakage through reverse-biased diode of the diffusion area(2) Subthreshold current from drain to source
James Morizio 14
Leakage• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF ≠ 0)– Dynamic value will leak away over time– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node– Must be weak enough not to fight evaluation
A
φH
2
2
1 kX Y
weak keeper
James Morizio 15
Charge Sharing (redistribution)
Mp
Me
VDD
Out
A
B = 0
CL
Ca
Cb
Ma
Mb
X
• Assume: during precharge, A and B are 0, Ca is discharged• During evaluation, B remains 0 and A rises to 1• Charge stored on CL is now redistributed over CL and Ca
CLVDD = CL Vout(t) + CaVX
VX = VDD - Vt, thereforeδVout(t) = Vout(t) - VDD = (VDD-Vt)CL
Ca
Desirable to keep the voltage drop below thresholdof pMOS transistor (why?) � Ca/CL < 0.2
James Morizio 16
Charge Sharing• Dynamic gates suffer from charge sharing
B = 0
AY
φ
x
Cx
CY
A
φ
x
Y
Charge sharing noise
Yx Y DD
x Y
CV V V
C C= =
+
James Morizio 17
Charge Redistribution - Solutions
Mp
Me
VDD
Out
A
B
Ma
Mb
Mbl Mp
Me
VDD
Out
A
B
Ma
Mb
Mbl
(b) Precharge of internal nodes(a) Static bleeder
Φ
Φ Φ
Φ
Φ
James Morizio 18
Secondary Precharge• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well
B
AY
φ
x
secondaryprechargetransistor
James Morizio 19
Domino Logic
Mp
Me
VDD
PDNIn1In2
In3
Out1Mp
Me
VDD
PDNIn4
Out2
Mr
VDD
Static Inverterwith Level Restorer
Φ
Φ
Φ
Φ
Static invertersbetween dynamic stages
James Morizio 20
Domino Gates• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate– Produces monotonic outputs
φ Precharge Evaluate
W
Precharge
X
Y
Z
A
φ
B C
φ φ φ
C
AB
W X Y Z =X
ZH H
A
W
φ
B C
X Y Z
domino AND
dynamicNAND
staticinverter
James Morizio 21
Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1->0 transitions at input of inverter
• Adding level restorer reduces leakage andcharge redistribution problems
• Optimize inverter for fan-out
• Precharging makes pull-up very fast
James Morizio 22
Domino Optimizations• Each domino gate triggers next one, like a string of
dominos toppling over• Gates evaluate sequentially but precharge in parallel• Thus evaluation is more critical than precharge• HI-skewed static stages can perform logic
S0
D0
S1
D1
S2
D2
S3
D3
φ
S4
D4
S5
D5
S6
D6
S7
D7
φ
YH
James Morizio 23
Dual-Rail Domino• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem– Takes true and complementary inputs – Produces true and complementary outputs
invalid11
‘1’01
‘0’10
Precharged00
Meaningsig_lsig_hY_h
f
φ
φ
inputs
Y_l
f
James Morizio 24
Example: AND/NAND• Given A_h, A_l, B_h, B_l• Compute Y_h = A * B, Y_l = ~(A * B)• Pulldown networks are conduction complements
Y_hφ
φ
Y_lA_h
B_hB_lA_l
= A*B= A*B
James Morizio 25
Example: XOR/XNOR
• Sometimes possible to share transistors
Y_hφ
φ
Y_lA_l
B_h
= A xor B
B_l
A_hA_lA_h= A xnor B
James Morizio 26
Domino Summary
• Domino logic is attractive for high-speed circuits– 1.5 – 2x faster than static CMOS– But many challenges:
• Monotonicity• Leakage• Charge sharing• Noise
• Widely used in high-performance microprocessors
James Morizio 27
np-CMOS (Zipper CMOS)
Mp
Me
VDD
PDNIn1In2In3
Me
Mp
VDD
PUNIn4
Out1
Out2
Φ
Φ
Φ
Φ
• Only 1-0 transitions allowed at inputs of PUN• Used a lot in the Alpha design
James Morizio 28
np CMOS Adder
VDD
φ
φCi0
A0 B0 B0
φ
A0
VDD
φ
B1
φ
A1
VDD
φ
φ
A1 B1
Ci1
Ci2
Ci0
Ci0
B0
A0B0
S0
A0
VDD
φ
φ
VDD
φ
VDD
φ
φ
B1 Ci1
B1
φ
A1A1
VDD
φ S1
Ci1
Carry Path
James Morizio 29
CMOS Circuit Styles - Summary