dspr in vhdl
DESCRIPTION
kgjhTRANSCRIPT
-
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity path is
port (
clk: in STD_LOGIC;
reset: in STD_LOGIC;
data: in STD_LOGIC_VECTOR (7 downto 0);
pathOut: out STD_LOGIC_VECTOR (7 downto 0);
addr: out STD_LOGIC_VECTOR (15 downto 0);
ALUFlag: out STD_LOGIC_VECTOR (8 downto 0)
);
end path;
architecture path_arch of path is
--multiplier
COMPONENT mult
PORT(
clk : IN std_logic;
start : IN std_logic;
pass : IN std_logic;
finish: IN std_logic;
result: OUT std_logic_vector(9 DOWNTO 0);
mstate: BUFFER std_logic_vector(1 DOWNTO 0);
in0 : IN std_logic_vector(3 DOWNTO 0);
in1 : IN std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
-- ALU
COMPONENT alu
-
port (
inA: in STD_LOGIC_VECTOR (9 downto 0);
inB: in STD_LOGIC_VECTOR (9 downto 0);
fn: in STD_LOGIC_VECTOR (3 downto 0);
aluout: out STD_LOGIC_VECTOR (9 downto 0);
flags: out STD_LOGIC_VECTOR (3 downto 0)
);
END COMPONENT;
COMPONENT shifter
port (
shtIn: in STD_LOGIC_VECTOR (9 downto 0);
sfn: in STD_LOGIC_VECTOR (3 downto 0);
shtOut: out STD_LOGIC_VECTOR (9 downto 0);
shtFlag: out STD_LOGIC;
shEn: in std_logic
);
END COMPONENT;
-- register signals
SIGNAL r0,r1,r2,r3: std_logic_vector(3 downto 0);
SIGNAL rgEn: std_logic;
-- multiplier interconnects
SIGNAL pass_logic: std_logic;
SIGNAL mul1,mul2,rin: std_logic_vector(3 downto 0);
SIGNAL multout: std_logic_vector(9 DOWNTO 0);
--mux and tristate signals
SIGNAL d1out, d2out: STD_LOGIC_VECTOR (9 downto 0);
SIGNAL outEn: STD_LOGIC;
--alu connection signals
SIGNAL aluout, aluI1, aluI2 : STD_LOGIC_VECTOR (9 downto 0);
--alu state signals
-
SIGNAL astate, anextstate: STD_LOGIC_VECTOR (1 downto 0);
--flag signals
SIGNAL tmpflag, mulflag, spflag, lmFlag: std_logic_vector(3 downto 0);
SIGNAL sflag: std_logic;
-- signals for accumulator file
SIGNAL a0, a1,a2,a3: STD_LOGIC_VECTOR (9 downto 0);
SIGNAL acon: STD_LOGIC_VECTOR (1 downto 0);
SIGNAL regEn: STD_LOGIC;
--limiter signals
SIGNAL lmOut: STD_LOGIC_VECTOR (7 downto 0);
SIGNAL lmIn: STD_LOGIC_VECTOR (9 downto 0);
SIGNAL lmfn: STD_LOGIC_VECTOR (3 downto 0);
SIGNAL zz: std_logic_vector(11 downto 0);
-- Instruction Register Signals
SIGNAL op: std_logic_vector(2 downto 0);
SIGNAL func: std_logic_vector(4 downto 0);
SIGNAL shOp: std_logic_vector(3 downto 0);
SIGNAL aca, acb: std_logic_vector(1 downto 0);
SIGNAL imm: std_logic_vector(9 downto 0);
SIGNAL imm2: std_logic_vector(3 downto 0);
SIGNAL ra, rb: std_logic_vector(1 downto 0);
-- Shifter Signals
SIGNAL shtOut: std_logic_vector(9 downto 0);
SIGNAL shift: std_logic;
-- address signal registers
SIGNAL ir1: std_logic_vector(7 DOWNTO 0);
SIGNAL ir2: std_logic_vector(7 DOWNTO 0);
SIGNAL mah: std_logic_vector(7 downto 0);
SIGNAL mal: std_logic_vector(7 downto 0);
SIGNAL pc: std_logic_vector(15 downto 0);
-
SIGNAL disp: std_logic;
-- state signal definitions
SIGNAL state: std_logic_vector(2 downto 0);
SIGNAL nextstate: std_logic_vector(2 downto 0);
-- execute start and finish signals
SIGNAL start: std_logic;
SIGNAL finish: std_logic;
SIGNAL mstate: std_logic_vector(1 downto 0);
BEGIN
-- multiplier port map
mlt: mult PORT MAP (
clk => clk,
start => start,
finish => finish,
result => multout,
mstate => mstate,
pass => pass_logic,
in0 => mul1,
in1 => mul2
);
--ALU port map
a: alu PORT MAP (
inA => aluI1,
inB => aluI2,
fn => func(3 downto 0),
aluout => aluout,
flags => tmpflag
);
-- shifter port map
s: shifter PORT MAP (
-
shtIn => d1out,
sfn => shOp,
shtOut => shtOut,
shtFlag => sflag,
shEn => shift
);
-- Map labels from IRs
mp: PROCESS (ir1,ir2)
BEGIN
op
- regEn
-
"101" WHEN (state = "010" AND NOT (disp = '1')) ELSE
-- 3->4
"100" WHEN (state = "011") ELSE
-- 4->5
"101" WHEN (state = "100") ELSE
-- 5->5
"101" WHEN (state = "101" AND finish = '0') ELSE
-- 5->1
"001" WHEN (state = "101" AND finish = '1') ELSE
-- ?
"000";
-- Sequential logic
PROCESS (clk, reset)
BEGIN
IF (reset ='1') THEN
pc
-
END IF;
-- State 1->2 transition
IF (nextstate = "010" AND state = "001") THEN
ir2 5 transition
IF (nextstate = "101" AND state = "001") THEN
start 5 transition
IF (nextstate = "101" AND state = "010") THEN
start 3 transition
IF (nextstate = "011" AND state = "010") THEN
mah 4 transition
IF (nextstate = "100" AND state = "011") THEN
mal 5 transition
IF (nextstate = "101" AND state = "100") THEN
start 1 transition
IF (nextstate = "001" AND state = "101") THEN
ir1
-
END IF;
END IF;
END PROCESS;
-- mux for accumlators
regSel: PROCESS (clk, reset)
BEGIN
IF (reset ='1') THEN
a0
-
-- register file input decision
reg_in: process (func)
BEGIN
IF (func(0) = '1') THEN
rin
- WHEN "10" => r2 r3 mul1 mul1 mul1 mul1
- WHEN "00" => mul2 mul2 mul2 mul2
-
--limiter
funct:PROCESS(lmIn, lmfn)
BEGIN
CASE lmfn IS
WHEN "1000" => --limit to eight (LIMA)
IF lmIn(8 DOWNTO 7) = "00" THEN
zz
- mulflag(0)
-
---------------------------------------------------------------------------------------------------------
-- 10-bit ALU for DSP
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port (
inA: in STD_LOGIC_VECTOR (9 downto 0);
inB: in STD_LOGIC_VECTOR (9 downto 0);
fn: in STD_LOGIC_VECTOR (3 downto 0);
aluout: out STD_LOGIC_VECTOR (9 downto 0);
flags: out STD_LOGIC_VECTOR (3 downto 0)
);
end alu;
architecture alu_arch of alu is
signal z: std_logic_vector(10 downto 0);
begin
sort: PROCESS (fn, inA,inB)
BEGIN
CASE fn(3 DOWNTO 0) IS
WHEN "0000" => z z z z z z z z
-
WHEN "1000" => z z z
IF inA(9) = '1' THEN
z
- WHEN OTHERS => aluout z z z z z
-
nput
WHEN "0101" =>
IF shtIn(3 DOWNTO 0) = "0000" THEN
z
-
clk : IN std_logic;
start : IN std_logic;
pass : IN std_logic;
finish: IN std_logic;
result: OUT std_logic_vector(9 DOWNTO 0);
mstate: BUFFER std_logic_vector(1 DOWNTO 0);
in0 : IN std_logic_vector(3 DOWNTO 0);
in1 : IN std_logic_vector(3 DOWNTO 0)
);
END mult;
ARCHITECTURE one OF mult IS
-- Signal definitions
SIGNAL product, nextproduct: std_logic_vector(7 DOWNTO 0);
SIGNAL count, nextcount: std_logic_vector(2 DOWNTO 0);
SIGNAL state,nextstate: std_logic_vector(1 DOWNTO 0);
SIGNAL mult,nextmult: std_logic_vector(3 DOWNTO 0);
SIGNAL answer: std_logic_vector(7 DOWNTO 0);
SIGNAL sum,temp: std_logic_vector(3 DOWNTO 0);
BEGIN
-- Combinatorial logic
result
-
"01" WHEN (state = "00" AND start = '1') ELSE
"01" WHEN (state = "01" AND count < "100") ELSE
"10" WHEN (state = "01" AND count = "100") ELSE
"10" WHEN (state = "10" AND start = '1') ELSE
"00";
-- Sequential logic
PROCESS(clk,in0,in1,start)
BEGIN
-- Initialization
IF (start = '0') THEN
count
-
IF (nextstate = "10") THEN
answer