TMS320C5x

By-D.Jenny Simpsolin

Memory Space Overview The ’C5x design is based on the enhanced

Harvard architecture, which has multiple memory spaces that can be accessed on two parallel buses

This makes it possible to access both program and data simultaneously.

The two parallel buses are the program bus (PB) and data read bus (DB).

On-Chip Memory

The ’C5x architecture contains a considerable amount of on-chip memory to aid in system performance and integration: Program read-only memory (ROM) Data/program dual-access RAM (DARAM) Data/program single-access RAM (SARAM)

The ’C5x has a total address range of 224K words x 16 bits.

The memory space is divided into four individually selectable memory segments: 64K-word program memory space 64K-word local data memory space 64K-word input/output ports 32K-word global data memory space.

Within a given machine cycle, the ALU can execute as many as three concurrent memory operations.

64K-word program space contains the instructions to be executed.

64K-word local data space stores data used by the instructions.

32K-word global data space can share data with other processors within the

system or can serve as additional data space. 64K-word I/O port space

Interfaces to external memory-mapped peripherals and can also serve as extra data storage space.

The advantages of operating from internal (on-chip) memory:

1) Higher performance because no wait states are required for slower external memories.

2) Lower cost than external memory.3) Lower power than external memory.

The large on-chip memory enhances system performance

and integration. It includes:

Program Read-Only Memory(ROM)

Single Access RAM in Program/Data(SARAM)

Dual Access RAM in Program/Data(DARAM)

Program Read-Only Memory(ROM) 16 bit on chip maskable programmable ROM. Some C5X DSPs have boot loader code in the ROM. Program can reside on both ON and OFF chip. By manipulating the MP/ bit in processor mode

status register (PMST) or by MP/MC pin control input,the ROM can be enabled or disabled.

MP/MC bit High->On-chip is enabled MP/MC bit Low->Off-chip

Data/Program Single-Access RAM 16-bit on chip SARAM Codes can be booted from an off-chip ROM and

then executed at full speed from SARAM SARAM can be configured in one of the following

ways-> Data memory Program memory Both data and program memory

Parallel access to various SARAM block, but only one block can be accessed per machine cycle.

Data/Program Dual-Access RAM 1056 word x 16 bit DARAM Used to store values or programs Three memory blocks->

512 word data or program block B0 512 word data block B1 32 word data block B2

The first instruction could be reading data while the next instruction is writing data.

On Chip Memory Protection The program memory protection feature prevents

an instruction fetched from off-chip memory from reading or writing on-chip program memory.

On-Chip Peripherals Clock Generator Hardware Timer Software-Programmable Wait-State

Generators Parallel I/O Ports Serial Port Interface Buffered Serial Port (BSP) Interface Time-Division Multiplexed (TDM) Serial Port

Interface Host Port Interface User Maskable Interrupts

Clock Generator

The ’C5x clock generator consists of an internal oscillator and a phase lock loop (PLL) circuit that provides the flexibility for the system designer to select the clock source.

The clock generator is driven by a crystal resonator circuit or by an external clock source.

The frequency of CLKOUT1 is one-half the crystal oscillating frequency.

PLL multiplies clock with a specific factor.Hence lower frequency clock source can be used.

Hardware Timer

The 16-bit timer is an on-chip down counter that can be used to periodically generate CPU interrupts.

The timer operation is controlled via the timer control register (TCR), the timer counter register (TIM), and the timer period register (PRD).

The timer is driven by a prescaler(PSC) which is decremented by 1 at every CLKOUT1 cycle.

It can be stopped,restarted,reset or disabled by status bits.

OPERATION When the PSC

decrements to 0 ,the contents of the TDDR(Timer divide down register) are loaded into the PSC and the TIM is decremented.

When the TIM decrements to 0 ,the contents of the PRD are loaded into the TIM.

A timer interrupt (TINT) is generated each time the counter decrements to 0.

Software-Programmable Wait-State Generators

The software-programmable wait-state generators can extend external bus cycles by up to seven machine cycles.

This operation provides a convenient means to interface the ’C5x to external devices that do not satisfy the full speed access-time requirement of the ’C5x.

Two 16-bit wait-state registers and a 5-bit control register control the software programmable wait-state generators.

Parallel I/O Ports

The ’C5x has 64K parallel I/O ports. Sixteen of the 64K I/O ports are memory mapped

You can access the 64K I/O ports using the IN and OUT instructions.

Can be accessed by read or write instructions also..

The C5x requires minimal off-chip address decoding circuits.

Serial Port Interface

Types-> basic standard serial port interface (SP) buffered serial port(BSP) Time-Division Multiplexed (TDM) Serial Port

Standard serial port C5x consists of atleast one general-purpose,high-

speed synchronous,full-duplexed serial port interface.

Direct communication with devices like codecs,ADC etc.

Serial port operates upto 1/4th of machine cyle rate.

16-bit registers for control SPC-serial port control DRR-data receive register DXR-data transmit register XSR-data transmit shift register RSR-data receive shift register

Buffered serial port Full duplexed,double buffered with autobuffering

unit(ABU) Provides flexibility on the data stream length. High speed,less interrupt latencies. 2K word buffer.

TDM serial port The time-division multiplexed (TDM) serial port

allows the ’C5x device to communicate serially with up to seven other devices.

Can be used for synchronous also. Time-division multiplexing is the division of time

intervals into a number of subintervals, with each subinterval representing a communications channel according to a prespecified arrangement

Addressing Modes Direct addressing Indirect addressing Immediate addressing Dedicated-register addressing Memory-mapped register addressing Circular addressing

Direct Addressing

Data memory split into 512 pages,128 words long.In the direct memory addressing mode, the instruction contains the lower 7 bits of the data memory address (dma).

The 7-bit dma is concatenated with the 9 bits of the data memory page pointer (DP) in status register 0 to form the full 16-bit data memory address.

This 16-bit data memory address is placed on an internal direct data memory address bus (DAB).

Indirect Addressing Eight 16-bit auxiliary registers (AR0–AR7) provide

flexible and powerful indirect addressing. In indirect addressing, any location in the 64K-

word data memory space can be accessed using a 16-bit address contained in an AR,denoted by ARP.

Content of ARP temporarily stored in ARB. AR is automatically updated. After the instruction uses the data value, the

content of the current AR can be incremented or decremented by the auxiliary register arithmetic unit (ARAU), which implements unsigned 16-bit arithmetic.

Immediate Addressing In immediate addressing, the instruction word(s)

contains the value of the immediate operand. 16 bit constant or 13,9,7 bit constants can be

loaded. Represented by #. Types

Short Immediate Addressing operand is contained within the instruction machine

code. ADD #0FFh

Long Immediate Addressing the operand is contained in the second word of a two-

word instruction. ADD #01234h

Dedicated-Register Addressing The dedicated-registered addressing mode

operates like the long immediate addressing mode, except that the address comes from one of two special-purpose memory-mapped registers in the CPU: the block move address register (BMAR) the dynamic bit manipulation register (DBMR).

Memory-Mapped Register Addressing With memory-mapped register addressing, you can

modify the memory mapped registers without affecting the current data page pointer value.

The following instructions operate in the memory-mapped register addressing mode. Using these instructions does not affect the contents of the DP: LAMM — Load accumulator with memory-mapped

register LMMR — Load memory-mapped register SAMM — Store accumulator in memory-mapped

register SMMR — Store memory-mapped register

Like direct addressing,except that the 9 MSB are made 0.

Circular Addressing Many algorithms such as convolution,

correlation, and finite impulse response(FIR) filters can use circular buffers in memory to implement a sliding window, which contains the most recent data to be processed.

The following five memory-mapped registers control the circular buffer operation: CBSR1 — Circular buffer 1 start register CBSR2 — Circular buffer 2 start register CBER1 — Circular buffer 1 end register CBER2 — Circular buffer 2 end register CBCR — Circular buffer control register