8/13/2019 Dsp _ Vlsi.docx

1/1

ECE 528 DSP for VLSIL

3

T

0

P

0

C

3

Version No. 1.0

Prerequisite

Course

Description:

This course deals with the concept of Reconfigurable Computing. For better

understanding the reconfigurable computing FPGA and their applicationsare described.

Expected Outcome: At the end of the course, the student will be able to

1. Understand the use of VLSI in DSP.

2. Design the different digital filters with efficient ways using VLSI.

Unit I Introduction to DSP Systems

Introduction to DSP Systems, Iteration bound, Data Flow graphs (DFGs) representation, Loop

Bound, Iteration rate, Critical loop, Critical path, Area-Speed-Power trade-offs, Algorithms for

computing iteration bound, Pipelining of FIR Digital Filters, Parallel Processing, Pipelining and

Parallel Processing for low power.

Unit II Algorithmic Transformations

Retiming Definitions and properties, Retiming Techniques, Clock period minimization, Unfolding,

An algorithm for unfolding, Critical path, Applications of unfolding, Sample period reduction,

Folding, Folding order, Folding Factor, register minimization techniques, register minimization in

folded architecture, Forward Backward Register Allocation technique, folding of multi-rate systems,

Folding Bi-quad filters, Retiming for folding.

Unit III Systolic Architecture Design and Fast Convolution

Introduction, system array design methodology, FIR systolic arrays, , Systolic Design for space

representations containing delays Systolic architecture design methodology, Design examples of

systolic architectures, selection of scheduling vector, matrix-matrix multiplication and 2-D systolic

array design, Hardware Utilization efficiency, Cook-Toom Algorithm, Wniograd Algorithm,

Iterated Convolution, Cyclic Convolution, Design of fast convolution algorithm by inspection.Unit IV Algorithm Strength Reduction in filter

Introduction, Parallel FIR filters, Polyphase decomposition, Discrete Cosine Transform and Inverse

Discrete Cosine Transform, parallel architectures for Rank Order filters.

Unit V Pipelined and Parallel Recursive and Adaptive Filters

Introduction, pipelining in 1st order IIR digital filters, pipelining in higher order IIR digital filters,

parallel processing for IIR filters, combined pipelining and parallel processing for IIR filters, low

power IIR Filter Design using pipelining and parallel processing, pipelined adaptive digital filters.

Reference Books

1. Parhi, K.K., VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley

(2007).

2. Oppenheim, A.V. and Schafer, R.W., Discrete-Time Signal Processing, Prentice Hall (2009) 2nd

ed.

3. Mitra, S.K., Digital Signal Processing. A Computer Based Approach, McGraw Hill (2007)3rd ed.

4. Wanhammar, L., DSP Integrated Circuits, Academic Press (1999).2005, ISBN: 978-0131543188.

Mode of Evaluation Written Examinations, Quizzes, Assignments.

Recommended by the Board of Studies on:

Date of Approval by the Academic Council: