dsk6416_techref
TRANSCRIPT
TMS320C6416T DSK
2004 DSP Development Systems
ReferenceTechnical
TMS320C6416T DSK Technical Reference
508035-0001 Rev. A November 2004
SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com
IMPORTANT NOTICE
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Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.
Copyright © 2004 Spectrum Digital, Inc.
Contents
1 Introduction to the TMS320C6416T DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the TMS320C6416T DSK Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the TMS320C6416T DSK. 2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 CPLD Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.3 USER_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.4 DC_REG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.5 Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.6 MISC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4 Flash ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 LEDs and DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.7 CPU and EMIFA Clcok Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-83 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the TMS320C6416T DSK and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Connector Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.1 J201, USB Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.2 J8, External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.7 System LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.8 Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the TMS320C6416T DSKB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the TMS320C6416T DSK
About This Manual
This document describes the board level operations of the TMS320C6416T DSPStarter Kit (DSK) module. The DSK is based on the Texas Instruments TMS320C6416T Digital Signal Processor.
The TMS320C6416T DSK is a table top card to allow engineers and softwaredevelopers to evaluate certain characteristics of the TMS320C6416T DSP to determineif the processor meets the designers application requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6416T DSK will sometimes be referred to as the DSK, C6416T DSK, orTMS320C6416 DSK.
Program listings, program examples, and interactive displays are shown is a specialitalic typeface. Here is a sample program listing.
equations!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C64xx DSP CPU Reference GuideTexas Instruments TMS320C64xx DSP Peripherals Reference Guide
Table 1: Manual History
Revision History
A Initial Release
1-1
Chapter 1
Introduction to the TMS320C6416T DSK
Chapter One provides a description of the TMS320C6416T DSK alongwith the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-7
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1-2 TMS320C6416T DSK Module Technical Reference
1.1 Key Features
The C6416T DSK is a low-cost standalone development platform that enables users toevaluate and develop applications for the TI C64xx DSP family. The DSK also servesas a hardware reference design for the TMS320C6416T DSP. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.
The DSK comes with a full compliment of on-board devices that suit a wide variety ofapplication environments. Key features include:
• A Texas Instruments TMS320C6416T DSP operating at 1 Gigahertz.
• An AIC23 stereo codec
• 16 Mbytes of synchronous DRAM
• 512 Kbytes of non-volatile Flash memory
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configured boot options and clock input selection
• Standard expansion connectors for daughter card use
• JTAG emulation through on-board JTAG emulator with USB host interface or external emulator
• Single voltage power supply (+5V)
Figure 1-1, Block Diagram C6416T DSK
Ext.JTAG
AIC23Codec
Hos
t Por
t Int
MUX
MUX
MIC
IN
LIN
E O
UT
HP
OU
T
LIN
E IN
Peripheral Exp
LED DIP
EMIFA
HPI
McBSPs
JTAG
0 1 2 30 1 2 3
CPL
D
Memory Exp
VoltageReg
PWR
USB
EmbeddedJTAG
JP1 1.2V
JP2 3.3V
END
IAN
BOO
TM 1
BOO
TM 0
SDR
AM
648
Flas
h
8
EMIFB
1 32
ConfigSW3
32
JP45V
SPAR
E
4
6416TDSP
PLL_
SEL1
PLL_
SEL2
PLL_
SEL3
5 76
PLL_
SEL4
8
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1.2 Functional Overview of the TMS320C6416T DSK
The DSP on the 6416T DSK interfaces to on-board peripherals through one of twobusses, the 64-bit wide EMIFA and the 8-bit wide EMIFB. The SDRAM, Flash andCPLD are each connected to one of the busses. EMIFA is also connected to thedaughter card expansion connectors which is used for third party add-in boards.
An on-board AIC23 codec allows the DSP to transmit and receive analog signals. McBSP1 is used for the codec control interface and McBSP2 is used for data. AnalogI/O is done through four 3.5mm audio jacks that correspond to microphone input, lineinput, line output and headphone output. The codec can select the microphone or theline input as the active input. The analog output is driven to both the line out (fixedgain) and headphone (adjustable gain) connectors. McBSP1 and McBSP2 can be re-routed to the expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that tiesthe board components together. The CPLD also has a register based user interfacethat lets the user configure the board by reading and writing to the CPLD registers.
The DSK includes 4 LEDs and 4 position DIP switch as a simple way to provide theuser with interactive feedback. Both are accessed by reading and writing to the CPLDregisters.
An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the 1.2V DSP core voltage and 3.3V I/O supplies. Theboard is held in reset until these supplies are within operating specifications. Aseparate regulator powers the 3.3V lines on the expansion interface.
Code Composer communicates with the DSK through an embedded JTAG emulatorwith a USB host interface. The DSK can also be used with an external emulatorthrough the external JTAG connector.
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1-4 TMS320C6416T DSK Module Technical Reference
1.3 Basic Operation
The DSK is designed to work with TI’s Code Composer Studio developmentenvironment and ships with a version specifically tailored to work with the board.Code Composer communicates with the board through the on-board JTAG emulator.To start, follow the instructions in the Quick Start Guide to install Code Composer. This process will install all of the necessary development tools, documentation anddrivers.
After the install is complete, follow these steps to run Code Composer. The DSK mustbe fully connected to launch the DSK version of Code Composer.
1) Connect the included power supply to the DSK.
2) Connect the DSK to your PC with a standard USB cable (also included).
3) Launch Code Composer from its icon on your desktop.
Detailed information about the DSK including a tutorial, examples and referencematerial is available in the DSK’s help file. You can access the help file through CodeComposer’s help menu. It can also be launched directly by double-clicking on the filec6416Tdsk.hlp in Code Composer’s docs\hlp subdirectory.
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1.4 Memory Map
The C64xx family of DSPs has a large byte addressable address space. Program codeand data can be placed anywhere in the unified address space. Addresses are always32-bits wide.
The memory map shows the address space of a generic 6416T processor on the leftwith specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.
Each EMIF (External Memory Interface) has 4 separate addressable regions calledchip enable spaces (CE0-CE3). The SDRAM occupies CE0 of EMIFA while the CPLDand Flash are mapped to CE0 and CE1 of EMIFB respectively. Daughter cards useCE2 and CE3 of EMIFA.
Figure 1-2, Memory Map, C6416T DSK
Internal Memory
Reserved Spaceor
Peripheral Regs
EMIFB CE0
EMIFB CE3
EMIFB CE2
EMIFB CE1
AddressGeneric 6416
Address Space
0x60000000
0x64000000
0x68000000
0x6C000000
SDRAM
CPLD
Flash
DaughterCard
6416 DSK
InternalMemory
Reservedor
Peripheral
EMIFA CE0
EMIFA CE3
EMIFA CE2
EMIFA CE1
0x80000000
0x90000000
0xA0000000
0xB0000000
0x00000000
0x00100000
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1-6 TMS320C6416T DSK Module Technical Reference
1.5 Configuration Switch Settings
The DSK has 8 configuration switches that allows users to control the operational stateof the DSP when it is released from reset. The configuration switch block is labeledSW3 on the DSK board, next to the reset switch.
Configuration switch 1 controls the endianness of the DSP while switches 2 and 3configure the boot mode that will be used when the DSP starts executing. Position 4 onSW3 is a spare. Positions 5-8 on SW3 control the CPU and EMIFA clockingfrequencies. By default all switches are off which corresponds to EMIFB boot (out of 8-bit Flash) in little endian mode at 1 gigahertz CPU frequency and 125 Mhz.EMIFA frequency. The following 2 tables show these settings.
* SW3-4 is spare** Default
Table 1: Boot/Endian Configuration Switch Settings
SW3-4 * SW3-3 SW3-2 SW3-1 Configuration Description
x Off Off EMIF boot from 8-bit Flash **
x Off On No Boot
x On Off Reserved
x On On HPI boot
x Off Little endian **
x On Big endian
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The following table shows the switch position settings for desired CPU and EMIFAfrequencies.
** Default
1.6 Power Supply
The DSK operates from a single +5V external power supply connected to the mainpower input (J5). Internally, the +5V input is converted into +1.2V and +3.3V using adual voltage regulator. The +1.2V supply is used for the DSP core while the +3.3Vsupply is used for the DSP's I/O buffers and all other chips on the board. The powerconnector is a 2.5mm barrel-type plug.
There are three power test points on the DSK at JP1, JP2 and JP4. All 6416T I/Ocurrent passes through JP2 while all core current passes through JP1. All systemcurrent passes through JP4. Normally these jumpers are closed. To measure thecurrent passing through remove the jumpers and connect the pins with a currentmeasuring device such as a multimeter or current probe.
The DSK provides +3.3V, up to 1A for the daughter card. The +3.3V supply is derivedfrom the +5V power source via the main +3.3 volt regulator. It is also possible toprovide the daughter card with +12V and -12V when the external power connector (J6)is used.
Table 2: CPU and EMIFA Frequency Configuration Switch Settings
SW3-8 SW3-7 SW3-6 SW3-5 CPU Frequency EMIFA Frequency
Off Off Off Off 1 Ghz. 125 Mhz. **
Off Off Off On Reserved Reserved
Off Off On Off Reserved Reserved
Off Off On On 720 Mhz. 125 Mhz.
Off On Off Off 850 Mhz. 125 Mhz.
Off On Off On Reserved Reserved
Off On On Off Reserved Reserved
Off On On On 1.2 Ghz. 125 Mhz.
On Off Off Off Reserved Reserved
On Off Off On 500 Mhz. 100 Mhz.
On Off On Off 600 Mhz. 100 Mhz.
On Off Off On Reserved Reserved
On On Off Off Reserved Reserved
On On On On Reserved Reserved
On On On Off Reserved Reserved
On On On On Reserved Reserved
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2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components onthe TMS320C6416T DSK.
Topic Page
2.1 CPLD (Programmable Logic) 2-22.1.1 CPLD Overview 2-22.1.2 CPLD Registers 2-32.1.3 USER_REG Register 2-32.1.4 DC_REG Register 2-42.1.5 Version Register 2-42.1.6 MISC Register 2-52.2 AIC23 Codec 2-62.3 Sychronous DRAM 2-72.4 Flash Memory 2-72.5 LEDs and DIP Switches 2-72.6 Daughter Card Interface 2-82.7 DSP and EMIFA Clock Generation 2-8
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2-2 TMS320C6416T DSK Module Technical Reference
2.1 CPLD (Programmable Logic)
The C6416T DSK uses an Altera EPM3128TC100-10 Complex Programmable LogicDevice (CPLD) device to implement:
• 4 Memory-mapped control/status registers that allow software control of various board features.
• Address decode and memory access logic.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your ownhardware designs will likely implement a completely different set of functions or takeadvantage of the DSPs high level of integration for system design and avoid the use of external logic completely.
The CPLD implements simple random logic functions that eliminate the need foradditional discrete devices. In particular, the CPLD aggregates the various resetsignals coming from the reset button and power supervisors and generates a globalreset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides 128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface (a 10-pin header on the DSK). The CPLD source files are written in the industrystandard VHDL (Hardware Design Language) and included with the DSK.
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2.1.2 CPLD Registers
The 4 CPLD memory-mapped registers allows users to control CPLD functions insoftware. On the C6416T DSK the registers are primarily used to access the LEDs andDIP switches and control the daughter card interface. The registers are mapped intoEMIFB data space at address 0x60000000. They appear as 8-bit registers with asimple asynchronous memory interface. The following table gives a high leveloverview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 4 registers in CPLD.
2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on oroff to allow the user to interact with the DSK. The DIP switches are read by reading thetop 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 1: CPLD Register Definitions
Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 USER_REG USR_SW3R
USR_SW2R
USR_SW1R
USR_SW0R
USR_LED3R/W
0(Off)
USR_LED2R/W
0(Off)
USR_LED1R/W
0(Off)
USR_LED0R/W
0(Off)
1 DC_REG DC_DETR
0 DC_STAT1R
DC_STAT0R
DC_RSTR
0(No reset)
0 DC_CNTL1R/W
0(low)
DC_CNTL0R/W
0(low)
4 VERSION CPLD_VER[3.0]R
0 BOARD VERSION[2.0]R
6 MISC McBSP2_ENR
(MCBSP2enabled)
DSP_PLL_Select4
R1
DSP_PLL_Select3
R1
DSP_PLL_Select2
R1
DSP_PLL_Select1
R1
FLASH_PAGER/W
0(A19=0)
McBSP2ON/OFFBoardR/W
0(Onboard)
McBSP1ON/OFFBoardR/W
0(Onboard)
Table 2: CPLD USER_REG Register
Bit Name R/W Description
7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)
6 USER_SW2 R User DIP Switch 2(1 = Off, 0 = On)
5 USER_SW1 R User DIP Switch 1(1 = Off, 0 = On)
4 USER_SW0 R User DIP Switch 0(1 = Off, 0 = On)
3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)
2 USER_LED2 R/W User-defined LED 2 Control (0 = Off, 1 = On)
1 USER_LED1 R/W User-defined LED 1 Control (0 = Off, 1 = On)
0 USER_LED0 R/W User-defined LED 0 Control (0 = Off, 1 = On)
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2.1.4 DC_REG Register
DC_REG is used to monitor and control the daughter card interface. DC_DET detectsthe presence of a daughter card. DC_STAT and DC_CNTL provide simplecommunications with the daughter card through readable status lines and writablecontrol lines.
The daughter card is released from reset when the DSP is released from reset. DC_RST can be used to put the card back in reset.
2.1.5 VERSION Register
The VERSION register contains two read only fields that indicate the BOARD andCPLD versions. This register will allow your software to differentiate betweenproduction releases of the DSK and account for any variances. This register is notexpected to change often, if at all.
Table 3: DC_REG Register
Bit Name R/W Description
7 DC_DET R Daughter Card Detect (1= Board detected)
6 0 R Always 0
5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)
4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)
3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)
2 0 R Always zero
1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)
0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)
Table 4: Version Register Bit Definitions
Bit # Name R/W Description
7 CPLD_VER3 R Most Significant CPLD Version Bit
6 CPLD_VER2 R CPLD Version Bit
5 CPLD_VER1 R CPLD Version Bit
4 CPLD_VER0 R Least Significant CPLD Version Bit
3 0 R Always 0
2 DSK_VER2 R Most Significant DSK Board Version Bit
1 DSK_VER1 R DSK Board Version Bit
0 DSK_VER0 R Least Significant DSK Board Version Bit
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2.1.6 MISC Register
The MISC register is used to provide software control for miscellaneous boardfunctions. On the C6416T DSK, the MISC register controls how auxiliary signals arebrought out to the daughter-card connectors.
McBSP1 and McBSP2 are usually used as the control and data ports of the on-boardAIC23 codec. The power-on state of these bits (both 0s) represents that configuration. Set MCBSP1SEL or MCBSP2SEL to route the McBSPs to the daughter cardconnectors rather than the codec.
The Flash and CPLD share CE1 which means that the highest address bit (A21) isused to differentiate between the two. In this configuration 512Kbytes of 8-bit Flash arevisible at the beginning of CE1 which matches the chip on the production board. If theFlash is replaced with a 1Mbyte chip, only 512Kbytes of Flash will still be visible butFLASH_PAGE can be used to select between the top and bottom halves. FLASH_PAGE replaces the address bit (A21) that is lost sharing CE1 with the CPLD.
An on-board PLL is used to generate the DSP’s input clock frequency. TheDSPPLL_SELECT bits are read-only versions of the PLL configuration signals.DSPLL_SELECT1-4 (set by configuration switch 3, positions 5-8) allows selection ofone of the following CPU frequencies: 500,600,720,850,1000, and 1200 Mhz. Only the1 Ghz. operation is directly supported in the software that ships with the DSK.
The 6416T’s PCI interface and McBSP2 share some pins. The McBSP2_EN signal isused to disable McBSP2 when the PCI interface is active. McBSP2_EN is generatedon the board when an appropriate daughter card that uses PCI is plugged in, it can beread through this CPLD bit.
The scratch bits are unused. They can be set to any value.
Table 5: MISC Register
Bit Name R/W Description
7 McBSP2_EN R Value of McBSP2_EN from PCI header
6 DSP_PLL SELECT4 R Used to read frequency selection, see table 2
5 DSP_PLL SELECT3 R Used to read frequency selection, see table 2
4 DSP_PLL SELECT2 R Used to read frequency selection, see table 2
3 DSP_PLL SELECT1 R Used to read frequency selection, see table 2
2 FLASH_PAGE R/W Flash address bit 19
1 MCBSP2SEL R/W McBSP2 on/off board (0 = on-board, 1 = off-board)
0 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)
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2-6 TMS320C6416T DSK Module Technical Reference
2.2 AIC23 Codec
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for inputand output of audio signals. The codec samples analog signals on the microphone orline inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples backinto analog signals on the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internalconfiguration registers and one to send and receive digital audio samples. McBSP1 isused as the unidirectional control channel. It should be programmed to send a 16T-bitcontrol word to the AIC23 in SPI format. The top 7 bits of the control word shouldspecify the register to be modified and the lower 9 should contain the register value. The control channel is only used when configuring the codec, it is generally idle whenaudio data is being transmitted,
McBSP2 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The DSK examples generallyuse a 16T-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side. Thepreferred serial format is DSP mode which is designed specifically to operate with theMcBSP ports on TI DSPs.
The codec has a 12MHz system clock. The 12MHz system clock corresponds to USBsample rate mode, named because many USB systems use a 12MHz clock and canuse the same clock for both the codec and USB controller. The internal sample rategenerate subdivides the 12MHz clock to generate common frequencies such as48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATEregister. The figure below shows the codec interface on the C6416T DSK.
Figure 2-1, TMS320C6416T DSK CODEC INTERFACE
MIC IN
LINE IN
LINE OUT
HP OUT
ADC
DAC
McBSP2
DSP Format
0 LEFTINVOL1 RIGHTINVOL2 LEFTHPVOL3 RIGHTHPVOL4 ANAPATH5 DIGPATH6 POWERDOWN7 DIGIF8 SAMPLERATE9 DIGACT15 RESET
Con
trol R
egis
ters
LRCINBCLK
DIN
DOUTLRCOUTFSX2
DX2
CLKXFSR2
CLKR
DR2
CSSCLKSDIN
McBSP1
SPI Format
FSX1
TX1CLKX1
AIC23 Codec
Digital Analog
MIC IN
LINE IN
LINE OUT
HP OUT
Spectrum Digital, Inc
2-7
2.3 Synchronous DRAM
The DSK uses a pair of industry standard 64 megabit SDRAMs in CE0 of EMIFA. Thetwo devices are used in parallel to create a 64-bit wide interface. Total availablememory is 16 megabytes.
The DSK uses a factory setting EMIFA clock at 125 MHz. The integrated SDRAMcontroller is started by configuring the EMIF in software. Timings can be found in theSDRAM data sheet and the DSK help file. When using the SDRAM, note that one rowof the memory array must be refreshed at least every 15.6 microseconds to maintainthe integrity of its contents.
2.4 Flash Memory
The DSK uses a 512Kbyte external Flash as a boot option. It is connected to CE1 ofEMIFB with an 8-bit interface. Flash is a type of memory which does not lose itscontents when the power is turned off. When read it looks like a simple asynchronousread-only memory (ROM). Flash can be erased in large blocks commonly referred toas sectors or pages. Once a block has been erased each word can be programmedonce through a special command sequence. After than the entire block must be erasedagain to change the contents.
The Flash requires 70ns for both reads and writes. The general settings used with theDSK use 8 cycles for both read and write strobes (80ns) to leave a little extra margin.
2.5 LEDs and DIP Switches
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) thatprovide the user a simple form of input/output. Both are accessed through the CPLDUSER_REG register.
Spectrum Digital, Inc
2-8 TMS320C6416T DSK Module Technical Reference
2.6 Daughter Card Interface
The DSK provides three expansion connectors that can be used to accept plug-indaughter cards. The daughter card allows users to build on their DSK platform toextend its capabilities and provide customer and application specific I/O. Theexpansion connectors are for memory, peripherals, and the Host Port Interface (HPI)
The memory connector provides access to the DSP’s asynchronous EMIF signals tointerface with memories and memory mapped devices. It supports byte addressing on32 bit boundaries. The peripheral connector brings out the DSP’s peripheral signalslike McBSPs, timers, and clocks. Both connectors provide power and ground to thedaughter card.
The HPI is a high speed interface that can be used to allow multiple DSPs tocommunicate and cooperate on a given task. The HPI connector brings out the HPIspecific control signals as well as McBSP2.
Most of the expansion connector signals are buffered so that the daughter card cannotdirectly influence the operation of the DSK board. The use of TI low voltage, 5V tolerantbuffers, and CBT interface devices allows the use of either +5V or +3.3V devices to beused on the daughter card.
Other than the buffering, most daughter card signals are not modified on the board. However, a few daughter card specific control signals like DC_RESET andDC_DET exist and are accessible through the CPLD DC_REG register. The DSKalso multiplexes the McBSP1 and McBSP2 of on-board or external use. This functionis controlled through the CPLD MISC register.
2.7 DSP and EMIFA Clock Generation
The C6416T DSK incorporates a multiple clocking input to the DSP via a selectorswitch, CPLD, PLL, and multiple oscillators. The oscillators are input to the CPLD andSW3-5 to SW3-8 are also input to the CPLD. Depending on the value of the selectorswitch the CPLD outputs the appropriate “codes” to the ICS512 PLL devices andappropriate frequency to generate the frequencies in table 2. The same technique isused for the EMIFA clock. This allows the DSK to support 500,600,720, 850, 1000, and1200 megahertz CPU clocks. However, the default configuration is 1 gigahertz and thesoftware shipped with the DSK assumes the default configuration
3-1
Chapter 3
Physical Description
This chapter describes the physical layout of the TMS320C6416T DSKand its connectors.
Topic Page
3.1 Board Layout 3-23.2 Connector Index 3-33.3 Expansion Connectors 3-33.3.1 J4, Memory Expansion Connector 3-43.3.2 J3, Peripheral Expansion Connector 3-53.3.3 J1, HPI Expansion Connector 3-63.4 Audio Connectors 3-73.4.1 J301, Microphone Connector 3-73.4.2 J303, Audio Line In Connector 3-73.4.3 J304, Audio Line Out Connector 3-83.4.4 J302, Headphone Connector 3-83.5 Power Connectors 3-93.5.1 J5, +5 Volt Connector 3-93.5.2 J6, Optional Power Connector 3-93.6 Miscellaneous Connectors 3-103.6.1 J201, USB Connector 3-103.6.2 J8, External JTAG Connector 3-103.6.3 JP3, PLD Programming Connector 3-113.7 System LEDs 3-113.8 Reset Switch 3-11
Spectrum Digital, Inc
3-2 TMS320C6416T DSK Module Technical Reference
3.1 Board Layout
The C6416T DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which ispowered by an external +5 volt only power supply. Figure 3-1 shows the layout of the C6416T DSK.
Figure 3-1, TMS320C6416T DSK
J4
J5J6 JP3
J302
J8SW1 SW2J201 D7-10
J304J303J301 J3 J1 J2
Spectrum Digital, Inc
3-3
3.2 Connector Index
The TMS320C6416T DSK has many connectors which provide the user accessto the various signals on the DSK.
Note: “*” Not populated
3.3 Expansion Connectors
The TMS320C6416T DSK supports three expansion connectors that follow the TexasInstruments interconnection guidelines. The expansion connector pinouts aredescribed in the following three sections.
The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profileconnectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectorsare designed for high speed interconnections because they have low propagationdelay, capacitance, and cross talk. The connectors present a small foot print on theDSK. Each connector includes multiple ground, +5V, and +3.3V power signals so thatthe daughter card can obtain power directly from the DSK. The peripheral expansionconnector additionally provides both +12V and -12V to the daughter card. Therecommended mating connector, whose part number is TFM-140-32-S-D-LC, is asurface mount connector that provides a 0.465” mated height.
Note: I is on an Input pin O is on an Output pin Z is on a High Impedance pin
Table 1: TMS320C6416T DSK Connectors
Connector # Pins Function
J4 80 Memory
J3 80 Peripheral
J1 80 HPI
J301 3 Microphone
J303 3 Line In
J304 3 Line Out
J303 3 Headphone
J5 2 +5 Volt
J6 * 4 Optional Power Connector
J8 14 External JTAG
J201 5 USB Port
JP3 10 CPLD Programming
SW3 8 DSP Configuration Switch
Spectrum Digital, Inc
3-4 TMS320C6416T DSK Module Technical Reference
3.3.1 J4, Memory Expansion Connector
Table 2: J4, Memory Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin
3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20
5 AEA19 O EMIF address pin 19 6 AEA18 O EMIF address pin 18
7 AEA17 O EMIF address pin 17 8 AEA16 O EMIF address pin 16
9 AEA15 O EMIF address pin 15 10 AEA14 O EMIF address pin 14
11 GND Vss System ground 12 GND Vss System ground
13 AEA13 O EMIF address pin 13 14 AEA12 O EMIF address pin 12
15 AEA11 O EMIF address pin 11 16 AEA10 O EMIF address pin 10
17 AEA9 O EMIF address pin 9 18 AEA8 O EMIF address pin 8
19 AEA7 O EMIF address pin 7 20 AEA6 O EMIF address pin 6
21 5V Vcc 5V voltage supply pin 22 5V Vcc 5V voltage supply pin
23 AEA5 O EMIF address pin 5 24 AEA4 O EMIF address pin 4
25 AEA3 O EMIF address pin 3 26 AEA2 O EMIF address pin 2
27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2
29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0
31 GND Vss System ground 32 GND Vss System ground
33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30
35 AED29 I/O EMIF data pin 29 36 AED28 I/O EMIF data pin 28
37 AED27 I/O EMIF data pin 27 38 AED26 I/O EMIF data pin 26
39 AED25 I/O EMIF data pin 25 40 AED24 I/O EMIF data pin 24
41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
43 AED23 I/O EMIF data pin 23 44 AED22 I/O EMIF data pin 22
45 AED21 I/O EMIF data pin 21 46 AED20 I/O EMIF data pin 20
47 AED19 I/O EMIF data pin 19 48 AED18 I/O EMIF data pin 18
49 AED17 I/O EMIF data pin 17 50 AED16 I/O EMIF data pin 16
51 GND Vss System ground 52 GND Vss System ground
53 AED15 I/O EMIF data pin 15 54 AED14 I/O EMIF data pin 14
55 AED13 I/O EMIF data pin 13 56 AED12 I/O EMIF data pin 12
57 AED11 I/O EMIF data pin 11 58 AED10 I/O EMIF data pin 10
59 AED9 I/O EMIF data pin 9 60 AED8 I/O EMIF data pin 8
61 GND Vss System ground 62 GND Vss System ground
63 AED7 I/O EMIF data pin 7 64 AED6 I/O EMIF data pin 6
65 AED5 I/O EMIF data pin 5 66 AED4 I/O EMIF data pin 4
67 AED3 I/O EMIF data pin 3 68 AED2 I/O EMIF data pin 2
69 AED1 I/O EMIF data pin 1 70 AED0 I/O EMIF data pin 0
71 GND Vss System ground 72 GND Vss System ground
73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable
75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready
77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2
79 GND Vss System ground 80 GND Vss System ground
Spectrum Digital, Inc
3-5
3.3.2 J3, Peripheral Expansion Connector
Table 3: J3, Peripheral Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin
3 GND Vss System ground 4 GND Vss System ground
5 5V Vcc 5V voltage supply pin 6 5V Vcc 5V voltage supply pin
7 GND Vss System ground 8 GND Vss System ground
9 5V Vcc 5V voltage supply pin 10 5V Vcc 5V voltage supply pin
11 N/C - No connect 12 N/C - No connect
13 N/C - No connect 14 N/C - No connect
15 N/C - No connect 16 N/C - No connect
17 N/C - No connect 18 N/C - No connect
19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin
21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source
23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data
25 GND Vss System ground 26 GND Vss System ground
27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect
29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data
31 GND Vss System ground 32 GND Vss System ground
33 CLKX2 I/O McBSP2 transmit clock 34 CLKS2 I McBSP2 clock source
35 FSX2 I/O McBSP2 transmit frame sync 36 DX2 O McBSP2 transmit data
37 GND Vss System ground 38 GND Vss System ground
39 CLKR2 I/O McBSP2 receive clock 40 N/C - No connect
41 FSR2 I/O McBSP2 receive frame sync 42 DR2 I McBSP2 receive data
43 GND Vss System ground 44 GND Vss System ground
45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input
47 N/C - No connect 48 EXT_INT5 I External interrupt 5
49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input
51 GND Vss System ground 52 GND Vss System ground
53 EXT_INT4 I External interrupt 4 54 N/C - No connect
55 N/C - No connect 56 N/C - No connect
57 N/C - No connect 58 N/C - No connect
59 RESET O System reset 60 N/C - No connect
61 GND Vss System ground 62 GND Vss System ground
63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control
65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status
67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7
69 ACE3# O Chip enable 3 70 N/C - No connect
71 N/C - No connect 72 N/C - No connect
73 N/C - No connect 74 N/C - No connect
75 DC_DET# Vss System ground 76 GND Vss System ground
77 GND Vss System ground 78 ECL KOUT O EMIF Clock
79 GND Vss System ground 80 GND Vss System ground
Spectrum Digital, Inc
3-6 TMS320C6416T DSK Module Technical Reference
3.3.3 J1, HPI Expansion Connector
Table 4: J1, HPI Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description
1 PCI_EN I PCI enable 2 BSP2_EN I MCBSP2_EN
3 GND Vss System ground 4 HPI_RS# I HPI reset
5 XSP_CS O PCI serial 6 BEA13 I PCI EEPROM auto-init
7 GND Vss System ground 8 GND Vss System ground
9 AD1 I/O PCI address/data 1 10 PCBE0# I/O PCI command/byte ena 0
11 AD3 I/O PCI address/data 3 12 AD0 I/O PCI address/data 0
13 AD5 I/O PCI address/data 5 14 AD2 I/O PCI address/data 2
15 AD7 I/O PCI address/data 7 16 AD4 I/O PCI address/data 4
17 GND System ground 18 AD6 I/O PCI address/data 6
19 AD8 I/O PCI address/data 8 20 GND Vss System ground
21 AD10 I/O PCI address/data 10 22 AD9 I/O PCI address/data 9
23 AD12 I/O PCI address/data 12 24 AD11 I/O PCI address/data 11
25 AD14 I/O PCI address/data 14 26 AD13 I/O PCI address/data 13
27 GND Vss System ground 28 AD15 I/O PCI address/data 15
29 PCBE1# I/O PCI command/byte ena 1 30 GND Vss System ground
31 GND Vss System ground 32 PPAR I/O PCI parity
33 PSERR# I/O PCI system error 34 GND Vss System ground
35 GND Vss System ground 36 PSTOP# I/O PCI stop
37 PPERR# I/O PCI parity error 38 GND Vss System ground
39 GND Vss System ground 40 PTRDY# I/O PCI target ready
41 PDEVSEL# I/O PCI device select 42 GND Vss System ground
43 GND Vss System ground 44 PFRAME# I/O PCI Frame
45 PIRDY# I/O PCI initiator ready 46 GND Vss System ground
47 GND Vss System ground 48 AD16 I/O PCI address/data 16
49 PCBE2# I/O PCI command/byte ena 2 50 AD18 I/O PCI address/data 18
51 AD17 I/O PCI address/data 17 52 AD20 I/O PCI address/data 20
53 AD19 I/O PCI address/data 19 54 AD22 I/O PCI address/data 22
55 AD21 I/O PCI address/data 21 56 GND Vss System ground
57 AD23 I/O PCI address/data 23 58 PIDSEL I PCI init device select
59 PCBE3# I/O PCI command/byte ena 3 60 AD24 I/O PCI address/data 24
61 GND Vss System ground 62 AD26 I/O PCI address/data 26
63 AD25 I/O PCI address/data 25 64 AD28 I/O PCI address/data 28
65 AD27 I/O PCI address/data 27 66 AD30 I/O PCI address/data 30
67 AD29 I/O PCI address/data 29 68 PGNT# I PCI bus grant
69 AD31 I/O PCI address/data 31 70 GND Vss System ground
71 GND Vss System ground 72 PRST# I PCI reset
73 PREQ# O PCI bus request 74 GND Vss System ground
75 GND Vss System ground 76 PINTA# O PCI interrupt A
77 PCLK I PCI Clock 78 GND Vss System ground
79 GND Vss System ground 80 N/C - No connect
Spectrum Digital, Inc
3-7
3.4 Audio Connectors
The C6416T DSK has 4 audio connectors. They are described in the followingsections.
3.4.1 J301, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it ismonaural. The signals on the plug are shown in the figure below.
3.4.2 J303, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
Microphone In
Ground
Figure 3-2, Microphone Stereo Jack
Microphone Bias
Left Line In
Ground
Figure 3-3, Audio Line In Stereo Jack
Right Line In
Spectrum Digital, Inc
3-8 TMS320C6416T DSK Module Technical Reference
3.4.3 J304, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. Thesignals on the mating plug are shown in the figure below.
3.4.4 J303, Headphone Connector
Connector J4 is a headphone/speaker jack. It can drive standard headphones or a highimpedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Left Line Out
Ground
Figure 3-4, Audio Line Out Stereo Jack
Right Line Out
Left Headphone
Ground
Figure 3-5, Headphone Jack
Right Headphone
Spectrum Digital, Inc
3-9
3.5 Power Connectors
The C6416T DSK has 2 power connectors. They are described in the followingsections.
3.5.1 J5, +5 Volt Connector
Power (+5 volts) is brought onto the TMS320C6416T DSK via connector J5. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. TheA diagram of J5 is shown below.
3.5.2 J6, Optional Power Connector
Connector J6 is an optional power connector. It will operate with the standard personalcomputer power supply. To populate this connector use a Molex #15109-0410 orTyco #174552-1. The table below shows the voltages on the respective pins.
Table 5: J6, Optional Power Connector
Pin # Voltage Level
1 +12 Volts
2 -12 Volts
3 Ground
4 +5 Volts
PC Board
J5+5V
Ground
Front ViewFigure 3-6, TMS320C6416T DSK Power Connector
WARNING !Do not plug into J5 and J6 at the same time.
Spectrum Digital, Inc
3-10 TMS320C6416T DSK Module Technical Reference
3.6 Miscellaneous Connectors
The C6416T DSK has 3 additional connectors to aid the user in developing with thisproduct. They are described in the following sections.
3.6.1 J201, USB Connector
Connector J201 provides a Universal Serial Bus (USB) Interface to the embeddedJTAG emulation logic on the DSK. This allows for code development and debugwithout the use of an external emulator. The signals on this connector are shown in thebelow.
3.6.2 J8, External JTAG Connector
The TMS320C6416T DSK is supplied with a 14 pin header interface, J8. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.The pinout for the connector is shown figure 3-6 below.
Table 6: J201, USB Connector
Pin # USB Signal Name
1 USBVdd
2 D+
3 D-
4 USB Vss
5 Shield
6 Shield
1 23 4
5 67 89 1011 1213 14
TMSTDI
PD (+3.3V)TDO
TCK-RET
TCKEMU0
TRST-GNDno pin (key)GNDGND
GNDEMU1
Header Dimensions
Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
Figure 3-7, JTAG INTERFACE
Spectrum Digital, Inc
3-11
3.6.3 JP3, PLD Programming Connector
This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for theprogramming of the CPLD. This connector is not intended to be used outside thefactory.
3.7 System LEDs
TheTMS320C6416T DSK has four system light emitting diodes (LEDs). TheseLEDs indicate various conditions on the DSK. These function of each LED is shown inthe table below.
3.8 Reset Switch
There are three resets on the TMS320C6416T DSK. The first reset is the power onreset. This circuit waits until power is within the specified range before releasing thepower on reset pin to the TMS320C6416T.
External sources which control the reset are push button SW2, and the on boardembedded USB JTAG emulator.
Table 7: System LEDs
Reference Designator Color Function On Signal
State
D4 Green USB Emulation in use. When External JTAG Emulator is used this LED is off.
1
D3 Green +5 Volt present 1
D6 Orange RESET Active 1
DS201 Green USB Active, Blinks during USB data transfer 1
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3-12 TMS320C6416T DSK Module Technical Reference
A-1
Appendix A
Schematics
This appendix contains the schematics for the TMS320C6416T DSK.Board components with designators between 200 and 299 (e.g. DS201,R211) are part of Spectrum Digital’s embedded JTAG emulator and are notincluded in these schematics.
Spectrum Digital, Inc
A-2 TMS320C6416T DSK Module Technical Reference
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A
NO
V 0
1,20
04
ENGR
CHK
REV
QA
NO
V 0
1,20
04
9
15
R.R
.P.
5
MFG
A
6
NO
V 0
1,20
04A
DATE
810
A
13
SH
RLSE
DATE
DATE
14
A
R.R
.P.
REV
A
11
A
DATE
34
NEXTASSY
5080
32A
TMS3
20C
6416
TDSK
B
115
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Spectrum Digital, Inc
A-3
CP
LD
PU
LLU
P/D
OW
N T
O K
EEP
LO
GIC
IN R
ES
ET
WH
EN
TH
E C
PLD
IS N
OT
PR
OG
RA
MM
ED
.
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
215
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
US
B_D
SP_R
ST#
DS
P_R
ST#
DC
_EM
IFA
_OE
#
BR
D_R
ST#
FLA
SH_P
AG
E
US
ER
_LE
D1
US
ER
_LE
D0
US
ER
_LE
D3
US
ER
_LE
D2
ISR
_TD
O
ISR
_TC
KIS
R_T
MS
ISR
_TC
KIS
R_T
MS
ISR
_TD
I
ISR
_TD
I
ISR
_TD
O
PU
SH
B_R
S
TBE
A1
TBE
A3
TBE
A2
DS
P_R
Sn_L
ED
DS
P_P
LL_S
1
CP
LD_M
CB
SP1_
MU
X
CP
LD_M
CB
SP2_
MU
X
DC
_STA
T0
DC
_STA
T1
TBE
D7
TBE
D6
TBE
D5
TBE
D4
TBE
D3
TBE
D2
TBE
D1
TBE
D0
TBED
4
TBED
1
TBED
5
TBED
0
TBED
3
TBED
6
TBED
7
TBED
2TB
EA
1
TBE
A3
TBE
A2
PWB
_RE
V2
PWB
_RE
V1
DS
P_P
LL_S
1
DS
P_P
LL_S
0
DS
P_P
LL_S
0
SPA
RE
_SE
LEC
T
SP
ARE
_EN
ABLE
SP
AR
E_E
NAB
LE
PWB
_RE
V0
SP
ARE
_SE
LEC
T
SV
S_R
ST#
(11,
17)
HPI
_RE
SE
T#(8
)
USB
_DS
P_R
ST#
(17)
TAC
E3#
(5,9
)
TAS
DC
AS
#(5
,9)
TAS
DR
AS
#(5
,9)
TAC
E2#
(5,9
)
TAS
DW
E#
(5,9
)
TBEA
[3..1
](6
)
DC
_STA
T0(1
0)
DC
_STA
T1(1
0)
DC
_CN
TL0
(10)
DC
_CN
TL1
(10)
DC
_EM
IFA
_OE#
(9)
DC
_EM
IFA
_DIR
(9)
DC
_CN
TL_O
E#
(9)
DC
_RS
T#(1
0)
DC
_DE
T(1
0)
CPL
D_M
CB
SP
2_M
UX
(7)
CPL
D_M
CB
SP
1_M
UX
(8)
MC
BS
P2_
EN
(7,8
)
BR
D_R
ST#
(6)
DS
P_R
ST#
(4)FL
AS
H_P
AG
E(6
)
CO
DE
C_C
LK(1
4,15
)
PU
SH
B_R
S(3
)
TBE
D[7
..0]
(6)
TBC
E0#
(6)
USE
R_S
W0
(3)
US
ER
_SW
1(3
)U
SE
R_S
W2
(3)
US
ER
_SW
3(3
)
TBA
WE
#(6
)
TBA
RE#
(6)
PW
B_R
EV2
(3)
PW
B_R
EV1
(3)
PW
B_R
EV0
(3)
CLK
MO
DE
0(4
)
CLK
MO
DE
1(4
)
DSP
PLL
_S0
(4)
DSP
PLL
_S1
(4)
SP
ARE
_EN
AB
LE(4
)
USE
R_L
ED
2(3
)
US
ER
_LE
D3
(3)
US
ER
_LE
D1
(3)
US
ER
_LE
D0
(3) DS
P_R
Sn_L
ED
(3)
SP
AR
E_S
ELE
CT
(6)
DS
P_P
LL_C
LK(4
)
EMIF
_PLL
_CLK
(4)
EM
IF_P
LL_S
0(4
)E
MIF
_PLL
_S1
(4)
DS
P_P
LL_S
ELE
CT4
(6)
DS
P_P
LL_S
ELE
CT3
(6)
DS
P_P
LL_S
ELE
CT1
(6)
DS
P_P
LL_S
ELE
CT2
(6)
OP
T_C
LK1
(3)
OP
T_C
LK2
(3)
TBA
OE
#(6
)
3.3V
DG
ND
DG
ND
3.3V
3.3V
DG
ND
DG
ND
3.3V
DG
ND C
68
0.1
C69
0.1
C70
0.1
C39
0.1
C40
0.1
C38
0.1
C71
0.1
C72
0.1
R56
10K
R39
1K
R22
1K
R35
10K
R24
1KU
12
EPM
3128
ATC
100
1 2
3
4
5 6 7 8 9 10
11
12 13 14
15
16 17
18
19 20 21 22 23 24 25
26
27 28 29 30 31 32
33
3435 36 37
38
39
40 41 4243
44 45 46 47 48 49 50
51
52
53
54 55 56 57 58
59
60 61 6263 64
65
66
67 68 69 70 71 72
73
74
75 76 77
78
79 80 81
82
83 84 85
86
8788 89 90
91
92 93 94
95
96 97 98 99 100
PIN
1P
IN2
VCCIO1
TDI
PIN
5P
IN6
PIN
7P
IN8
PIN
9P
IN10
GNDIO1
PIN
12P
IN13
PIN
14
TMS
PIN
16P
IN17
VCCIO2
PIN
19P
IN20
PIN
21P
IN22
PIN
23P
IN24
PIN
25
GNDIO2
PIN
26P
IN28
PIN
29
PIN
30P
IN31
PIN
32
GNDIO3
VCCIO3P
IN35
PIN
36P
IN37
GNDINT1
VCCINT1
PIN
40P
IN41
PIN
42GNDIO4
PIN
44P
IN45
PIN
46P
IN47
PIN
48P
IN49
PIN
50
VCCIO4
PIN
52
GNDIO5
PIN
54PI
N55
PIN
56PI
N57
PIN
58
GNDIO6
PIN
60PI
N61
TCK
PIN
63PI
N64
GNDIO7
VCCIO5
PIN
67PI
N68
PIN
69
PIN
70PI
N71
PIN
72
TDO
GNDIO8
PIN
75PI
N76
PIN
77
GNDIO9
PIN
79
PIN
80PI
N81
VCCIO6
PIN
83PI
N84
PIN
85
GNDINT2
IN/G
CLK
1
IN/O
E1IN
/GC
LR
IN/O
E2/G
CLK
2VCCINT2
PIN
92PI
N93
PIN
94
GNDIO10
PIN
96PI
N97
PIN
98PI
N99
PIN
100
JP3
HEA
DE
R 5
X2
12
34
56
78
910
RN
19A
10K
RN
19C
10K
RN
19B
10K
R10
110
0
R23
10K
R40
10K
R10
010
0
TP10
TP
R98
10K
R97
10K
TP15
TPTP20
TP TP19
TP TP16
TP
Spectrum Digital, Inc
A-4 TMS320C6416T DSK Module Technical Reference
RE
SE
T
PAD
DLE
SW
ITC
H
500
MH
z
600
MH
z
720
MH
z
850
MH
z
1000
MH
z
1200
MH
z
CPU
FREQ
EMIF
FREQ
PLL
IN-C
LKCP
UM
ULT
PLL
MU
LTPL
LCO
DE
12 M
Hz
12 M
Hz
20 20
2.5
3 5
20
12 M
Hz
12.5
MH
z
12.5
MH
z
20 20
2 4
8 M
Hz
205.
33
PLL
IN-C
LKPL
LM
ULT
PLL
CODE
100
MH
z
100
MH
z
125
MH
z
125
MH
z
125
MH
z
125
MH
z
25 M
Hz
25 M
Hz
25 M
Hz
25 M
Hz
25 M
Hz
25 M
Hz
55554 4
Z Z
Z 0
1 Z
0 Z
0 0
0 1
0 0
0 0
0 1
0 1
0 1
0 1
MU
LTIP
LIER
4X 5.33
X
5X 2.5X
2X 3.33
X
6X 3X 8X
Z
0
0
S1
0 1Z
11
0
Z
Z
Z
1
0
S0
1
10 ZIC
S51
2 FU
NC
TIO
N T
ABL
E
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
DU
E T
O P
RE
VIO
US
641
6 D
SK
SS
TAR
TIN
G B
OAR
D R
EV
ISIO
NFO
R 6
416T
IS 1
01bi
nary
SW3
-5SW
3 -6
SW3
-7SW
3 -8
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
ON
ON
5080
32A
TMS3
20C
6416
T D
SK
B
315
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
US
ER_L
ED
1U
SER
_LE
D0
US
ER_L
ED
3U
SER
_LE
D2
DS
P_R
Sn_
LED
PW
B_R
EV2
PW
B_R
EV1
PW
B_R
EV0
PU
SH
B_R
S(2
)
US
ER
_SW
3(2
)
US
ER
_SW
1(2
)U
SE
R_S
W2
(2)
US
ER
_SW
0(2
)
PW
B_R
EV2
(2)
PW
B_R
EV1
(2)
PW
B_R
EV0
(2)
US
ER
_LE
D2
(2)
US
ER
_LE
D0
(2)
US
ER
_LE
D1
(2)
US
ER
_LE
D3
(2)DS
P_R
Sn_
LED
(2)
OP
T_C
LK2
(2)
OPT
_CLK
1(2
)
DG
ND
3.3V
DG
ND
DG
ND 3.3V
DG
ND
3.3V
DG
ND
3.3V
3.3V
3.3V
DG
ND
DG
ND
DG
ND
DG
ND
D11 M
MB
D41
48
13
R81
150
R82
150
R79
150
R78
150
D10
GR
EE
N
D9
GR
EEN
D8
GR
EEN
D7
GR
EEN
D6
YE
LLO
W
R80
150
U27
25 M
Hz
1 4
8 5
OFF
n
GN
D
VC
C
CLK
L6
BLM
21P
221S
N
R12
010
0
C12
8
0.1u
F
R33
1K R36
NU
R37
1KR
54N
U
R34
NU
R53
1K
U8 SN
74A
HC
1G14
3
4
5
2
C12
9
0.1u
F
R12
110
0
U28
8 M
Hz
1 4
8 5
OFF
n
GN
D
VC
C
CLK
L7
BLM
21P2
21S
N
R84
10K
SW
2
PU
SH
BU
TTO
N
1 234
C11
90.
1uF
R83
33
SW
1
SW
DIP
-4/S
M
1234
8765
RN
19G
10K
RN
19F
10K
RN
19E
10K
RN
19D
10K
Spectrum Digital, Inc
A-5
CLK
MO
DE[
1:0]
: Cor
e C
LKIN
mul
tiple
s 0
0 =
x1 0
1 =
x6 1
0 =
x12
11
= x2
0 ( D
efau
lt )
THES
E IN
PU
TS A
RE
DR
IVE
N B
YTH
E C
PLD
Pla
ce a
ll P
LL e
xter
nal c
ompo
nent
s as
clo
seto
the
DSP
. All
PLL
ext
erna
l com
pone
nts
mus
t be
on a
sin
gle
side
of t
he b
oard
.
Max
imiz
e th
e di
stan
ce b
etw
een
switc
hing
sig
nals
an
d th
e P
LL e
xter
nal c
ompo
nent
s.
OPT
ION
AL
PLA
CE
CO
MP
ON
ENTS
ON
BA
CK
SID
EO
F P
WB
AS
CLO
SE
TO
U10
PIN
H25
AS
PO
SSIB
LE.
3-P
IN S
MT
JUM
PER
S A
CC
EP
T 60
3R
ESIS
TOR
S.
33 O
HM
A TO
B (
DEF
AU
LT)
S1
S0
MU
LTIP
LIER
4X 5.33
X
5X 2.5X
2X 3.33
X
6X 3X 8X
00 M
0 01
M0
MM
M1
10
1M
11
MU
ST
DR
IVE
1/0/
Z, Z
FO
RO
PE
NM
US
T D
RIV
E 1
/0/Z
, Z F
OR
OP
EN
NO
T U
SE
D
NO
T U
SE
DN
OT
US
ED
NO
T U
SED
NO
T U
SE
D
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
SEE
OP
TIO
NS
PAG
E F
OR
INPU
T C
LOC
K IN
FOR
MA
TIO
N
5080
32A
TMS3
20C
6416
T D
SK
B
415
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DS
P_C
OR
E_C
LK
EIN
T4E
INT5
EIN
T6E
INT7
TIN
P0
TIN
P1
TOU
T0TO
UT1
AEC
LKIN
CLK
MO
DE
1C
LKM
OD
E0
DS
P_T
DO
(13)
DS
P_T
RS
T#(1
3)
DS
P_T
MS
(13)
DSP
_TD
I(1
3)
DS
P_T
CK
(13)
DS
P_E
MU
0(1
3)D
SP
_EM
U1
(13)
DS
P_R
ST#
(2)
DC
_EIN
T4(1
0)
DC
_EIN
T6(1
0)D
C_E
INT7
(10)
DC
_TIN
P0
(10)
DC
_TIN
P1
(10)
DC
_EIN
T5(1
0)
DC
_TO
UT0
(10)
DC
_TO
UT1
(10)
DS
P_E
MU
9(1
3)D
SP
_EM
U8
(13)
DS
P_E
MU
4(1
3)
DS
P_E
MU
6(1
3)D
SP
_EM
U5
(13)
DS
P_E
MU
2(1
3)D
SP
_EM
U3
(13)
DS
P_E
MU
7(1
3)
DS
P_E
MU
11(1
3)D
SP
_EM
U10
(13)
XD
S_4
.1V
(7,1
3)
DSP
IO_3
.3V
(11,
12)
CLK
MO
DE0
(2)
CLK
MO
DE1
(2)
DS
PP
LL_S
0(2
)
SP
AR
E_E
NAB
LE(2
)
DS
PP
LL_S
1(2
)
DS
P_P
LL_C
LK(2
)
EM
IF_P
LL_C
LK(2
)
EM
IF_P
LL_S
0(2
)
EM
IF_P
LL_S
1(2
)
DG
ND
3.3V
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
3.3V
3.3V
DG
ND
DG
ND
3.3V
DG
ND
3.3V
DG
ND
3.3V
DG
ND
TP27
TP29
C40
0N
U
R29
1KR
301K R
27N
UR
28N
U
C40
1
NU
C92
0.1
TP28
TP5
E1EXC
CE
T103
UE
MI F
ILTE
R
13
2
IO
GND
+C
T10
10JP
401
JPS
MT
1
2
3A
B
C
JP40
0JP
SMT
1
2
3A B C
C12
1
0.1
C11
30.
01
R77
360
C40
2
.01U
FJP
402
JPS
MT
1
2
3A
B
C
JP50
2
JPS
MT
1
2
3A
B
C
C22
NO
-PO
P
Y1 N
O-P
OP
U40
0
ICS
512
1 2 3 45678
X1/
CLK
VD
D
GN
D
RE
FC
LKS0
S1
X2
C50
0
NO
-PO
P
C50
1
NO
-PO
PJP
500
JPS
MT
1
2
3A B C
JP50
1JP
SM
T
1
2
3A
B
C
Y50
0
NO
-PO
P
U50
0
ICS
512
1 2 3 45678
X1/
CLK
VD
D
GN
D
RE
FC
LKS0
S1
X2
C11
40.
1
R17
NO
-PO
P
L5 Ferr
ite C
hip
R50
33
U21
SN
74C
BTD
3384
PW
1 133 4 7 8 11
2 5 6 9 10
14 17 18 21 22
24 1215 16 19 20 23
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1B1
1B2
1B3
1B4
1B5
2A1
2A2
2A3
2A4
2A5
Vcc
GN
D
2B1
2B2
2B3
2B4
2B5
R51
NU
TP6
TP8
TP7
U10
E
TMS
320C
6416
TGLZ
AF1
5A
C15
AE
16A
D16
AC
16A
E17
AD
17A
F17
AC
17A
E18
AE
19A
D18
AC
18
D6
B5
A4
AF6
AE
6A
D6
AC
6
H4
H2
G1J6
AC
7
B4
AF5
AE5
AD
5A
F4 C6
A5
C5
AF1
8AB
16A
F16
AB15
H25 A1
1
EM
U0
EM
U1
EM
U2
EM
U3
EM
U4
EM
U5
EM
U6
EM
U7
EM
U8
EM
U9
TDO
EM
U10
EM
U11
TOU
T0TO
UT1
TOU
T2
GP0
0G
P01_
CLK
OU
T4G
P02_
CLK
OU
T6G
P03
CLK
IN
CLK
MO
DE
0C
LKM
OD
E1
PLL
V
RE
SE
T
NM
IE
XTI
NT4
_GP
04E
XTI
NT5
_GP
05E
XTI
NT6
_GP
06E
XTI
NT7
_GP
07
TIN
P0TI
NP1
TIN
P2
TDI
TMS
TCLK
TRS
T
AE
CLK
INB
EC
LKIN
Spectrum Digital, Inc
A-6 TMS320C6416T DSK Module Technical Reference
EM
IFA
& S
DR
AM
NE
AR
DS
PN
EA
R D
SP
NEA
R S
DR
AM
NEA
R S
DR
AM
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
515
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
TAED
34
TAED
51
TAED
48
TAED
45
TAED
42
TAED
54
TAED
46
TAED
57TA
ED56
TAED
37
TAED
43
TAED61
TAED
55
TAED32TA
ED44
TAED
61
TAED
33
TAED
53
TAED58
TAED
36
TAED
49
TAED
39
TAED55
TAED47
TAED
62
TAED
50
TAED
32
TAED
58
TAED
38
TAED
40
TAED
47
TAED62
TAED
60
TAED
52
TAED
63
TAED60
TAED53
TAED
41
TAED50TAED51
TAED
59
TAED
35
TAED38
TABE
3#TA
BE2#
TABE
7#TA
BE6#
TABE
0#
TABE
5#TA
BE4#
TABE
1#
TAB
E4#
TAB
E5#
TAB
E7#
TAB
E6#
TAC
E2#
TAC
E0#
TAC
E3# TA
SDC
AS
#
TAEC
LKO
UT1
TASD
CK
E
TAED9TAED10
TAED31
TAED4
TAE
A12
TAE
D23
TAE
D22
TAE
A7
TAED17
TAED14
TAED0
TAE
A14
TAE
A8
TAE
A16
TAE
A6
TAE
A13
TAE
A4
TAE
D26
TAE
D21
TAE
D20
TAE
D11
TAE
D9
TAE
D7
TAED15
TAE
A12
TAE
A12
TAE
D4
TAED23TAED22
TAB
E2#
TAE
A4
TAE
D31
TAE
D28
TAE
D27
TAE
A7
TAED1
TAED7
TAE
A5
TAE
D29
TAE
D18
TAE
D3
TAE
A6
TAED16
TAED27TAED26
TAE
A3
TAE
A9
TAE
D13
TAE
D5
TAED12
TAB
E3#
TAB
E1#
TAE
D24
TAE
D1
TAE
A11
TAED28
TAE
D19
TAE
D2
TAE
A9
TAED18
TAED13
TAE
A13
TAE
D15
TAE
D8
TAED8
TAE
A5
TAED11
TAE
A16
TAE
A11
TAE
D17
TAE
D25
TAE
D10
TAED29
TAE
A9
TAE
A14
TAED24
TAED2
TAED25
TAE
A14
TAE
A15
TAE
A8
TAE
A11
TAE
D30
TAE
D16
TAE
A15
TAE
A10
TAED21
TAED6
TAE
A8
TAE
A3
TAE
A7
TAE
A13
TAB
E0#
TAE
D6
TAED20
TAE
A6
TAED5
TAED30
TAE
A5
TAED19
TAE
A10
TAE
D12
TAED3
TAE
A4
TAE
A10
TAE
A16
TAE
A15
TAE
A3
TAE
D14
TAE
D0
TAS
DR
AS#
TAS
DC
AS#
TAS
DW
E#
TAC
E0#
TAS
DW
E#
TAS
DR
AS#
TAC
E0#
TAS
DC
AS#
TAE
CLK
OU
T1TA
EC
LKO
UT1
TAS
DC
KE
TAS
DC
KE
TAE
A21
TAE
A17
TAE
A20
TAE
A22
TAE
A19
TAE
A18
TAA
RD
Y
AEA
8
AEA
20
AB
E1#
AED43
AED36A
EA14
AEA
17
AB
E6#
AED39
AED47
AA
RD
Y
AEA
13
AS
DW
E#
AED58
AED46
AEA
12
AEA
15
AC
E2#
AED40
AEA
3
AEA
11
AEA
18
AB
E5#
AB
E0#
AB
E2#
AED52
AED44A
EA5
AED59
AED34
AS
DC
KE
AED51
AED32
AEA
9
AEA
21
AE
CLK
OU
T2
AB
E4#
AED45
AED53
AED41
AEA
4
AEA
7
AC
E0#
AED35
AS
DC
AS#
AED48
AEA
6
AEA
19
AE
CLK
OU
T1
AB
E3#
AED42
AEA
16
AB
E7#
AED38
AEA
10
AC
E3#
AED33
AEA
22
AS
DR
AS#
AED49
AED37
TASD
RA
S#
TASD
WE
#
TAED57
TAED42TAED41
TAED36
AED63AED62AED61AED60
AED57AED56AED55AED54
AED50
AED29
AED7
AED1AED0
AED14
AED11
AED4
AED18
AED16
AED13
AED2
AED30
AED21
AED9
AED6
AED17
AED20
AED15
AED27AED26
AED24
AED8
AED25
AED12
AED28
AED23
AED3
AED31
AED22
AED19
AED10
AED5
TAED33TAED34TAED35
TAED37
TAED39TAED40
TAED43TAED44TAED45TAED46
TAED48TAED49
TAED52
TAED54
TAED56
TAED59
TAED63
TAE
A17
TAE
A17
TAE
A[2
2..3
](9
)
TAAR
DY
9)
TAS
DR
AS#
(2,9
)TA
SD
WE
#(2
,9)
TAS
DC
AS#
(2,9
)
TAE
CLK
OU
T2(9
)
TAC
E2#
(2,9
)
TAB
E2#
(9)
TAB
E3#
(9)
TAC
E3#
(2,9
)
TAB
E1#
(9)
TAB
E0#
(9)
TAE
D[6
3..0
](9
)
3.3V
3.3V
DG
ND
DG
ND
DG
ND
3.3V
U10
A
TMS
320C
6416
TGLZ
AD26AC26AC25AB25AB24AB26AA24AA25AA23AA26Y24Y25Y23Y26W23W24AD19AC19AF20AC20AE20AD20AF21AC21AE21AD21AF22AD22AE22AE23AF23AF24
T23
T24
R25
R26
M25
M26
L23
L24
L26
K23
K24
K25
M22
P22
N22
R22
J25
J24
K26
L25
J26
J23
A24A23B23B22C22A22C21B21D21A21C20B20D20A20D19C19H24H23G26G23G25G24F26F23F25F24E26E24E25D25D26C26
T22
V24
V25
V26
U23
U24
U25
U26 T25
T26
R23
R24
P23
P24
P26
N23
N24
N26
M23
M24 L22
V23
AED32AED33AED34AED35AED36AED37AED38AED39AED40AED41AED42AED43AED44AED45AED46AED47AED48AED49AED50AED51AED52AED53AED54AED55AED56AED57AED58AED59AED60AED61AED62AED63
AB
E7
AB
E6
AB
E5
AB
E4
AB
E3
AB
E2
AB
E1
AB
E0
AC
E3
AC
E2
AC
E1
AC
E0
APD
TAB
USR
EQ
0AH
OLD
AA
SO
E3
A_A
RE
/SD
CAS
/SA
DS
/SR
EA
_AO
E/S
DR
AS/S
OE
A_A
WE
/SD
WE
/SW
E
ASD
CK
EA
ECLK
OU
T1A
ECLK
OU
T2
AED0AED1AED2AED3AED4AED5AED6AED7AED8AED9AED10AED11AED12AED13AED14AED15AED16AED17AED18AED19AED20AED21AED22AED23AED24AED25AED26AED27AED28AED29AED30AED31
AE
A22
AE
A21
AE
A20
AE
A19
AE
A18
AE
A17
AE
A16
AE
A15
AE
A14
AE
A13
AE
A12
AE
A11
AE
A10
AE
A9
AE
A8
AE
A7
AE
A6
AE
A5
AE
A4
AE
A3
AA
RD
YA
HO
LD
RN11F 33
RN14B 33
RN
8H33
R41
10K
RN
12C
33
RN
8G33
RN10D 33
RN13D 33
R44
33RN14F 33
RN
12B
33
RN11B 33
R46
33R
4333
RN
8F33
RN
12A
33
RN13H 33
RN14A 33
RN11G 33
RN
8E33
TP18
RN
9H33
RN13C 33
RN
7B33
RN
7A33
RN14E 33
RN10E 33
RN
7H33
RN
7G33
RN
7F33
RN
7E33
RN
7D33
RN
7C33
RN11C 33
TP17
RN
8D33
C97
0.1
RN
9G33
C75
0.1
C73
0.1
RN6F 33
RN6H 33
RN4B 33
RN5F 33RN5E 33RN5D 33
RN5B 33
RN10A 33
RN13G 33
RN3C 33
RN3A 33
RN3G 33
RN5C 33
RN4D 33
RN6A 33
RN3D 33
RN6C 33
C95
0.1
RN
8C33
RN11H 33RN6G 33
RN4A 33RN5H 33
RN6E 33
RN3E 33
RN6D 33
RN4G 33
RN4C 33
RN4F 33
RN3F 33
RN4H 33
RN4E 33
RN5G 33
RN6B 33
RN3H 33
RN3B 33
C44
0.1
RN5A 33R
N9F
33
C74
0.1
U9
MT4
8LC
2M32
B2T
G-6
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 34 36 37 39 40 42 45 47 48 50 51 53 54 5633
24 66 65 64 63 62 61 60 27 26 2523 22 68 672071 16 19 18 1759 28 86 72 58 44 84 78 52 46 38 32 12 6
43 29 15 1 81 75 55 49 41 35 9 3
21 70 6973 57 30 14
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8D
Q9
DQ
10D
Q11
DQ
12D
Q13
DQ
14D
Q15
DQ
16
DQ
18D
Q19
DQ
20D
Q21
DQ
22D
Q23
DQ
24D
Q25
DQ
26D
Q27
DQ
28D
Q29
DQ
30D
Q31
DQ
17
A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA
1B
A0
CLK
CK
E
CS
DQ
M1
DQ
M0
RA
SC
AS
WE
DQ
M3
DQ
M2
VSS
VSS
VSS
VSS
VSS
QVS
SQ
VSS
QVS
SQ
VSS
QVS
SQ
VSS
QVS
SQ
VD
DV
DD
VD
DV
DD
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
NC
NC
NC
NC
NC
NC
NC
C45
0.1
U13
MT4
8LC
2M32
B2T
G-6
2 4 5 7 8 10 11 13 74 76 77 79 80 82 83 85 31 34 36 37 39 40 42 45 47 48 50 51 53 54 5633
24 66 65 64 63 62 61 60 27 26 2523 22 68 672071 16 19 18 1759 28 86 72 58 44 84 78 52 46 38 32 12 6
43 29 15 1 81 75 55 49 41 35 9 3
21 70 6973 57 30 14
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8D
Q9
DQ
10D
Q11
DQ
12D
Q13
DQ
14D
Q15
DQ
16
DQ
18D
Q19
DQ
20D
Q21
DQ
22D
Q23
DQ
24D
Q25
DQ
26D
Q27
DQ
28D
Q29
DQ
30D
Q31
DQ
17
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA
1B
A0
CLK
CKE
CS
DQ
M1
DQ
M0
RAS
CAS
WE
DQ
M3
DQ
M2
VS
SV
SS
VS
SV
SS
VS
SQ
VS
SQ
VS
SQ
VS
SQ
VS
SQ
VS
SQ
VS
SQ
VS
SQ
VD
DV
DD
VD
DV
DD
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
VD
DQ
NC
NC
NC
NC
NC
NC
NC
C42
0.1
RN
8B33
RN10F 33
RN13B 33
RN11D 33
RN14D 33
RN
9E33
R42
33
RN
8A33
TP11
R26
33
RN
9D33
RN13F 33
RN14H 33
RN10B 33
C41
0.1
C43
0.1
RN
9C33
RN13A 33
TP14
RN14C 33
RN10G 33
+C
T5 10
TP13
RN11E 33
R45
33
RN
9B33
R25
33
R48
33
+C
T13
10
R47
33
RN13E 33
RN10C 33
RN11A 33
RN14G 33
RN
9A33
TP12
R49
33
RN
12D
33
RN10H 33
Spectrum Digital, Inc
A-7
EMIF
B &
FLA
SH
LIL_
EN
DIA
NB
OO
T_M
OD
E1
BO
OT_
MO
DE
0A
EC
LKIN
_SE
L1A
EC
LKIN
_SE
L0
BE
CLK
IN_S
EL0
BE
CLK
IN_S
EL1
EE
AI
UTO
PIA
_EN
NEA
R D
SP
NE
AR
DS
P
NEA
R D
SP
PE
NC
IL S
WIT
CH
EN
DIA
NB
OO
T-1
BO
OT-
0
OFF
- O
PE
NO
N -
CLO
SE
D
IPU
IPU
IPD
INP
UT
CLO
CK
FREQ
UE
NC
Y S
ELE
CT
IPD
IPD
IPD
IPD
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
615
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
BE
A6
BE
A17
BE
A7
BE
A11
BE
A19
BE
A8
BE
A3
BE
A10
BE
A9
BE
A20
BE
A12
BE
A2
BE
A14
BE
A13
BE
A15
BE
A18
BE
A16
BE
A5
BE
A4
BE
A1
BE
CLK
OU
T2
TBAO
E#
BE
CLK
OU
T1
BA
RE
#
TBEC
LKO
UT1
BA
OE
#TB
AWE
#B
AW
E#
BC
E1#
TBC
E1#
TBEC
LKO
UT2
TBED0
TBED5
TBE
D3
TBED2
TBE
D5
TBED1
TBED4
TBE
D1
TBED6
TBED3
TBE
D0
TBED7
TBE
D4
TBE
D2
TBE
D6
TBAO
E#
TBE
D7
TBAW
E#
TBEA
9
TBE
A7
TBEA
1TB
EA
17
TBE
A17
TBEA
3TB
EA
15TB
EA4
TBE
A5
TBE
A11
TBE
A8
TBEA
8
TBEA
13TB
EA
6
TBEA
8
TBEA
12
TBEA
14
TBE
A14
TBEA
7
TBE
A18
TBE
A4
TBE
A13
TBE
A15
TBEA
15
TBE
A9
TBE
A16
TBEA
20
TBEA
10
TBEA
16
TBEA
2
TBEA
17
TBE
A14
TBE
A20
TBEA
5
TBEA
11
TBE
A12
TBE
A16
TBEA
9
TBE
A10
TBEA
19
TBE
A2
TBE
A11
TBEA
6
TBE
A3
BC
E0#
TBC
E0#
TBAR
E#
TBE
A19
TBEA
18
TBC
E1#
TBE
A13BED1
BED6
BED3
BED0
BED7
BED4
BED2
BED5
TBEA
1
TBEA
20TB
EA19
TBEA
18
TBEA
[3..1
](2
)
TBC
E0#
(2)
TBAR
E#
(2)
TBAO
E#
(2)
TBAW
E#
(2)
TBE
D[7
..0]
(2)
FLAS
H_P
AG
E(2
)
TBEA
11(8
)
TBEA
13(8
)
BR
D_R
ST#
(2)
SP
AR
E_S
ELE
CT
(2)
DS
P_P
LL_S
ELE
CT3
(2)
DS
P_P
LL_S
ELE
CT2
(2)
DS
P_P
LL_S
ELE
CT4
(2)
DS
P_P
LL_S
ELE
CT1
(2)
3.3V
3.3V
DG
ND
DG
ND
3.3V
DG
ND
DG
ND3.
3V
DG
ND
DG
ND
3.3V
R10
210
KR
103
10K
R10
410
KR
105
10K
SW3
SW
DIP
-8/S
M
1 2 3 4
16
765 8
15 14 13 12 11 10 9
TP26
R58
33
R87
1K
C93
0.1
TP24
R50
51K
R74
NU
R50
4N
UR
721K
RN
17D
33
R73
NU
R68
NU
TP25
RN
17C
33
R85
1K
R70
NU
RN
17B
33
R50
31K
R86
1K
TP22
RN
17A
33R
N16
H33
RN
16G
33R
N16
F33
RN
16E
33R
N16
D33
RN
16C
33R
N16
B33
RN
16A
33R
N15
H33
RN
15G
33R
N15
F33
U15
AM
29LV
400B
2 1 48345678 9
10 13 14
16181920212223242537 4627
26 28 11 1247
1529 31 33 35 38 40 42 44 30 32 34 36 39 41 43 4517
A14
A15
A16
A13
A12
A11
A10
A9
A8
A19
NC
1N
C2
NC
3
A18
A7
A6
A5
A4
A3
A2
A1
A0
VC
C
VS
SV
SS
CE
OE
WE
RES
ET
BY
TE
RY
/BY
DQ
0D
Q1
DQ
2D
Q3
DQ
4D
Q5
DQ
6D
Q7
DQ
8D
Q9
DQ
10D
Q11
DQ
12D
Q13
DQ
14D
Q15
/A-1
A17
RN
15E
33R
N15
D33
R75
1K
RN
15C
33R
N15
B33
RN
15A
33
R71
NU
RN18H 33RN18G 33
R61
33
TP21
RN18F 33
R69
NU
RN18E 33
R59
33
RN18D 33RN18C 33RN18B 33RN18A 33
U10
B
TMS
320C
6416
TGLZ
E16
D18
C18
B18
A18
D17
C17
B17
A17
D16
C16
B16
A16
D15
C15
B15
A15
D14
C14
A14
E11
B19
B10D10A9C10B9D9B8C9A7C8B7D8A6C7B6D7
E12
E14
E13
E15
A10
B11
C11
D12
D11
A13
C12
B12
A12
D13
C13
BEA
20B
EA19
BEA
18B
EA17
BEA
16B
EA15
BEA
14B
EA13
BEA
12B
EA11
BEA
10B
EA9
BEA
8B
EA7
BEA
6B
EA5
BEA
4B
EA3
BEA
2B
EA1
BAR
DY
BH
OLD
BED0BED1BED2BED3BED4BED5BED6BED7BED8BED9BED10BED11BED12BED13BED14BED15
BPD
TBB
USR
EQ
0BH
OLD
AB
SO
E3
B_A
RE
/SD
CAS
/SA
DS
/SR
EB
_AO
E/S
DR
AS/S
OE
B_A
WE
/SD
WE
/SW
E
BEC
LKO
UT1
BEC
LKO
UT2
BC
E3
BC
E2
BC
E1
BC
E0
BB
E1
BB
E0
R60
33
R62
33
R63
33
R64
33
R57
10K
TP30
TP23
Spectrum Digital, Inc
A-8 TMS320C6416T DSK Module Technical Reference
MC
BS
P SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
715
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
CLK
X0
DX
0
CLK
S0
DR
0
CLK
R0
DR
2D
X2
FSX
2
CLK
S2
CLK
R2
CLK
X2
FSR
2
DC
ISO
-4.1
V
FSR
0FS
X0
MC
BSP
2_E
N(2
,8)
DC
_DR
0(1
0)D
C_C
LKX
0(1
0)D
C_C
LKR
0(1
0)D
C_C
LKS
0(1
0)
DC
_DX
0(1
0)
DC
_FS
R0
(10)
DC
_FS
X0(1
0)
DC
_CLK
S2
(10)
DC
_CLK
R2
(10)
DC
_CLK
X2
(10)
DC
_DR
2(1
0)
DC
_FS
R2
(10)
DC
_FS
X2(1
0)
DC
_DX
2(1
0)
AIC
23S
DA
TAO
UT
(15)
AIC
23S
DA
TAIN
(15)
BC
LK(1
5)
LRC
IN(1
5)
LRC
OU
T(1
5) CPL
D_M
CB
SP
2_M
UX
(2)
XD
S_4
.1V
(4,1
3)
3.3V
DG
ND
DG
ND
DG
ND
DG
ND
5V
DG
ND
DG
ND
DG
ND
R12
360
U10
D
TMS
320C
6416
TGLZ
F4 D1
E1
D2
E2
C1
E3
AE4
AB1
AC
2
AB3
AA2
AC
1A
B2 AF3
CLK
S0
CLK
R0
CLK
X0
DR
0D
X0
FSR
0FS
X0
CLK
S2_
GP
08C
LKR
2C
LKX
2_X
SP
CLK
DR
2_X
SP
DI
DX
2_X
SPD
O
FSR
2FS
X2
MC
BS
P2_E
N
C12
0
0.1
R1
1.6K
D1 LM
4040
DC
IM3-
4.1
21
C13 0.
1
R55
1K
U4
SN
74C
BT3
257P
W4
14
711
9 1213 12 15103 5 6
16 8
1A
4B1
2A3B
13A 4A
4B2
S1B1
OE
3B2
1B2
2B1
2B2
VC
C
GN
D
U20
SN
74C
BTD
3384
PW
1 133 4 7 8 11
2 5 6 9 10
14 17 18 21 22
24 1215 16 19 20 23
1OE
2OE
1A1
1A2
1A3
1A4
1A5
1B1
1B2
1B3
1B4
1B5
2A1
2A2
2A3
2A4
2A5
Vcc
GN
D
2B1
2B2
2B3
2B4
2B5
U3
SN
74C
BT3
257P
W4
14
711
9 1213 12 15103 5 6
16 8
1A
4B1
2A3B
13A 4A
4B2
S1B1
OE
3B2
1B2
2B1
2B2
VC
C
GN
D
R76
360
Spectrum Digital, Inc
A-9
UTO
PIA
& H
OS
T PO
RT
I/F
UTO
PIA
Inte
rface
HP
I DA
UG
HTE
R C
AR
D C
AN
RES
ET
DS
P V
IA T
HIS
SIG
NA
L. S
IGN
AL
ISC
OM
BIN
ED
WIT
H O
THE
R D
SP
RE
SE
T S
OU
RC
ES
.
LOC
ATE
NE
AR
UTO
PIA
HE
AD
ER
/DSP
PA
D8/
PAD
10 W
ERE
SW
APP
ED
ON
REV
A/B
PW
B.
RE
MO
VE
HA
RD
WIR
EO
F TB
EA1
1 O
N R
EV
EP
WB
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
815
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
UR
DA
TA4
UR
DA
TA0
UR
SO
C
UX
DA
TA2
UR
DA
TA5
UR
DA
TA3
UX
DA
TA0
UX
CLK
UR
CLA
V
UX
DA
TA6
UX
AD
DR
1U
RA
DD
R0
UR
CLK
UX
DA
TA5
UR
DA
TA1
UX
CLA
V
UX
SO
C
UR
AD
DR
3
UR
DA
TA2
UX
DA
TA4
UR
DA
TA6
UR
AD
DR
1U
XA
DD
R0
UR
DA
TA7
UX
EN
B#
UX
DA
TA1
UX
DA
TA3
UR
AD
DR
2
UR
EN
B#
UX
DA
TA7
UR
SO
C
UR
DA
TA0
UR
DA
TA6
UR
DA
TA2
UR
DA
TA4
UR
DA
TA1
UR
DA
TA5
UR
DA
TA7
UR
DA
TA3
UR
CLA
V
UX
DAT
A2U
XD
ATA0
UX
DAT
A4U
XD
ATA6
UR
AD
DR
3U
RA
DD
R1
UR
AD
DR
2U
RA
DD
R0
UR
AD
DR
4
UX
CLA
V
UX
SO
C
UX
CLK
UX
AD
DR
0U
XA
DD
R2
UX
AD
DR
4
UX
ADD
R1
UX
ADD
R3
PAD0PAD1PAD2PAD3PAD4PAD5PAD6PAD7PAD8PAD9PAD10PAD11PAD12PAD13PAD14PAD15PAD16PAD17PAD18PAD19PAD20PAD21PAD22PAD23PAD24PAD25PAD26PAD27PAD28PAD29PAD30PAD31
PD
EV
SE
LnP
STO
Pn
PTR
DY
n
PC
BE
2nP
SE
RR
nP
CB
E1n
PP
ER
Rn
PP
AR
PC
I_E
N
PIR
DYn
PFR
AME
n
PR
STn
PC
LKP
INTA
nP
GN
TnP
RE
Qn
PC
BE
3nP
IDS
EL
XS
P_C
S
PC
BE
0n
UR
CLK
UR
EN
B#
UX
EN
B#
CLK
X1
DX
1
FSX
1
CLK
X1
DX
1
UX
AD
DR
4
UX
AD
DR
3
UR
AD
DR
4
UX
AD
DR
2FS
X1
PCI_
EN
XSP
_CS
PA
D1
PA
D3
PA
D5
PA
D7
PA
D8
PA
D12
PA
D14
PC
BE
1n
PS
ERR
n
PD
EV
SEL
n
PIR
DY
n
PC
BE
2n
PA
D19
PA
D23
PC
BE
3n
PA
D25
PA
D29
PA
D31
PR
EQ
n
PC
LK
PA
D10
PA
D21
PA
D27
PA
D17
PP
ERR
n
PC
BE
0nP
AD0
PAD
2P
AD4
PAD
6
PAD
9P
AD11
PAD
13P
AD15
PPA
R
PST
OPn
PTR
DYn
PFR
AM
En
PAD
16P
AD18
PAD
20P
AD22
PID
SEL
PAD
24P
AD26
PAD
28P
AD30
PG
NTn
PR
STn
PIN
TAn
UX
DA
TA5
UX
DA
TA3
UX
DA
TA1
UX
DA
TA7
HP
I_R
ES
ET#
(2)
CTL
_FS
X1
(15)
CTL
_DX
1(1
5)
CTL
_CLK
X1
(15)
CP
LD_M
CB
SP1_
MU
X(2
)
MC
BS
P2_E
N(2
,7)
TBE
A13
(6)
TBEA
11(6
)
DG
ND
DG
ND
3.3V
DG
ND
5V
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
J2
SFM
-140
-L2-
S-D
-LC
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
R19
10K
U1
SN
74C
BT3
257P
W
4
14
711
9 1213 12 15103 5 6
16 8
1A
4B1
2A3B
13A 4A
4B2 S
1B1
OE
3B2
1B2
2B1
2B2
VCC
GN
D
R18
360
J1 SFM
140L
2SD
LC
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
JP50
3
SOLD
ER
_JU
MP
ER
12
AB
U10
F
TMS
320C
6416
GLZ
AE9
AF1
1A
C9
AB1
3A
B11
AD
7A
E7A
F7A
F9A
E8A
D8
AD
9A
D10
AD
11A
C14
AE1
5A
C13
AE
10A
F10
AC
10A
C8
AB
12
AD
13A
D14
AE
12A
C12
AC
11A
F13
AE
11A
F12
AD
12A
F14
AD
15A
B14
UX
AD
DR
0U
XA
DD
R1_
DR
1U
XAD
DR
2_FS
R1
UX
AD
DR
3_FS
X1
UX
AD
DR
4_D
X1
UX
DA
TA0
UX
DA
TA1
UX
DA
TA2
UX
DA
TA3
UX
DA
TA4
UX
DA
TA5
UX
DA
TA6
UX
DA
TA7
UX
CLK
UX
CLA
VU
XE
NB
UX
SO
C
UR
ADD
R0
UR
ADD
R1
UR
ADD
R2_
CLK
R1
UR
ADD
R3_
CLK
S1
UR
ADD
R4_
CLK
X1
UR
DA
TA0
UR
DA
TA1
UR
DA
TA2
UR
DA
TA3
UR
DA
TA4
UR
DA
TA5
UR
DA
TA6
UR
DA
TA7
UR
CLK
UR
CLA
VU
REN
BU
RSO
C
D2 LM
4040
DC
IM3-
4.1
21
R3
1.6K
C28 0.
1
U10
C
TMS3
20C
6416
TGLZ
AA
4
T3R2
T2T1P1
R3
T4R1
J2K3J1K4K2L3K1L4L1M4M2N4M1N5N1P5U4U1U3U2V4V1V3V2W2W4Y1Y3Y2Y4AA1AA3
W3
AD
1
M3L2F1J3G4F2G3
R4
P4
PC
I_E
N
PP
AR_H
AS
PP
ER
R_H
CS
PC
BE
1_H
DS
2P
SER
R_H
DS1
PCB
E2_H
R/W
PTR
DY
_HH
WIL
PS
TOP
_HC
NTL
0P
DE
VS
EL_H
CN
TL1
AD31_HD31AD30_HD30AD29_HD29AD28_HD28AD27_HD27AD26_HD26AD25_HD25AD24_HD24AD23_HD23AD22_HD22AD21_HD21AD20_HD20AD19_HD19AD18_HD18AD17_HD17AD16_HD16AD15_HD15AD14_HD14AD13_HD13AD12_HD12AD11_HD11AD10_HD10
AD9_HD9AD8_HD8AD7_HD7AD6_HD6AD5_HD5AD4_HD4AD3_HD3AD2_HD2AD1_HD1AD0_HD0
PC
BE
0
XS
P_C
S
PID
SE
L_G
P9
PC
BE
3_G
P10
PR
EQ
_GP
11P
GN
T_G
P12
PIN
TA_G
P13
PC
LK_G
P14
PR
ST_
GP
15
PFR
AME
_HIN
TP
IRD
Y_H
RD
Y
Spectrum Digital, Inc
A-10 TMS320C6416T DSK Module Technical Reference
#OE
DIR
OP
ERA
TIO
NL
L
A
<-- B
L
H
A --
> B
H
X
ISO
LATI
ON
DA
UG
HTE
RC
AR
D B
UFF
ER
ING
DC
_EM
IFA
_DIR
= 0
FO
R W
RIT
ES
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
915
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
TAE
A13
DC
_D30
DC
_D16
DC
_D26
DC
_D14
DC
_D15
DC
_D4
TAE
A9
DC
_D10
DC
_D21
DC
_D25
TAE
D17
DC
_A19
TAE
A4
TAED
11
TAED
1
DC
_A2
TAE
A3
TAE
A21
TAE
A12
TAE
D21
DC
_A16
DC
_D19
DC
_D23
DC
_D3
DC
_A11
DC
_A20
TAE
A14
DC
_D24
DC
_D22
DC
_D8
DC
_A8
DC
_A9
TAE
A22
DC
_D11
DC
_D17
TAE
A10
TAE
D18
TAED
13
DC
_D6
DC
_D1
DC
_A7
DC
_D20
DC
_A6
TAE
A20
TAE
A6
DC
_D5
DC
_D0
DC
_A15
TAE
A8
TAED
9
TAED
15
TAE
A15
DC
_D12
DC
_D31
TAE
A11
DC
_D7
DC
_D28
TAE
A7
DC
_D9
TAED
24
DC
_D2
DC
_A4
TAE
A17
TAE
D16
DC
_A14
DC
_A21
DC
_A3
TAE
A19
TAED
0
DC
_D18
DC
_D27
TAE
A18
DC
_A18
DC
_A5
DC
_A10
DC
_A17
TAE
A5
TAE
A16
TAED
8
DC
_D13
TAED
31
DC
_D29
TAED
2TA
ED3
TAED
4TA
ED5
TAED
6TA
ED7
TAED
14
TAED
12
TAED
10 TAE
D19
TAE
D20
TAE
D22
TAE
D23
TAED
30TA
ED29
TAED
28TA
ED27
TAED
26TA
ED25
DC
_A12
DC
_A13
DC
_A[2
1..2
](1
0)
TAE
A[22
..3]
(5)
TAE
D[6
3..0
](5
)
DC
_D[3
1..0
](1
0)
TAS
DW
E#
(2,5
)TASD
CA
S#
(2,5
) TAE
CLK
OU
T2(5
)
TABE
0#(5
)
TABE
2#(5
)
TAC
E3#
(2,5
)
TASD
RA
S#
(2,5
)
DC
_AR
DY
(10)
TAC
E2#
(2,5
)
TABE
3#(5
)
TABE
1#(5
)D
C_B
E2#
(10)
TAA
RD
Y(5
)
DC
_EC
LKO
UT
(10)
DC
_BE
3#(1
0)
DC
_BE
0#(1
0)D
C_C
E3#
(10)
DC
_AW
E#
(10)
DC
_AO
E#
(10)
DC
_AR
E#(1
0)
DC
_BE
1#(1
0)
DC
_CE
2#(1
0)
DC
_CN
TL_O
E#(2
)
DC
_EM
IFA
_DIR
(2)
DC
_EM
IFA
_OE
#(2
)
DG
ND
3.3V
DG
ND
3.3V
DG
ND
3.3V
3.3V
3.3V
3.3V 3.
3V
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
DG
ND
3.3V
DG
ND
3.3V
3.3V
U16
SN
74LV
TH16
245A
7 183142 47 46 44 43 41 40 38 37
2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26
13 14 16 17 19 20 22 23
48 1 25 24 4 10 15 21
28 34 39 45
Vcc
Vcc
Vcc
Vcc
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OE
1DIR
2OE
2DIR
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
R40
31K
U6
SN
74LV
TH16
245A
7 183142 47 46 44 43 41 40 38 37
2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26
13 14 16 17 19 20 22 23
48 1 25 24 4 10 15 21
28 34 39 45
Vcc
Vcc
Vcc
Vcc
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OE
1DIR
2OE
2DIR
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
U17
SN
74LV
TH16
245A
7 183142 47 46 44 43 41 40 38 37
2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26
13 14 16 17 19 20 22 23
48 1 25 24 4 10 15 21
28 34 39 45
Vcc
Vcc
Vcc
Vcc
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OE
1DIR
2OE
2DIR
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
C14
0.1
C16
0.1
C17
0.1
C15
0.1
R15
22
U5
SN
74LV
TH16
245A
7 183142 47 46 44 43 41 40 38 37
2 3 5 6 8 9 11 1236 35 33 32 30 29 27 26
13 14 16 17 19 20 22 23
48 1 25 24 4 10 15 21
28 34 39 45
Vcc
Vcc
Vcc
Vcc
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OE
1DIR
2OE
2DIR
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
C18
0.1
C21
0.1
C19
0.1
R13
10K
C20
0.1
R14
1K
C94
0.1
C96
0.1
C11
6
0.1
C11
5
0.1
C11
8
0.1
C98
0.1
C99
0.1
C11
7
0.1
Spectrum Digital, Inc
A-11
DA
UG
HTE
RC
AR
D I/
F
Ext
erna
l Mem
ory
Inte
rface
Ext
erna
l Per
iphe
ral I
nter
face
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
1015
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DC
_D27
DC
_D11
DC
_D19
DC
_D9
DC
_A2
DC
_A18
DC
_A12
DC
_D5
DC
_D17
DC
_A14
DC
_A10
DC
_A17
DC
_D15
DC
_A19
DC
_D3
DC
_A21
DC
_D7
DC
_A6
DC
_A16
DC
_D13
DC
_A13
DC
_A3
DC
_D21
DC
_A9
DC
_D29
DC
_D23
DC
_A4
DC
_A5
DC
_A15
DC
_D1
DC
_A7
DC
_A11
DC
_A20
DC
_D25
DC
_A8
DC
_D20
DC
_D4
DC
_D31
DC
_D18
DC
_D22
DC
_D14
DC
_D2
DC
_D30
DC
_D6
DC
_D24
DC
_D26
DC
_D28
DC
_D16
DC
_D10
DC
_D0
DC
_D12
DC
_D8
DC
_DR
0(7
)
DC
_CLK
S0
(7)
DC
_EIN
T7(4
)
DC
_CLK
X0
(7)
DC
_CLK
R2
(7)
DC
_A[2
1..2
](9
)
DC
_CN
TL0
(2)
DC
_BE3
#(9
)
DC
_AO
E#(9
)D
C_C
E2#
(9)
DC
_BE
0#(9
)
DC
_CLK
X2
(7)
DC
_TO
UT0
(4)
DC
_FS
R2
(7)
DC
_CN
TL1
(2)
DC
_TO
UT1
(4)
DC
_RST
#(2
)
DC
_EIN
T4(4
)
DC
_AW
E#(9
)
DC
_DR
2(7
)
DC
_BE1
#(9
)
DC
_FS
X2
(7)
DC
_EIN
T5(4
)
DC
_EC
LKO
UT
(9)
DC
_FS
R0
(7)
DC
_TIN
P0
(4)
DC
_AR
DY
(9)
DC
_CLK
S2
(7)
DC
_DX0
(7)
DC
_FS
X0
(7)
DC
_CE
3#(9
)
DC
_EIN
T6(4
)
DC
_CLK
R0
(7)
DC
_D[3
1..0
](9
)
DC
_TIN
P1
(4)
DC
_AR
E#
(9)
DC
_DX2
(7)
DC
_BE
2#(9
)
DC
_DE
T(2
)
DC
_STA
T1(2
)D
C_S
TAT0
(2)
DG
ND
DG
ND
DG
ND
DG
ND
-12V
12V
3.3V
5V
3.3V
5V
3.3V
3.3V
5V5V
3.3V
3.3V
R16
4.7K
R2
0
R65
10K
J4
CO
NN
EC
TOR
40
X 21
23
45
67
89
1011
1213
1415
1617
1819
2021
2223
2425
2627
2829
3031
3233
3435
3637
3839
4041
4243
4445
4647
4849
5051
5253
5455
5657
5859
6061
6263
6465
6667
6869
7071
7273
7475
7677
7879
80
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
J3
CO
NN
EC
TOR
40
X 21
23
45
67
89
1011
1213
1415
1617
1819
2021
2223
2425
2627
2829
3031
3233
3435
3637
3839
4041
4243
4445
4647
4849
5051
5253
5455
5657
5859
6061
6263
6465
6667
6869
7071
7273
7475
7677
7879
80
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
Spectrum Digital, Inc
A-12 TMS320C6416T DSK Module Technical Reference
3.3
sq in
AG
ND
, min
ther
mal
pad
Con
nect
at p
in 1
Set
s Vo
ltage
3.3V
@1.
5Am
p M
ax
3.3
sq in
AG
ND
, min
ther
mal
pad
1.4V
@1.
5Am
p M
ax
Con
nect
at p
in 1
WARNING:
DO
NOT
SUPPLY
POWERTO
BOTH
POWERCONNECTORS
ATTHE
SAMETIME!
TO B
E P
OP
ULA
TED
BY
THE
US
ER
IFN
EE
DE
D.
Mol
ex 1
5-24
-404
1
2.5
MM
JAC
K
POW
ER IN
PUT
DAUG
HTE
RCAR
D ST
ANDO
FF G
ROUN
DING
KE
EP
TRA
CE
S A
MIN
IMU
MO
F 0.
070
INC
HES
FR
OM
THE
SE H
OLE
S.
POW
ER
PO
WE
R E
STI
MA
TES
BA
SED
ON
SP
RU
190
1.4V
@60
0MH
z
3.3V
@60
0MH
z
1.09
W
0.52
W
0.77
8A
0.15
7A (
no e
mif
clk)
ME
AS
UR
ED
CU
RR
EN
T O
N C
6416
TEB,
~0.
7A@
5V
EAC
H R
EG
ULA
TOR
CA
N S
UP
PLY
UP
TO
3A
OF
CU
RR
EN
T. H
OW
EV
ER
CO
MPO
NE
NT
VA
LUE
SH
AV
E B
EE
N S
ELE
CTE
D F
OR
1.5
A O
PE
RA
TIO
N.
VAL
UE
S C
ALC
ULA
TED
WIT
H S
WIF
T D
ES
IGN
TO
OL
2.0.
EM
I SU
PP
RE
SIO
N.
LOC
ATE
NEA
R E
AC
H R
EG
ULA
TOR
.6
VIA
S FR
OM
PA
D T
O P
LAN
E O
R D
IRE
CT
TIE.
DS
P P
OW
ER
ME
AS
UR
EM
EN
TP
OIN
TS.
R IS
251
2 BO
DY
, 6
VIA
SFR
OM
PA
D T
O P
LAN
E
FOLL
OW
TP
S54
310
EV
M L
AYO
UT
1.4V
-> 1
7.4K
1%
1.2V
-> 2
8.0K
1%
1.1V
-> 4
2.2K
1%
OP
TIO
NA
L C
RO
SS C
OU
PLE
OP
TIO
NA
L, P
OW
ER
SU
PP
LYLO
AD R
ES
ISTO
RS
, 251
2B
OD
Y
SYS
TEM
PO
WE
R M
EA
SU
REM
EN
TPO
INTS
. R
IS 2
512
BO
DY,
6 V
IAS
FRO
M P
AD
TO
PLA
NE
0.02
5 O
HM
S F
OR
PO
WE
RM
EA
SU
RE
ME
NT
0.02
5 O
HM
S F
OR
PO
WE
RM
EA
SU
RE
MEN
T
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
1115
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
SEN
SE_
DS
P_C
VD
D
SVS
_RS
T#(2
,17)
DS
PIO
_3.3
V(4
,12)
DS
P_C
VD
D(1
2)
AG
ND
3.3V
AG
ND
3.3V
5V
-12V
12V
DG
ND
DG
ND
DS
PIO
_3.3
V
DS
P_C
VD
D
DG
ND
DG
ND
5V
U7
TPS
5431
0PW
P
1 2 3 4 5 6 7 8 9 101112131415161718192021
AG
ND
VSE
NS
EC
OM
PPW
RG
DB
OO
T
PH
1P
H2
PH
3P
H4
PH
5PG
ND
1PG
ND
2PG
ND
3
VIN
1VI
N2
VIN
3
VBIA
SSS
/EN
ASY
NC
RT
POW
ER
PA
D
C11
1000
pF
C63
0.1u
FC
64
0.1u
F
+C
T9
10uF
LE
SR
U2
TPS
5431
0PW
P
1 2 3 4 5 6 7 8 9 101112131415161718192021
AG
ND
VSE
NS
EC
OM
PPW
RG
DB
OO
T
PH
1P
H2
PH
3P
H4
PH
5PG
ND
1PG
ND
2PG
ND
3
VIN
1VI
N2
VIN
3
VBIA
SSS
/EN
ASY
NC
RT
POW
ER
PA
D
C2
560p
F
C3
0.04
7uF
L12.
7 uH
C9
0.1u
FC
7
0.1u
F
+C
T3
10uF
LE
SR
L2
BLM
41P
750S
PT
C4
0.01
uF
TP32
Test
Poin
t
1
C1
1000
pF
R6
28.0
K 1
%
+C
T210
0uF
4V
R7 10
K 1
%
R8
107
1%C
533
00pF
R5
1.65
K 1
%
D12
MU
RS
120T
3
L32.
7 uH
C10
0.04
7uF
C12
7
NO
-PO
P
J5 RA
SM
712
CE
NTE
RS
HU
NT
SLE
EV
E
R21
10K
1%
R20
107
1%C
3733
00pF
C12
470p
FR11
2K 1
%C
3682
00pF
R10
3.74
K 1%
+C
T4
100u
F 4V
R38 10
K
+C
T16
47uF
R9
71.5
KC
6
0.1u
F
R31
71.5
K 1%
C65
0.1u
F
R66
0
C66
0.03
9uF
JP2
NO
-PO
P
12
JP1
NO
-PO
P
12
R99
0 JP4
NO
-PO
P
12
R4
0
D3
GR
EE
N
C8
0.03
9uF
M4
125_
PH
M2
125_
PH
M3
125_
PH
M1
125_
PH
+C
T15
100
uF
+C
T1
100
uF
R34
6N
UR
347
NU
TP31
TP
TP2
TPTP1
TP
L4
BLM
41P
750S
PT
J6
NU
1234
+12
-12
GN
D+5
R52
180
D13
MU
RS
120T
3
D14
MU
RS
120T
3
D15
MU
RS
120T
3
D16
MU
RS
120T
3
Spectrum Digital, Inc
A-13
DS
P P
OW
ER
& D
EC
OU
PLI
NG
All
capa
cito
rs o
n th
is s
heet
are
dec
oupl
ing
capa
cito
rs fo
r th
e D
SP
. The
y sh
ould
be
plac
ed a
s cl
ose
as p
ossi
ble
to th
e D
SP.
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
1215
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
DS
PIO
_3.3
V(4
,11)
DSP
_CV
DD
(11)
DG
ND
DG
ND
DG
ND
DG
ND
DS
PIO
_3.3
VD
SP
IO_3
.3V
DS
PIO
_3.3
V
DS
P_C
VD
DD
SP
_CVD
D
DS
P_C
VD
D
DS
P_C
VD
D
DS
PIO
_3.3
V
DS
PIO
_3.3
V
C76
0.1
U10
H
TMS3
20C
6416
TGLZ
A2
A25 B1
B14
B26 E7
E8
E10
E17
E19
E20 F9 F12
F15
F18
G5
G22 H
5H
22 J21
K5
K22 M6
M21 N2
P25
R21
U5
U22
V6 V21
W5
W22
Y5 Y22
AA9
AA12
AA15
AA18
AB7
AB8
AB10
AB17
AB19
AB20
AE1
AE13
AE26
AF2
AF25
L5 M5
T5R5
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
DV
DD
U10
I
TMS
320C
6416
TGLZ
A8
A19 B3
B13
B24 C2
C4
C23
C25 D3
D5
D22
D24 E4
E6
E9
E18
E21
E23 F5 F8 F10
F11
F13
F14
F16
F17
F19
F22
G9
G12
G15
G18 H
1H
6H
21H
26 J5 J7 J20
J22
K21 L6 L21
M7
M20 N6
N21
N25 P2
P6
P21
R7
R20
T6 T21
U6
U21
V5
V7
V20
V22
W1
W6
W21
W26
Y9
Y12
Y15
Y18
AA5
AA8
AA1
0A
A11
AA1
3A
A14
AA1
6A
A17
AA1
9A
A22
AB4
AB6
AB9
AB1
8A
B21
AB2
3A
C3
AC
5A
C22
AC
24A
D2
AD
4A
D23
AD
25A
E3A
E14
AE2
4A
F8A
F19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C52
0.1
C11
00.
1
C10
20.
1
C88
0.1
C78
0.1
C24
0.1
C10
40.
1
U10
G
TMS
320C
6416
TGLZ
A1 A26 B2 B25 C3
C24 D4
D23 E5 E22 F6 F7 F2
0F2
1G
6G
7G
8G
10G
11G
13G
16G
17G
19G
20G
21H
20 K7 K20 L7 L20
N7
P20
T7 T20
U7
U20
W7
W20
Y6
Y7
Y8
Y10
Y11
Y14
Y16
Y17
Y19
Y20
Y21
AA
6A
A7
AA
20A
A21
AB
5A
B22
AC
4A
C23
AD
3A
D24
AE
2A
E25
AF1
AF2
6
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
CV
DD
C10
30.
1C
620.
1
C25
0.1
C32
0.1
C10
90.
1
C10
80.
1
C11
10.
1
C10
50.
1C
300.
1C
790.
1C
460.
1
C58
0.1
C50
0.1
C77
0.1
C34
0.1
C60
0.1
C90
0.1
C10
70.
1C
910.
1C
490.
1C
890.
1C
870.
1C
570.
1
C31
0.1
C61
0.1
C84
0.1
C10
10.
1
+C
T6 10
C35
0.1
C55
0.1
C80
0.1
+C
T8 10
C56
0.1
C86
0.1
C48
0.1
+C
T14
10+
CT1
110
C10
60.
1
C85
0.1
+C
T7 10
C53
0.1
U10
J
TMS
320C
6416
TGLZ
F3 A3
G2
G14 H
3H
7 J4 K6
N3
N20
P3
P7
R6
W25
Y13
RS
VR
SV
RS
VR
SV
RS
VR
SV
RS
VR
SV
RS
VR
SV
RS
VR
SV
RS
VR
SV
RS
V
C11
20.
1
C33
0.1
C54
0.1
+C
T12
10
C81
0.1
C26
0.1
C47
0.1
C27
0.1
C23
0.1
C10
00.
1
C82
0.1
C59
0.1
C83
0.1
C29
0.1
C51
0.1
Spectrum Digital, Inc
A-14 TMS320C6416T DSK Module Technical Reference
JTAGMULTIPLEXERS
EMU
LATI
ON
DSPJTAGHEADER
ROU
TE T
RAC
ES A
SO
NE G
ROUP
. MAT
CHSI
GNA
L LE
NG
TH.
LOC
ACTE
R-P
AC
K N
EA
R D
SP
US
B IN
USE
SPEC
TRU
M D
IGIT
AL IN
CO
RPO
RAT
ED
5080
32A
TMS3
20C
6416
T D
SK
B
1315
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
XD
S_T
RS
T#T_
TMS
XD
S_E
MU
1
XD
S_T
DO
XD
S_T
MS
XD
S_E
MU
0
XD
S_T
VD
XD
S_T
DI
T_EM
U1
XD
S_4
.1V
T_EM
U0
HU
RR
ICAN
E_D
ETn
HU
R_E
MU
9H
UR
_EM
U8
HU
R_E
MU
3H
UR
_EM
U2
HU
R_E
MU
5H
UR
_EM
U4
HU
R_E
MU
7H
UR
_EM
U6
HU
R_E
MU
1H
UR
_EM
U0
MU
X_E
MU
0
MU
X_E
MU
1
HU
R_E
MU
10H
UR
_EM
U11
HU
R_T
CK
HU
R_T
CK
RTN
T_TR
STn
T_TC
K
HU
RR
ICA
NE
_DE
Tn
XD
S_T
CK
RE
T
XD
S_T
CK
T_TC
K_R
ET
T_TD
O
T_TD
I
DS
P_T
DO
(4)
DS
P_T
DI
(4)
DS
P_T
MS
(4)
T_EM
U0
(16,
17)
T_EM
U1
(16,
17)
DS
P_E
MU
9(4
)D
SP
_EM
U8
(4)
DS
P_E
MU
2(4
)
DS
P_E
MU
7(4
)
DS
P_E
MU
3(4
)
DS
P_E
MU
5(4
)D
SP
_EM
U4
(4)
DS
P_E
MU
6(4
)
T_TC
K_R
ET
(17)
DS
P_E
MU
0(4
)
DS
P_E
MU
1(4
)
DS
P_E
MU
10(4
)D
SP
_EM
U11
(4)
DS
P_T
CK
(4)
DS
P_T
RS
T#(4
)
T_TM
S(1
7)
T_TC
K(1
7)
T_TR
STn
(17)
XDS
_4.1
V(4
,7)
T_TD
O(1
7)
T_TD
I(1
7)
DG
ND
3.3V
DG
ND
DG
ND
DG
ND
3.3V
DG
ND
5V
DG
ND
DG
ND3.
3V
DG
ND
3.3V
DG
ND
DG
ND
DG
ND
3.3V
3.3V
DG
ND
3.3V
3.3V
DG
ND
DG
ND
3.3V
DG
ND
DG
ND
3.3V
RN
1D42
RN
1E42
RN
2D42
RN
2C42
R92
33
R96
33
U24
SN
74LV
C1G
32
1 24
5 3
R93
1.6K
D5 LM
4040
DC
IM3-
4.1
21
RN
2A42
RN
2B42
C12
2
.1uF
R89
150
R95
100
1%
U26 SN
74LV
C1G
321 2
4
5 3
C12
6
22pF
J8
HE
AD
ER
7x2
, Em
ulat
ion
1 3 5 7 9
2 4 8 1011
1213
14
R90
47K
R67
47K
C12
4.1
uF
U19
SN
74C
BT3
257P
W4
14
711
9 1213 12 15103 5 6
16 8
1A
4B1
2A3B
13A 4A
4B2
S1B1
OE
3B2
1B2
2B1
2B2
VC
C
GN
D
J7 HE
AD
ER
4x1
5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
B14
C14
B13
C13
B12
C12
B11
C11
B10
C10B9
C9
B7
C7
B6
C6
B5
C5
B4
C4
B3
C3
B2
C2
B1
B15C1
C15 B8
C8
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DTY
PE0
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DTY
PE1
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
EM
U0
EM
U1
EM
U2
EM
U3
TCLK
EM
U4
EM
U5
EM
U6
EM
U7
EM
U8
EM
U9
EM
U10
TDO
EM
U11
EM
U12
EM
U13
EM
U14
EM
U15
TDI
EM
U16
EM
U17
TRS
TnTM
S
EM
U18
ID0
ID1
ID2
ID3
TVD
TCK
RTN
U25
SN
74C
BT3
257P
W4
14
711
9 1213 12 15103 5 6
16 8
1A
4B1
2A3B
13A 4A
4B2
S1B1
OE
3B2
1B2
2B1
2B2
VC
C
GN
D
D4
LTS
T-C
150G
KT
R88
1K
R94
30.1
K
C12
3
0.1
U23
SN
74LV
C1G
32
1 24
5 3
U22
SN
74A
HC
1G14
3
4
5
2
U18 SN
74A
HC
1G14
3
4
5
2
RN
2E42
RN
2F42
RN
2G42
RN
1C42
RN
1A42
RN
1B42
RN
2H42
RN
1F42
RN
1G42
R91
1K
C12
5
0.1
Spectrum Digital, Inc
A-15
5 5
4 4
3 3
2 2
1 1
D C B AH
iera
rchi
cal B
lock
sSP
ECTR
UM
DIG
ITAL
INC
OR
POR
ATED
5080
32A
TMS3
20C6
416T
DSK
B
1415
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
US
B/E
mul
atio
n
US
B/E
mul
atio
n
5V
US
B_D
SP_R
ST#
T_TD
O
T_TC
KT_
TMS
T_TR
STn
T_E
MU
0T_
EMU
1
T_TD
I
3.3V PO
NR
Sn
GN
D
T_TC
K_R
ET
CLK
_12M
HZ
CLK
_24M
HZ
AIC
23 A
udio
AIC
23 A
udio
GN
D
DA
TA_B
CLK
DA
TA_S
YN
CIN
DA
TA_D
IND
ATA
_DO
UT
CTL
_DA
TAC
TL_C
LKC
TL_C
S
CO
DE
C_S
YS
CLK
AIC
3.3V
DA
TA_S
YN
CO
UT
CLK
_12M
HZ
US
B_D
SP
_RS
T#(2
,17)
T_TD
I(1
3,17
)T_
TMS
(13,
17)
T_TC
K(1
3,17
)
T_EM
U0
(13,
16,1
7)T_
EMU
1(1
3,16
,17)
T_TD
O(1
3,17
)SV
S_R
ST#
(2,1
1,17
)
T_TR
STn
(13,
17)
T_TC
K_R
ET
(13,
17)
CTL
_CLK
X1(8
,15)
CTL
_FS
X1
(8,1
5)
CTL
_DX
1(8
,15)
BCLK
(7,1
5)
AIC
23S
DA
TAO
UT
(7,1
5)LR
CO
UT
(7,1
5)
AIC
23S
DAT
AIN
(7,1
5)LR
CIN
(7,1
5)
CO
DE
C_C
LK(2
,15)
5V
DG
ND
3.3V
3.3V
DG
ND
DG
ND
3.3V
DG
ND
U11
SN
74LV
C1G
32
1 24
5 3
C67
.1uF
R32
33
Spectrum Digital, Inc
A-16 TMS320C6416T DSK Module Technical Reference
5 5
4 4
3 3
2 2
1 1
D C B A
Con
trol P
ort
AU
DIO SP
ECTR
UM
DIG
ITAL
INC
OR
POR
ATED
5080
32A
TMS3
20C6
416T
DSK
B
1515
Wed
nesd
ay, N
ovem
ber 1
0, 2
004
Title
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
LLIN
E_O
UT
RLI
NE
_OU
T
AIC
23LR
CIN
AIC
23C
S
SPI
MO
DE
3.3V
A
3.3V
A
AIC
3.3V
AIC
3.3V
AIC
3.3V
AIC
3.3V
AIC
3.3V
+
C32
510
uF
C32
60.
1uF
+
C31
910
uF
C32
20.
1uF
R32
52.
2K
R32
8N
O P
OP
R32
64.
7K
R33
74.
7K
R33
44.
7K
R33
64.
7K
R33
54.
7K
C34
1
0.1u
F
+C32
3220
uF
+ C32
4220
uF
L306
BLM
21P
221S
NC
340
NO
PO
P
C34
4N
O P
OP
C34
5N
O P
OP
R34
30
C32
1
47pF
+
C31
5
1uF
L307
BLM
21P
221S
N
C33
9N
O P
OP
C33
847
0nF
J302
Hea
d P
hone
Out
3 4 2 1
C34
2
0.1u
F
R33
247
KC
333
470n
F
C33
447
0nF
R33
347
KJ3
03
Line
In
3 4 2 1
R34
533
C33
20.
1uF
J301
Mic
roph
one
In
3 4 2 1
+
C34
3
10uF
C33
747
0nF
R31
20
C33
6N
O P
OP
L305
BLM
21P
221S
N
C32
9N
O P
OP
+
C33
110
uF
J304
Line
Out
3 4 2 1
R34
147
KR
342
47K
R33
910
0
R33
80
L304
BLM
21P
221S
NC
330
NO
PO
P
C33
5N
O P
OP
RN
314
10K
1 2 3 45678
RN
316
33
1 2 3 45678
R34
010
0
PWPackage
U30
7 TLV
320A
IC23
22141115 25
34 5 212423
10 9 28
16 17 18 20 19
26 13 12
8
167
2 27
MO
DE
AVd
dH
PGN
DA
GN
D
XTI
/MC
LK
BC
LK
DIN
LRC
IN
CS
SC
LKS
DIN
RH
PO
UT
LHP
OU
T
DG
ND
VM
ID
MIC
_BIA
SM
IC_I
NLL
INE
_IN
RLI
NE
_IN
XTO
RLI
NE
_OU
TLL
INE
_OU
T
HP
Vdd
BV
dd
DO
UT
LRC
OU
T
CLK
OU
T
DV
dd
L308
BLM
21P
221S
N
L303
BLM
21P2
21S
N
C31
8N
O P
OP
R34
42.
2
L301
HZ0
805E
601R
R32
70
C32
0N
O P
OP
L309
BLM
21P
221S
N
C31
7N
O P
OP
C31
6N
O P
OP
C32
7N
O P
OP
R33
10
+
C34
7
10uF
+
C34
6
10uFL3
02B
LM21
P221
SN C
328
NO
PO
P
RN
315
10K
1 2 3 45678
CTL
_CLK
(8)
CTL
_CS
(8)
CTL
_DAT
A(8
)
DA
TA_D
IN(7
)D
ATA
_SY
NC
IN(7
)D
ATA
_BC
LK(7
) DAT
A_D
OU
T(7
)
DA
TA_S
YN
CO
UT
(7)
CO
DEC
_SY
SC
LK(1
4)
AIC
3.3V
GN
D
B-1
Appendix B
Mechanical Information
This appendix contains the mechanical information about theTMS320C6416T DSK produced by Spectrum Digital.
Spectrum Digital, Inc
B-2 TMS320C6416T DSK Module Technical Reference
TH
IS D
RA
WIN
G IS
NO
T T
O S
CA
LE
Printed in U.S.A., November 2004508035-0001 Rev. A