ds9420-p01

RT9420

Preliminary

DS9420-P01 October 2012 www.richtek.com1

Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

Host-Side Single Cell Lithium Battery Gauge

General DescriptionThe RT9420 is a compact, host-side fuel gauge IC forlithium-ion (Li+) battery-powered systems.

RT9420 calculates and determines the Li+ battery State-of-Charge (SOC) according to battery OCV informationand a sophisticated battery voltaic model. The dynamicvoltaic information can effectively emulate the Li+ batterybehavior and determines the SOC.

The calculation is base on the battery voltage informationand the dynamic difference of battery voltage, by usingiteration algorithm to track the battery open circuit voltageto estimate state-of-charge. Comparing to coulombcounter based fuel gauge solution, voltaic gauge does notaccumulate error with time and current.

A quick sensing operation provides a good initial estimateof the battery's SOC. This feature allows the IC to belocated on system side, reducing cost and supply chainconstraints on the battery. Measurement and estimatedcapacity data sets are accessed through an I2C interface.

The RT9420 is available in WDFN-8L 2x3 package.

Featureszzzzz Host-Side Fuel Gaugingzzzzz Precision Voltage Measurement 12.5mV Accuracyzzzzz Accurate Relative Capacity (RSOC) Calculated from

Voltaic Gauge Algorithmzzzzz No Accumulation Error on Capacity Calculationzzzzz No Battery Relearning Necessaryzzzzz No Current Sense Resistor Requiredzzzzz External Alarm/Interrupt for Low Battery Alertzzzzz I2C Compatible Interfacezzzzz Low Power Consumptionzzzzz Tiny, 8-Lead WDFN Packagezzzzz RoHS Compliant and Halogen Free

Applicationsz Smartphonesz MP3 Playersz Digital Still Camerasz Digital Video Camerasz Handheld and Portable Applications

Simplified Application Circuit

VBAT

RT9420

QSTEST

SDA

GND

VDD

SCL

R2 R3 System Processor

SDASCL

R1

C1

C2

+

Li + Protection

Circuit

ALERT IRQ

RT9420

2DS9420-P01 October 2012www.richtek.com

Preliminary


Function Pin DescriptionPin No. Pin Name Pin Function

1 TEST Test Pin. Connect to GND Pin During Normal Operation. 2 VBAT Battery Voltage Measurement Input.

3 VDD Processor Power Input. Decouple with a 10nF capacitor.

4, 9 (Exposed Pad) GND

Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

5 ALERT Alert Output. When SOCLow condition is detected, It outputs low as interrupt signal. Connect to interrupt input of the system processor. Connect to GND if not used.

6 QS Quick Sensing Input. Active high to restart the calculation. Pull low to GND during normal operation.

7 SCL Serial Clock Input. Slave I2C Serial Communications Clock Line for

Communication with System.

8 SDA Serial Data Input. Slave I2C Serial Communications Data Line for

Communication with System. Open-drain I/O.

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Marking InformationRT9420

Package TypeQW : WDFN-8L 2x3 (W-Type)

Lead Plating SystemG : Green (Halogen Free and Pb Free)

06W

06 : Product Code

W : Date Code

Pin Configurations(TOP VIEW)

WDFN-8L 2x3

TEST

GND

VBATSDASCLQSALERT

VDD GN

D

9

765

1234

8

RT9420

3DS9420-P01 October 2012 www.richtek.com

Preliminary


Function Block Diagram

Operation

12-bit ADCAnalog-to-Digital Converter. It converts the voltage inputfrom VBAT pin to target value.

Battery OCV ModelParameters for battery characteristics.

Voltaic Gauge AlgorithmThe RT9420 calculates and determines the Li+ batterySOC according to battery OCV information and asophisticated battery voltaic model.

The algorithm is base on the battery voltage informationand the dynamic difference of battery voltage, by usingiteration calculation to track the battery open circuit voltageto estimate state-of-change.

ControllerThe controller takes care of the control flow of systemroutine, ADC measurement flow, algorithm calculation andalert determined.

I2C InterfaceThe fuel gauge registers can be accessed through the I2CInterface.

I2C Interface

SDAGND SCL

ControllerVoltaic Gauge Algorithm

Battery OCV Model

ALERT12-bit ADCVBAT

VDD

QS

TEST

RT9420


Preliminary


Recommended Operating Conditions (Note 3)z Supply Voltage, VDD ----------------------------------------------------------------------------------------------------- 2.5V to 4.5Vz Junction Temperature Range-------------------------------------------------------------------------------------------- 40C to 125Cz Ambient Temperature Range-------------------------------------------------------------------------------------------- 40C to 85C

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit DC Section Active Current IACTIVE -- 22 40 A

VDD = 2.5V -- 0.5 1 Sleep-Mode Current (Note 4) ISLEEP -- 1 3

A VDD = 3.6V at 25C 1 -- 1 TA = 0C to 70C 2 -- 2 Time-Base Accuracy tERR TA = 20C to 70C 3 -- 3

%

TA = 25C, VBAT = VDD 12.5 -- 12.5 Voltage Measurement Error VGERR 25 -- 25 mV

VBAT Pin Input Impedance RVBAT 15 -- -- M Logic-High All voltage reference to GND 1.4 -- -- SCL, SDA,

QS Input Logic-Low All voltage reference to GND -- -- 0.5 V

SDA Output Logic-Low VOL_SDA IOL_SDA = 4mA, All voltage reference to GND -- -- 0.4 V

ALERT Output Logic-Low VOL_ALERT IOL_ALERT = 2mA, All voltage reference to GND -- -- 0.4 V

SCL, SDA Pull-down Current IPD VDD = 4.5V, VSCL = VSDA = 0.4V -- 0.2 0.4 A Bus Low Timeout tSLEEP (Note 5) 1.75 -- 2.5 s

(2.5V VDD 4.5V, TA = 25C unless otherwise specified)

Absolute Maximum Ratings (Note 1)z Voltage on TEST Pin Relative to GND -------------------------------------------------------------------------------- 0.3V to 5.5Vz Voltage on VBAT Pin Relative to GND ------------------------------------------------------------------------------- 0.3V to 5.5Vz Voltage on All Other Pins Relative to GND -------------------------------------------------------------------------- 0.3V to 6Vz SCL, SDA, QS, ALERT to GND --------------------------------------------------------------------------------------- 0.3V to 5.5Vz VBAT to GND --------------------------------------------------------------------------------------------------------------- 0.3V to 5Vz Power Dissipation, PD @ TA = 25C

WDFN-8L 2x3 -------------------------------------------------------------------------------------------------------------- 3.17Wz Package Thermal Resistance (Note 2)

WDFN-8L 2x3, JA --------------------------------------------------------------------------------------------------------- 31.5C/WWDFN-8L 2x3, JC--------------------------------------------------------------------------------------------------------- 7.5C/W

z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260Cz Junction Temperature ----------------------------------------------------------------------------------------------------- 150Cz Storage Temperature Range -------------------------------------------------------------------------------------------- 65C to 150C

RT9420


Preliminary


Parameter Symbol Test Conditions Min Typ Max Unit I2C Interface

Clock Operating Frequency fSCL (Note 6) 10 -- 400 kHz Bus Free Time Between a STOP and START Condition tBUF 1.3 -- -- s Hold Time After START Condition tHD_STA (Note 6) 0.6 -- -- s Low Period of the SCL Clock tLOW 1.3 -- -- s High Period of the SCL Clock tHIGH 0.6 -- -- s Setup Time for a Repeated START Condition tSU_STA 0.6 -- -- s Data Hold Time tHD_DAT (Note 7, Note 8) 0.2 -- 0.9 ms Data Setup Time tSU_DAT (Note 7) 100 -- ns Clock Data Rise Time tR 20 -- 300 ns Clock Data Fall Time tF 20 -- 300 ns Set-Up Time for STOP Condition tSU_STO 0.6 -- -- s Spike Pulse Widths Suppressed by Input Filter tSP (Note 9) 0 -- 50 ns

Capacitive Load for Each Bus Line CB (Note 10) 400 -- -- pF

SCL, SDA Input Capacitance CBIN -- -- 60 pF

Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC ismeasured at the exposed pad of the package.

Note 3. The device is not guaranteed to function outside its operating conditions.Note 4. SDA, SCL = GND; QS, ALERT idle.Note 5. The RT9420 enter Sleep mode 1.75s to 2.5s after (SCL < VIL) AND (SDA < VIL).Note 6. fSCL must meet the minimum clock low time plus the rise/fall times.Note 7. The maximum tHD_DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.Note 8. This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)

to bridge the undefined region of the falling edge of SCL.

Note 9. Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.Note 10. CB total capacitance of one bus line in pF.

RT9420


Preliminary


Typical Application Circuit

Timing Diagram

SDA

SCL

tFtLOW

tHD_STA tHD_DAT tHIGH

tSU_DAT

tSU_STA

tHD_STA tSPtBUF

tSU_STOP S

tR

SrS

tF tR

VBAT

RT9420

QSTEST

SDA

GND

VDD

SCL

R2150

R34.7k

System Processor

SDASCL

R11k

C11F

C210nF

+

Li + Protection

Circuit

ALERT

1

2

6

4, 9 (Exposed Pad)

87

5

3

IRQ

RT9420


Preliminary


Typical Operating Characteristics(TA = 25C, battery is Sanyo UF534553F, unless otherwise specified.)

* : Sample accuracy with custom parameters into the IC.

Voltage ADC Error vs. Temperature

-25

-20

-15

-10

-5

0

5

10

15

20

25

-20 -5 10 25 40 55 70

Temperature (C)V

olta

ge A

DC

Erro

r (m

V)

VBAT = 3VVBAT = 3.6VVBAT = 4.3V

Quiescent Current vs. Supply Voltage

0

5

10

15

20

25

30

35

40

2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5

Supply Voltage (V)

Qui

esce

nt C

urre

nt (

A)

VOUT = 3.3V

70C25C20C

Constant Discharge C/4 SOC Accuracy *

0

10

20

30

40

50

60

70

80

90

100

0 2 4 6 8 10 12 14 16 18 20Time (h)

SO

C (%

)

-10

-8

-6

-4

-2

0

2

4

6

8

10

SO

C E

rror (

%)

Reference SOCRT9420 SOCError

Constant Discharge C/2 SOC Accuracy *

0

10

20

30

40

50

60

70

80

90

100

0 2 4 6 8 10 12 14

Time (h)

SO

C (%

)

-10

-8

-6

-4

-2

0

2

4

6

8

10

SO

C E

rror (

%)


Zigzag Discharge C/2 SOC Accuracy *

0

10

20

30

40

50

60

70

80

90

100

0 2 4 6 8 10 12Time (h)

SO

C (%

)

-10

-8

-6

-4

-2

0

2

4

6

8

10

SO

C E

rror (

%)


RT9420


Preliminary


Application Information

Voltaic Gauge Theory and PerformanceThe RT9420 calculates and determines the Li+ batterySOC according to battery OCV information and asophisticated battery voltaic model. The dynamic voltaicinformation can effectively emulate the Li+ battery behaviorand determines the SOC.

The calculation is base on the battery voltage informationand the dynamic difference of battery voltage, by usingiteration algorithm to track the battery open circuit voltageto estimate state-of-charge. Comparing to coulombcounter based fuel gauge solution, voltaic gauge does notaccumulate error with time and current. The coulombcounter based fuel gauge suffers from SOC drift due tocurrent-sense error and cell self-discharge. Even there isa very small current sensing error, the coulomb counteraccumulates the error from time to time. The accumulatederror can be eliminated by only full charged or fulldischarged. The RT9420 estimates battery capacity byonly voltage information and will not accumulate errorbecause it does not rely on battery current information.For different chemistry battery, users need to uploadcompensation data to the RT9420 to achieve optimumperformance, please contact factory for details.

Power OnWhen the IC is power on by the battery insertion, the ICmeasures the battery voltage quickly and predict the firstSOC according to the voltage. The first SOC would beaccurate if the battery has been well relaxed for over 30min. Otherwise, the initial SOC error occurs.

However, the initial SOC error will be convergent and theSOC will be adjusted gradually and finally approach to theaccurate SOC without accumulation error.

Quick SensingA Quick Sensing operation allows RT9420 to restartsensing and SOC calculation. It is the same behavior aspower on. The operation is used to reduce the initial SOCerror caused by unwell power on sequence. A QuickSensing operation could be performed by either a risingedge on the QS pin or I2C Quick Sensing command tothe Control register.

Sleep ModeRT9420 will enter sleep mode if host pulls low both SDAand SCL to logic-low at least 2.5s. All operation such asvoltage measurement and SOC calculation are halted andpower consumption is reduced under 3A in sleep mode.Any rising edge of SDA or SCL will transfer IC back toactive mode immediately.

The other way to enter sleep mode is write [Sleep] bit inthe Config register to 1 through I2C communication, andthe only way to exit sleep mode is to write [Sleep] bit tologic 0 or power on reset the IC.

InitializationThe RT9420 can be reset by writing an initializationcommand to MFA resister. The behavior of initialization isthe same as power on reset.

I2C RegisterThe RT9420 supports the following 16-bit I2C registers:VBAT, SOC, Control, Device ID, Config and MFA.

The register writing is valid when all of 16 bits data aretransferred; otherwise, the write data will be ignored. Thevalid register addresses are defined in Table 1. Otherremaining addresses are reserved.

ALERT InterruptThe RT9420 monitors the SOC and reports the alertcondition if the SOC falls below the SOCLow which is inthe Config (0Dh) register.

When alert condition occurs, the RT9420 outputs logic-low to the ALERT pin and sets 1 to the [Alert] bit in theConfig register. The only two ways to recover the alertcondition is either writing 0 to clear [Alert] bit or power onreset. Before the recovery, the [Alert] bit will keep 1 andthe ALERT pin will keep logic-low. It can't recover the alertcondition by entering sleep mode.

Please note that the alert detection function is enablewhen power on.

RT9420


Preliminary


Device IDThe Device ID register is a read only register that containsa value indicating the production ID of the RT9420.

ConfigThe Config register includes the parameter ofcompensation, setting of sleep mode and SOCLowthreshold. It also indicates the alert status. The format ofConfig is shown in Figure 3.

VGCOMP is the setting to optimize IC performance fordifferent cell chemistries or temperatures. Contact Richtekfor instructions for optimization. The power on reset valuefor VGCOMP is ABh.

Table 2. Control Register Commands

Value Command Description

4000h Quick Sensing Restart sensing and

SOC calculation

Figure 3. Config Register

Register Bit Description 0x0C 7 : 0 VGCOMP

7 Sleep 6 X (Dont Care) 5 Alert

0x0D

4 : 0 SOCLow SOCLow Range : 11111b = 1% SOCLow Range : 00000b = 32% SOCLow Unit : 1 LSB = 2's Complement 1%

Table 1. I2C RegisterAddress

(Hex) Register Description Read/ Write

Default (Hex)

02h-03h VBAT It reports voltage measured form the input of VBAT pin. R --

04h-05h SOC It reports the SOC result calculated by voltaic-gauge algorithm. R --

06h-07h Control It's the command interface for special function such as Quick Sensing. W --

08h-09h Device ID It reports the device ID. R --

0Ch-0Dh Config The Config register includes the parameter of compensation, setting of sleep mode and SOCLow threshold. It also indicates the alert status.

R/W AB1Ch

FEh-FFh MFA Manufacturer Access. Sends special commands to the IC for the manufacturing. W --

VBATThe VBAT register is a read only register that reports themeasured voltage at VBAT pin. The VBAT is reported inunits of 1.25mV. The first report is made after chip PORwith 250ms delay and then updates 1s periodically. Figure1 shows the VBAT register format.

MSB-Address 04h

MSB211

LSB MSB LSB

LSB-Address 03h

0 0 0 029210 28 27 26 25 24 23 22 21 20

0 : Bits Always Read Logic 0Unit : 1.25mV

SOCThe SOC register is a read only register that returns therelative state of charge of the cell as calculated by thevoltaic gauge algorithm. The result is displayed as apercentage of the cell's full capacity. The high byte isreported in units of %. The low byte is reported in units of1/256%. Figure 2 shows the SOC register format.

Figure 1. VBAT Register

Figure 2. SOC Register

MSB-Address 04h

MSB27

LSB MSB LSB

LSB-Address 05h

2526 24 23 22 21 20 2-1 2-2 2-3 2-4

Unit : 1%

2-5 2-6 2-7 2-8

ControlThe Control register allows the host processor to sendspecial commands to the IC (Table2). Valid Control registerwrite values are listed as follows. All other Control registervalues are reserved.

RT9420


Preliminary


Table 3. MFA Register Commands

Value Command Description 5400h Initialization Reset the IC

[Sleep]Writing [Sleep] to logic 1 forces the IC to enter Sleepmode. Writing [Sleep] to logic 0 forces the IC to exit Sleepmode. The power on reset value for [Sleep]is logic 0.

[Alert]The [Alert] bit is set by the IC when the alert conditionoccurs. The [Alert] bit is cleared by either host writing 0to clear or a reset condition occurs.

The power on reset value for [Alert] is logic 0.

[SOCLow]The SOCLow is a 5-bit value for setting the low batteryalert threshold and defined as 2's-complement form. Theprogramming unit is 1% and range is 32% to 1%. (00000= 32%, 10001 = 15%, 11100 = 4%, 11111 = 1%). Thepower on reset value for SOCLow is 4% or 1Ch.

MFAThe MFA register allows the host processor to sendspecial commands to the chip for manufacturing. ValidMFA register write values are listed as follows. All otherMFA register values are reserved. Table 3 shows MFAregister commands.

Application ExamplesThe RT9420 has multi configurations for differentapplication. Table 4 shows the typical applicationconfigurations and the corresponding pin connections.

Table 4. Typical Application Configurations

System Configuration VDD ALERT QS System-Side Location Power directly from battery Connect to GND Connect to GND System-Side Location

SOCLow Interrupt Power directly from battery Connect to system interrupt Connect to GND

System-Side Location Hardware Quick Sensing Power directly from battery Connect to GND

Connect to rising-edge Reset signal

Figure 4. RT9420 Application Example with Alert Interrupt

VBAT

RT9420

QSTEST

SDA

GND

VDD

SCL

R2150

R34.7k

System Processor

SDASCL

R11k

C11F

C210nF

Protection IC (Li+/Polymer)

System VDD

System GND

+

BatteryPack+

Pack-

1

2

6

4, 9 (Exposed Pad)

87

5

3

ALERT IRQ

VBAT

RT9420


Preliminary


Table 5. 2-Wire Protocol

Symbol Description Symbol Description S START bit Sr Repeated START

SAddr Slave address (7bit) R/W Read : R/W = 1; Write : R/W = 0 CAddr Command address (byte) P STOP bit Data Data byte written by master Data Data byte returned by slave

A Acknowledge bit written by master A Acknowledge bit returned by slave N No acknowledge bit written by master N No acknowledge bit returned by slave

Thermal ConsiderationsFor continuous operation, do not exceed absolutemaximum junction temperature. The maximum powerdissipation depends on the thermal resistance of the ICpackage, PCB layout, rate of surrounding airflow, anddifference between junction and ambient temperature. Themaximum power dissipation can be calculated by thefollowing formula :

PD(MAX) = (TJ(MAX) TA) / JA

where TJ(MAX) is the maximum junction temperature, TA isthe ambient temperature, and JA is the junction to ambientthermal resistance.

For recommended operating condition specifications, themaximum junction temperature is 125C. For WDFN-8L2x3 package, the thermal resistance, JA, is 31.5C/Won a standard JEDEC 51-7 four-layer thermal test board.The maximum power dissipation at TA = 25C can becalculated by the following formula :

PD(MAX) = (125C 25C) / (31.5C/W) = 3.17W forWDFN-8L 2x3 package

The maximum power dissipation depends on the operatingambient temperature for fixed TJ(MAX) and thermalresistance, JA. The derating curve in Figure 6 allow thedesigner to see the effect of rising ambient temperatureon the maximum power dissipation.

Figure 5. I2C Timing DiagramRead Protocol

Write ProtocolS SAddr W A CAddr A Data0 A Data1 A P

S SAddr W A CAddr A SAddr R Data0

A

Sr A

Data1 N P

Figure 4 presents a single cell battery-powered systemapplication. The RT9420 is used on system side and directpowered from the battery.

The RC filter saves the noise for IC power supply andvoltage measurement on VBAT pin.

To reduce the I-R drop effect, make the connection of VBATas close as possible to the battery pack.

The ALERT pin provides a battery low interrupt signal tosystem processor when capacity low is detected.

The QS pin is unused in this configuration, so it needs tobe tied to GND.

I2C Bus InterfaceFigure 5 shows the timing diagram of the I2C interface.

The RT9420 communicates with a host (master) by usingthe standard I2C 2-wire interface. After the START condition,the I2C master sends 8-bits data, consisting of 7 bit slaveaddress and a following data direction bit (R/W).

A byte of data consists of 8 bits ordered MSB first andthe LSB followed by the Acknowledge bit.

The RT9420 address is 0110110 (6Ch) and is a receiveonly (slave) device. The second word selects the registerto which the data will be written. The third word containsdata to write to the selected register.

Table 5 applies to the transaction formats.

RT9420


Preliminary


Figure 6. Derating Curve of Maximum Power Dissipation

0.0

0.6

1.2

1.8

2.4

3.0

3.6

0 25 50 75 100 125

Ambient Temperature (C)

Max

imum

Pow

er D

issi

patio

n (W

) 1 Four-Layer PCB

Figure 7. PCB Layout Guide

B-

TEST

GND

VBATSDASCLQSALERT

VDD GN

D

9

7

6

5

1

2

3

4

8

R3B+

B-

B+

C1

C2

R2

R1Positive Power Bus

Negative Power Bus

VDD and GND need direct connect to battery for preventing the affect of I-R drop.

Connect to GND, if not used.

Input filter must be placed as close as possible to the input pins.

Place the chip as close as possible to the battery.

RT9420


Preliminary

Richtek Technology Corporation5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers shouldobtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannotassume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to beaccurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of thirdparties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Dimensions In Millimeters Dimensions In Inches Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.200 0.300 0.008 0.012

D 1.900 2.100 0.075 0.083

D2 1.550 1.650 0.061 0.065

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

e 0.500 0.020

L 0.350 0.450 0.014 0.018

W-Type 8L DFN 2x3 Package

1 122

Note : The configuration of the Pin #1 identifier is optional,but must be located within the zone indicated.

DETAIL APin #1 ID and Tie Bar Mark Options

D

1

E

A3A

A1

D2

E2

L

be

SEE DETAIL A

Outline Dimension

RT9420


Preliminary


Datasheet Revision History Version Data Page No. Item Description

P00 2011/11/21 First edition

P01 2012/10/15 All Modify

ds9420-p01

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