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Computer Science and Engineering (CSE) Department

National Institute of Technology (NIT)Hamirpur (H.P.) INDIA

Website: http://nith.ac.in/newweb/computer-science-engineering/

E-mail: [email protected]

Dr. Lokesh ChouhanAssistant Professor

Computer Organization

Numerical Problems

Instruction Format

• If a Computer has 128 operation codes and 512 k addresses, how many bits would be required for

(i) Single address instruction

(ii) Two address instruction.

Dr. Lokesh Chouhan NIT Hamirpur

Numerical Practice3

• No. of Op codes = 128 = 27

• Size of memory = 512 K = 29 ×210 bits.

(a) Size of single address instructions

= 7 + 19 = 26 bits.

(b) Size of two address instruction

= 7 + 2(19)

= 7+38 = 45 bits


Numerical Practice4

Instruction Format

Hard Disk Calculation

• A hard disk with 5 platters has 1024 tracks perplatter, 512 sectors per track and 512bytes/sector. What is the total capacity of thedisk?


Numerical Practice5

• 512 bytes x 512sectors

=0.2MB/track

• 0.2MB x 1024 tracks

=0.2GB/platter

• Therefore the hard disk has the total capacity of

5 x 0.2=1GB


Numerical Practice6

RAM/ROM Chip

• How many 256X8 ROM chips are required toproduce a memory capacity of 4000 bytes?How many address lines are required toaccess the 4000 bytes? How many of theseaddresses will be common to all these chips?


Numerical Practice7


Numerical Practice8

RAM/ROM Chip

Cache Access

• Give the cache access time as 10 ns memory access time as 100 ns and cache hit rate as 90%, calculate the effective memory access time.


Numerical Practice9

Hit Ratio - % of memory accesses satisfied by Cache memory systemTe: Effective memory access time in Cache memory systemTc: Cache access timeTm: Main memory access time

Te = Tc + (1 - h) Tm

Te= h*Tc+ (1-h) Tm

• 0.90 * 10 + 0.10 * 100

• = 19 ns Effective Mem Access Time.


Numerical Practice10

Cache Access

Cache: Direct Mapping

• A personal computer has main memory of

32 K × 8 bytes and cache memory of 512words. The cache is directly mapped withblock size of 4 words.

(i) How many bits are required in tag, indexblock and word fields of the address format?

(ii) Show the addressing format?




• Size of main memory

= 32 K × 8 bytes

= 25 × 210 ×23 bytes

= 218 bytes.

• Size of cache memory = 512 words = 29 words.

• Mapping method is direct mapping Block size = 4 words



(i) No. of index bits = 9, No. of tag bits = 18-9 = 9

• Total no. of bits in each word of cache

= Data bits + Tag bits = 8 + 9 =17 bits

• No. of bits for representing block

= 7 (512 /4 =27)

• No. of bits for representing the word in theblock = (9-7) = 2.

(ii) The addressing format for cache memory isby the index bits starting from (000) to (777)in octal representation.Dr. Lokesh Chouhan NIT Hamirpur



Other Not Covered

• Speed Up Factor (Amdlaw )

• Programming

• Instruction Cycle

• Addressing Modes

• DMA

• Memories



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