WebHenryWeb Based RLC interconnect tool
http://eda.ece.wisc.edu/WebHenry
Project Leader: Prof Lei HeStudents : Min Xu, Karan MehraEDA Lab (http://eda.ece.wisc.edu]ECE Dept., University of Wisconsin, Madison, WI 53706
Adapted from Min Xu’s GLS’01 presentation
06/17/01 Design Automation Conference, June 2001
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REFERENCES
• [1] L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An Efficient Inductance Modeling for On-chip Interconnects", IEEE
Custom Integrated Circuits Conference, May 1999.• [2] N. Chang, S. Lin, L. He, O. S. Nakagawa, and W. Xie,
"Clocktree RLC extraction with Efficient Inductance Modeling", IEEE/ACM Design Automation and Test in
Europe, March 2000.• [3] Min Xu and Lei He, "An efficient model for frequency-
based on-chip inductance," Design Automation Conference, June 2001.
06/17/01 Design Automation Conference, June 2001
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Inductance for GHz Designs • Interconnect impedance is more than resistance
– Z = R +jωL
– ω is decided not by the clock frequency, but by clock edge
• ω ∝ 1/tr
• On-chip inductance must be considered when ωL is comparable to R
• Inductive coupling is a long range effect
06/17/01 Design Automation Conference, June 2001
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Resistance and Inductance
0
20
40
60
80
100
120
140
160
180
200
1.00E+08 1.00E+09 1.00E+10 1.00E+11
frequency (100M-100G)
Imp
ed
an
ce
R
wL
2.50E-09
2.60E-09
2.70E-09
2.80E-09
2.90E-09
3.00E-09
3.10E-09
3.20E-09
1.00E+08 1.00E+10 1.00E+12 1.00E+14
frequency (100M-100T)Hz
Ind
ucta
nce(H
)
Self
mutual
Figure 1: R and Figure 1: R and ωωL for a single long wireL for a single long wire Figure 2: Ls and Lx for two parallel wiresFigure 2: Ls and Lx for two parallel wires
L = 2000u, W = 0.8u , T = 2.0u, S = 0.8uL = 2000u, W = 0.8u , T = 2.0u, S = 0.8u
LL
WWSS
WW
06/17/01 Design Automation Conference, June 2001
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Related Work
• Accurate but slow approach– Numerical extraction (FastHenry: Kamon et. al.94’ MTT)– Too slow to be applied on whole chip level simulation
and design iteration• Fast but less accurate approach
– Table method for bus structure (He et. al. 99’ CICC)– Analytical methods for parallel wires (Gala et. al. 00’
and Qi et. al. 00’)– Accurate enough for layout design and verification
06/17/01 Design Automation Conference, June 2001
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Our Contributions
• Developed a table & formula driven extraction tool
– For arbitrary wires– Accuracy: ±5% for most cases– http://eda.ece.wisc.edu/WebHenry/
• Proposed the so called normalized circuit model to replace full RLC circuit
– Experimentally verified their equivalence– Less complexity and shorter runtime: 11x speedup in
simulation
06/17/01 Design Automation Conference, June 2001
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Definition of Loop Inductance
• The loop inductance is
ViVj
Ii Ij
jijiloop a ijloop ajiji
ij dadadIdIrIIaa
Lj ji i
∫ ∫∫ ∫••=111
4πµ
06/17/01 Design Automation Conference, June 2001
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Loop Inductance for N Traces
• Assume edge traces are grounded– leads to 3x3 loop inductance matrix
• Inductance has a long range effect– e.g., non-negligible coupling between t1 and
t3 with t2 between them
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsR
1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tL t1 t2 t3 tR
06/17/01 Design Automation Conference, June 2001
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Table in Brute-Force Way is Expensive
• Self inductance has nine dimensions:– (n, length, location,TwL,TsL,Tw,Ts,TwR,TsR)
• Mutual inductance has ten dimensions:– (n, length, location1, location2,TwL,TsL,Tw,Ts,TwR,TsR)
• Length is needed because inductance is not linearly scalable
TwL
tL
Tw Tw Tw
t1 t2 t3
TwR
Ts TsTsL TsR
1.73 1.15 0.531.15 1.94 1.240.53 1.24 1.92tR
06/17/01 Design Automation Conference, June 2001
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Definition of Partial Inductance
• Partial inductance is the portion of loop inductance for a segment when its current returns via the infinity
– called partial element equivalent circuit (PEEC) model• If current is uniform, the partial inductance is
ViVj
il
ib
ic
jb
jc
lj
∫ ∫ ∫ ∫••=i
i i
j
j j
c
b a
c
b aji
ij
ji
jiij dada
r
dldl
aaL
14πµ
06/17/01 Design Automation Conference, June 2001
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Partial Inductance for N Traces
Treat edge traces same as inner traceslead to 5x5 partial inductance table
Partial inductance model is more accurate compared to loop inductance model
6.17 5.43 5.12 4.89 4.665.43 6.79 6.10 5.48 5.045.12 6.10 6.79 6.10 5.334.89 5.48 6.10 6.79 5.774.66 5.04 5.33 5.77 6.50
Tw Tw Tw
Ts Ts
TwL TwR
TsL TsRtL t1 t2 t3 tR
06/17/01 Design Automation Conference, June 2001
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Two Foundations
• By PEEC Definition, He et. al. (CICC ’99) pointed out two foundations:– Self inductance of a wire is solely depended on
the wire itself– Mutual inductance of two wires is solely
depended on these two wires themselves
06/17/01 Design Automation Conference, June 2001
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Table-based approach (He et. el. 99’ CICC)• Inductance table for parallel wires• Self inductance table
– Length -- L– Width -- W– Thickness -- T– Frequency -- F
• Mutual inductance table– L, W, T, F– Space -- S
06/17/01 Design Automation Conference, June 2001
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Displaced parallel wires?
• Based on foundation for mutual inductance:– Solve ten dimensional problem– L1, L2, W1, W2, T1, T2, Sv, Sh, D, F– Too big, too slow
• A formula is proposed to use only fivedimensional tables
06/17/01 Design Automation Conference, June 2001
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Formula for Lateral Dimension
• Lab =
+ - -
Mutual inductance
Lm1 Lm2 Lm3 Lm4
ab
06/17/01 Design Automation Conference, June 2001
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Formula for Cross-section
• Linear approximation
sw1
w2
T2
T1
2
+s s
06/17/01 Design Automation Conference, June 2001
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Accuracy
• WebHenry versus FastHenry• 400 random displaced parallel wires cases
06/17/01 Design Automation Conference, June 2001
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Error Distribution
l ±5% most casesl Bigger error only found in smaller inductance values
06/17/01 Design Automation Conference, June 2001
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Inductance Circuit Modeling
• Full and normalized circuit model for non-displaced parallel wires
06/17/01 Design Automation Conference, June 2001
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Full RLC Circuit Model
• Linear RC number• Quadratic L number, O(n2)
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Normalized RLC Circuit Model
• Again, linear RC number• Linear L number too!
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Full Versus Normalized
• Two waveforms are almost identical• Running time:
– Full 99.0 seconds– Normalized 9.1 seconds
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Applications
• Simultaneous shield insertion and net ordering for signal integrity
– [He-Lepak, ISPD’00] [Lepak-et al, DAC’01]
• Interconnect analysis using decoupling model– [Yin-He, ASP-DAC’01]
• Simultaneous signal and power routing– [Ma-He, SLIP’01]
• ……
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Conclusion
• A table-formula driven extraction method is proposed– Very efficient– Reasonably accurate– Frequency dependent
• Two circuit models are studied– Verified the normalized model is accurate and
efficient
06/17/01 Design Automation Conference, June 2001
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On-chip Inductance
• Wire impedance: Z = R + jϖL– Copper interconnects makes R ↓
– ϖ is proportional to signal rising time• 1 GHz clock → ϖ = 2π*10GHz
• Inductive coupling is a long range effect
• Partial inductance model is preferred. Let the circuit simulator to determine the signal return path
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The PEEC Model
• Eliminate the current return path problem
I1
L(loop)
I1I2
I3L1
L2
L3
Assume current return from infinite
K13
K12
K23
I2
I4