Download - Watchdog Timer on the PIC18F4525
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Simulated output when the ClrWdt()macro is commented out of the main loop. Note thatat 9600 bpsit takes about 2 ms to send a 0 and a comma out the USART.
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When the ClrWdt() macro is put back in the timeouts do not occur.
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To get the simulation working correctly the Break Options under simulator settings shouldbe changed to match the screen shot shown below.
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23.2 Watchdog Timer (WDT)page256
PIC18F4525 datasheet
Reset Control Register page 42 PIC18F4525 datasheet
CONFIG2H: CONFIGURATION
REGISTER 2 HIGH
page
252
PIC18F4525 datasheet
ClrWdt()Instruction Macro page 35MPlab C18 C Compiler User's
Guide
isWDTTO()functionpage
145
MPlab C18 C Compiler
Libraries
isPOR()functionpage145
MPlab C18 C CompilerLibraries
StatusReset()functionpage146
MPlab C18 C CompilerLibraries
28.3 Watchdog Timer (WDT) Operationpage
28-4
PICmicro 18C Family
Reference Manual
There are flags set within the processor that indicate different possible causes of a system
reset. For example there is a power on reset flag that indicates a rising edge has been
detected on the power pins. There is also a flag to indicate that the watchdog timer has
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timed out.
For power saving modes it is possible to shut down the 8 MHzsource while keeping the 31KHzsource running as the source clock for the watchdog timer. The watchdog timer can be
used to periodically wake up the processor.