AVR Microcontrollers Architecture
AV
R M
icro
con
tro
ller
s A
rch
itec
ture
AVR Microcontrollers Architecture
1
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Th
ere
are
two
fu
nd
amen
tal
arch
itec
ture
s to
acc
ess
mem
ory
1.
Vo
n N
eum
ann
Arc
hit
ectu
re
2.
Har
var
d A
rch
itec
ture
2
Von N
eum
ann A
rchi
tectu
re
3
Th
ere
are
two
fu
nd
amen
tal
arch
itec
ture
s to
acc
ess
mem
ory
.
Joh
n V
on
Neu
man
n's
: O
ne
shar
ed m
emo
ry f
or
inst
ruct
ion
s (p
rog
ram
) an
d
dat
a w
ith
on
e d
ata
bu
s an
d o
ne
add
ress
bu
s b
etw
een
pro
cess
or
and
mem
ory
. In
stru
ctio
ns
and
dat
a h
ave
to b
e fe
tch
ed i
n s
equ
enti
al o
rder
(kn
ow
n a
s th
e V
on
Neu
man
Bo
ttle
nec
k),
lim
itin
g t
he
op
erat
ion
ban
dw
idth
.
Its
des
ign
is
sim
ple
r th
an t
hat
of
the
Har
var
d a
rch
itec
ture
. It
is
mo
stly
use
d
to i
nte
rfac
e to
ex
tern
al m
emo
ry.
Harv
ard A
rchi
tectu
re
Th
e te
rm o
rig
inat
ed f
rom
th
e H
arv
ard
Mar
k 1
rel
ay-b
ased
co
mp
ute
r, w
hic
h s
tore
d
4
Th
e te
rm o
rig
inat
ed f
rom
th
e H
arv
ard
Mar
k 1
rel
ay-b
ased
co
mp
ute
r, w
hic
h s
tore
d
inst
ruct
ion
s o
n p
un
ched
tap
e an
d d
ata
in r
elay
lat
ches
.
Har
var
d A
rch
itec
ture
: T
he
Har
var
d a
rch
itec
ture
use
s p
hysi
call
y s
epar
ate
mem
ori
es f
or
thei
r
inst
ruct
ion
s an
d d
ata,
req
uir
ing
ded
icat
ed b
use
s fo
r ea
ch o
f th
em.
Inst
ruct
ion
s an
d o
per
and
s
can
th
eref
ore
be
fetc
hed
sim
ult
aneo
usl
y.
Dif
fere
nt
pro
gra
m a
nd
dat
a b
us
wid
ths
are
po
ssib
le,
allo
win
g p
rog
ram
an
d d
ata
mem
ory
to
be
bet
ter
op
tim
ized
to
th
e ar
chit
ectu
ral
req
uir
em
ents
. E
.g.:
If
the
inst
ruct
ion
fo
rmat
req
uir
es
14
bit
s th
en p
rog
ram
bu
s an
d m
em
ory
can
be
mad
e 1
4-b
it w
ide,
wh
ile
the
dat
a b
us
and
dat
a m
em
ory
rem
ain
8-b
it w
ide.
AVR Microcontrollers Architecture
Som
e Adv
ance
d Micr
ocon
trolle
rs
8-b
it m
icro
co
ntr
oll
er
–A
tme
l A
VR
(A
Tm
eg
a8
)
16
-bit
mic
roc
on
tro
lle
r –
Inte
l M
CS
-96
32
-bit
mic
roc
on
tro
lle
r –
AR
M m
icro
co
ntr
oll
er
PIC
Mic
roc
on
tro
lle
r –
AVR Microcontrollers Architecture
5
� 32
-bit R
ISC
archit
ectur
e�
ARM
offer
s sev
eral m
icrop
rocess
or co
re de
signs
, inclu
ding
theAR
M7,
ARM
9,AR
M11
,Cort
ex-
AVR Microcontrollers Architecture
ARM
Micr
ocon
trolle
rs
theAR
M7,
ARM
9,AR
M11
,Cort
ex-
A8,C
ortex
-A9,
andC
ortex
-A15
.�
Optim
ized f
or im
pleme
ntatio
n in
FPGA
s6
AVR Microcontrollers Architecture
AVR Microcontrollers Architecture
Micr
ochi
p M
icroc
ontro
llers
PIC
Micr
ocon
trolle
rs
AVR Microcontrollers Architecture
7
AVR Microcontrollers Architecture
AV
R M
icro
con
tro
ller
s
AVR Microcontrollers Architecture
8
AVR Microcontrollers Architecture
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AVR Microcontrollers Architecture
9
- tin
y AVR
-meg
a AVR
-XM
EGA
AVR
-32-
bit A
VR
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ePin
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sh M
emory
Spec
ial Fe
ature
Tiny
AVR
6-32
0.5-8
KBSm
all in
size
Meg
aAVR
28-10
04-2
56KB
Exten
ded p
eriph
erals
Xmeg
aAVR
44-10
016
-384K
BDM
A , E
vent
Syste
m
AVR Microcontrollers Architecture
Xmeg
aAVR
44-10
016
-384K
BDM
A , E
vent
Syste
m inc
luded
10
AVR Microcontrollers Architecture
AVR Microcontrollers Architecture
PIC
and A
VR M
icroc
ontro
llers
•T
he P
IC (
Pro
gra
mm
able
Inte
rrupt C
ontr
olle
r) a
ppeare
d
aro
und 1
980.
→M
icro
ch
ip T
ech
no
log
y In
c.
→8
bit b
us
→
exe
cu
tes 1
in
str
uctio
n in
4 c
lkcycle
s
→H
arv
ard
arc
hite
ctu
re
AVR Microcontrollers Architecture
11
•A
VR
(1994)
→A
tme
l corp
ora
tio
n
→
8 b
it b
us
→o
ne
in
str
uctio
n p
er
cycle
→H
arv
ard
arc
hite
ctu
re
AVR Microcontrollers Architecture
�8���
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arva
rd A
rchi
tectu
re M
icroc
ontro
ller
AVR Microcontrollers Architecture
12
AVR Microcontrollers Architecture
Bloc
k diag
ram
of th
e AVR
MCU
Arc
hitec
ture
AVR Microcontrollers Architecture
13
SIM
PLIF
IED
INTE
RNAL
ARCH
ITEC
TURE
OFAT
MEG
A8
�T
he
ce
ntr
al
fea
ture
is t
he
AV
R c
ore
co
nsis
tin
g A
LU
,
32
ge
ne
ra
l p
urp
ose
re
gis
ters i
nclu
din
g t
hre
e
ind
ex
re
gis
ters, p
ro
ce
sso
r
14
ind
ex
re
gis
ters, p
ro
ce
sso
r
sta
tus r
eg
iste
r, sta
ck
po
inte
r a
nd
pro
gra
m
co
un
ter w
ith
in
str
ucti
on
re
gis
ter a
nd
in
str
ucti
on
de
co
de
r.
SOM
EIM
PORT
ANT
FEAT
URES
OFAT
MEG
A8�
8-b
it a
dvan
ced
RIS
C a
rch
itect
ure
.
�R
egis
ter
to r
egis
ter
arc
hit
ect
ure
wit
hou
t
an
y a
ccu
mu
lato
r.
�130 i
nst
ruct
ion
s in
clu
din
g s
ign
ed
an
d
un
sign
ed
mu
ltip
lica
tion
.
�32 g
en
era
l p
urp
ose
8-b
it r
egis
ters
.
�F
ull
y s
tati
c to
16 M
Hz o
pera
tion
al
frequ
en
cy.
15
frequ
en
cy.
�8K
byte
s on
-ch
ip f
lash
pro
gra
m m
em
ory
.
�1K
byte
s on
-ch
ip S
RA
M f
or
data
sto
rage.
�512 b
yte
s on
-ch
ip E
EP
RO
M.
�P
rogra
mm
ing l
ock
for
soft
ware
secu
rity
.
�23 p
rogra
mm
able
I/O
lin
es.
AVR Microcontrollers Architecture
�T
wo
8-b
it a
nd
on
e 1
6-b
it
Tim
ers/C
ou
nte
rs.
�S
ix-c
ha
nn
el
10-b
it o
n-c
hip
AD
C.
�P
ro
gra
mm
ab
le s
eria
l U
SA
RT
.
�S
PI
seria
l in
terfa
ce.
�W
atc
hd
og
tim
er w
ith
sep
ara
te o
n-
ch
ip o
scil
lato
r.
�O
n-c
hip
an
alo
g c
om
pa
ra
tor.
SOM
EIM
PORT
ANT
FEAT
URES
OFAT
MEG
A8 (�
��)
AVR Microcontrollers Architecture
16
�O
n-c
hip
an
alo
g c
om
pa
ra
tor.
�E
xte
rn
al
an
d i
nte
rn
al
inte
rru
pt
so
urces.
�F
ive s
leep
mo
des f
or p
ow
er
ma
na
gem
en
t.
AVR Microcontrollers Architecture
PIN
SA
ND
SIG
NA
LS
OF
AT
ME
GA
8
�N
ote
th
at
all
23
I/O
lin
es h
av
e
alt
ern
ate
fun
cti
on
s.
�F
ive
po
we
r i
np
ut
AVR Microcontrollers Architecture
17
�F
ive
po
we
r i
np
ut
lin
es.
�E
xte
rn
al
cry
sta
l
an
d r
ese
t a
re
no
t
esse
nti
al.
AVR Microcontrollers Architecture
OPER
ATIN
GVO
LTAG
EAN
DPO
WER
CONS
UMPT
ION
�O
pera
tin
g v
olt
age o
f
�A
Tm
ega
8:
4.5
V t
o 5
.5V
�A
Tm
ega
8L
: 2
.7V
to 5
.5V
�A
t 4
Mh
zw
ith
3 v
olt
s it
con
sum
es
3.6
mA
, re
du
ced
to 1
mA
in i
dle
mod
e a
nd
0.5
uA
in p
ow
er-
dow
n m
od
e.
AVR Microcontrollers Architecture
18
�E
ach
port
pin
of
AT
mega
8L
is
cap
ab
le o
f so
urc
ing o
r si
nk
ing
20
mA
curr
en
t a
t 5
V a
nd
10
mA
curr
en
t a
t 3
V.
N
ote
th
e i
den
tica
l so
urc
ing a
s w
ell
as
sin
kin
g c
ap
ab
ilit
ies.
AVR Microcontrollers Architecture
Prog
ram
Mem
ory (
Flas
h)
Th
e F
lash
mem
ory
has
an
en
du
ran
ce o
f at
le
ast
10
,00
0 w
rite
/era
se c
ycl
es.
Th
e A
Tm
ega8
A P
rogra
m C
ou
nte
r (P
C)
is
12
bit
s w
ide,
th
us
add
ress
ing t
he
4K
AVR Microcontrollers Architecture
19
12
bit
s w
ide,
th
us
add
ress
ing t
he
4K
P
rogra
m m
emo
ry l
oca
tion
s
ab� Fl
ash Q$
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AVR Microcontrollers Architecture
MAP
OFAT
MEG
A8 P
ROGR
AMM
EMOR
Y(F
LASH
)
�Pr
ogram
mem
ory is
arran
ged a
s 4K
words
as AT
mega
8 opc
odes
are
eithe
r 16-b
it or 3
2-bit.
�Th
e prog
ram m
emory
is di
vided
int
o two
secti
ons :
boot
and
AVR Microcontrollers Architecture
20
into t
wo se
ction
s : bo
otan
d ap
plica
tion
for so
ftware
sec
urity.
AVR Microcontrollers Architecture
SRAM
Dat
a Mem
ory a
nd R
egist
er
Dat
a M
emo
ry M
ap
AVR Microcontrollers Architecture
21
8 b
its
AVR Microcontrollers Architecture
ORGA
NIZA
TION
OF11
20 BY
TES
OFSR
AM D
ATA
MEM
ORY
�D
ata
mem
ory
(S
RA
M)
acc
om
mod
ate
s gen
era
l p
urp
ose
regis
ters
, I/
O
regis
ters
an
d s
cratc
h p
ad
are
a.
I/O
regis
ters
are
sim
ilar
to
AVR Microcontrollers Architecture
22
�I/
O r
egis
ters
are
sim
ilar
to
the S
peci
al
Fu
nct
ion
R
egis
ters
(S
FR
s) o
f 8051.
�I/
O r
egis
ters
have t
wo s
ets
of
ad
dre
sses.
AVR Microcontrollers Architecture
AVR
CPU
Gene
ral P
urpo
se W
orki
ng R
egist
ers
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The X
-regis
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gister
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AVR Microcontrollers Architecture
24
AVR Microcontrollers Architecture
DETA
ILS
OFST
ATUS
REGI
STER
(SRE
G) O
FAT
MEG
A8
�C
: ca
rry
�Z
: ze
ro
�N
: n
eg
ati
ve
�V
: 2
’s c
om
ple
me
nt
ov
erfl
ow
•S
: s
ign
•H
: h
alf
ca
rry
•T
: b
it c
op
y s
tora
ge
•I:
glo
ba
l in
terr
up
t
AVR Microcontrollers Architecture
25
ov
erfl
ow
dis
ab
le
AVR Microcontrollers Architecture
Stat
us R
egist
er
Bit
7–
I: G
lob
al
Inte
rru
pt
En
ab
le
Th
e G
lob
al I
nte
rru
pt
En
able
bit
mu
st b
e se
t fo
r th
e in
terr
up
ts t
o b
e en
able
d. T
he
ind
ivid
ual
inte
rru
pt
enab
le c
on
tro
l is
th
en p
erfo
rmed
in
sep
arat
e co
ntr
ol
reg
iste
rs.
If t
he
Glo
bal
In
terr
up
t
En
able
Reg
iste
r is
cle
ared
, n
on
e o
f th
e in
terr
up
ts a
re e
nab
led
in
dep
end
ent
of
the
ind
ivid
ual
inte
rru
pt
enab
le s
etti
ng
s. T
he
I-b
it i
s cl
eare
d b
y h
ard
war
e af
ter
an i
nte
rru
pt
has
occ
urr
ed,
and
is
set
by t
he
RE
TI
inst
ruct
ion
to
en
able
su
bse
qu
ent
inte
rru
pts
. T
he
I-b
it c
an a
lso
be
set
and
cle
ared
by
the
app
lica
tio
n w
ith
th
e S
EI
and
CL
I in
stru
ctio
ns,
as
des
crib
ed i
n t
he
Inst
ruct
ion
Set
Ref
eren
ce.
• B
it6
–T
: B
it C
op
y S
tora
ge
AVR Microcontrollers Architecture
26
• B
it6
–T
: B
it C
op
y S
tora
ge
Th
e B
it C
op
y i
nst
ruct
ion
s B
LD
(B
it L
oaD
) an
d B
ST
(B
it S
To
re)
use
th
e T
-bit
as
sou
rce
or
des
tin
atio
n f
or
the
op
erat
ed b
it. A
bit
fro
m a
reg
iste
r in
th
e R
egis
ter
Fil
e ca
n b
e co
pie
d i
nto
T b
y
the
BS
T i
nst
ruct
ion
, an
d a
bit
in
T c
an b
e co
pie
d i
nto
a b
it i
n a
reg
iste
r in
th
e R
egis
ter
Fil
e b
y t
he
BL
D i
nst
ruct
ion
.
• B
it5
–H
: H
alf
Ca
rry
Fla
g
Th
e H
alf
Car
ry F
lag
H i
nd
icat
es a
Hal
f C
arry
in
so
me
arit
hm
etic
op
erat
ion
s. H
alf
Car
ry i
s u
sefu
lin
BC
D a
rith
meti
c.
See
th
e “In
stru
ctio
n S
et D
escr
ipti
on
” fo
r d
etai
led
in
form
atio
n.
Stat
us R
egist
er
• B
it 4
–S
: S
ign
Bit
, S
= N
⊕V
Th
e S
-bit
is
alw
ays
an e
xcl
usi
ve
or
bet
wee
n t
he
Neg
ativ
e F
lag
N a
nd
th
e T
wo
’s C
om
ple
men
t
Ov
erfl
ow
Fla
g V
. S
ee t
he
“In
stru
ctio
n S
et D
escr
ipti
on
” fo
r d
etai
led
in
form
ati
on
.
• B
it 3
–V
: T
wo
’s C
om
ple
men
t O
ver
flo
w F
lag
Th
e T
wo
’s C
om
ple
men
t O
ver
flo
w F
lag
V s
up
po
rts
two
’s c
om
ple
men
t ar
ith
met
ics.
See
th
e
“In
stru
ctio
n S
et D
escr
ipti
on
” fo
r d
etai
led
in
form
atio
n.
• B
it 2
–N
: N
egat
ive
Fla
g
27
• B
it 2
–N
: N
egat
ive
Fla
g
Th
e N
egat
ive
Fla
g N
in
dic
ates
a n
egat
ive
resu
lt i
n a
n a
rith
meti
c o
r lo
gic
op
erat
ion
. S
ee t
he
“In
stru
ctio
n S
et D
escr
ipti
on
” fo
r d
etai
led
in
form
atio
n.
• B
it 1
–Z
: Z
ero
Fla
g
Th
e Z
ero
Fla
g Z
in
dic
ates
a z
ero
res
ult
in
an
ari
thm
etic
or
log
ic o
per
atio
n.
See
th
e “In
stru
ctio
n
Set
Des
crip
tio
n”
for
det
aile
d i
nfo
rmat
ion
.
• B
it 0
–C
: C
arry
Fla
g
Th
e C
arry
Fla
g C
in
dic
ates
a C
arry
in
an
ari
thm
etic
or
log
ic o
per
atio
n.
See
th
e “In
stru
ctio
n S
et
Des
crip
tio
n”
for
det
aile
d i
nfo
rmat
ion
.
AVR Microcontrollers Architecture
STAC
KAN
DST
ACK
POIN
TER
�S
tack
ma
y b
e l
oca
ted
an
yw
he
re
wit
hin
up
pe
r 1
02
4
by
tes o
f S
RA
M. L
ow
er 9
6 b
yte
s (
re
gis
ter a
re
a)
mu
st
no
t b
e o
ccu
pie
d b
y s
tack
.
�1
6-b
it s
tack
po
inte
r c
on
tain
s t
wo
8-b
it r
eg
iste
rs,
SP
H a
nd
SP
L.
�P
US
H c
om
ma
nd
de
cre
ase
s t
he
sta
ck
po
inte
r a
nd
AVR Microcontrollers Architecture
28
�P
US
H c
om
ma
nd
de
cre
ase
s t
he
sta
ck
po
inte
r a
nd
PO
P c
om
ma
nd
in
cre
ase
s i
t.
�In
ge
ne
ra
l, t
he
sta
ck
po
inte
r t
o b
e i
nit
iali
ze
d b
y t
he
hig
he
st
ad
dre
ss o
f S
RA
M.
AVR Microcontrollers Architecture
SPH
and S
PL d
Stac
k Poin
ter H
igh an
d Low
Reg
ister AVR Microcontrollers Architecture
29
AVR Microcontrollers Architecture
Stac
k Poin
ter In
struc
tions
AVR Microcontrollers Architecture
30
AVR Microcontrollers Architecture
POW
ERM
ANAG
EMEN
T AND
SLEE
PM
ODES
�A
Tm
eg
a8
off
ers f
ive
sle
ep
mo
de
s f
or
eff
icie
nt
po
we
r m
an
ag
em
en
t. T
he
y a
re
:
�Id
le m
od
e
�A
DC
no
ise
re
du
cti
on
mo
de
�P
ow
er-d
ow
n m
od
e
Po
we
r-s
av
e m
od
e, a
nd
AVR Microcontrollers Architecture
31
�P
ow
er-s
av
e m
od
e, a
nd
�S
tan
db
y m
od
e.
�S
LE
EP
in
str
ucti
on
ev
ok
es t
he
sle
ep
mo
de
.
AVR Microcontrollers Architecture
SYST
EMRE
SET
�Fo
ur so
urce
s of r
eset
for A
Tmeg
a8 ar
e:
�Po
wer-o
n res
et
�Ex
terna
l res
et
�W
atch
dog r
eset,
and
AVR Microcontrollers Architecture
32
Wat
chdo
g res
et, an
d
�Br
own-
out r
eset.
�Al
l I/O
regis
ters a
re in
itiali
zed a
nd ex
ecut
ion st
arts
from
the
rese
t vec
tor.
�M
CUCS
R re
gister
hold
s the
info
rmat
ion ab
out t
he so
urce
of
rese
t.
AVR Microcontrollers Architecture
WAT
CHDO
GTI
MER
�Op
erated
by a
separa
te int
ernal
oscil
lator
of 1 M
Hz fr
eque
ncy.
�M
ay be
enab
led or
disab
led th
rough
its re
gister
WDT
CR.
�Ge
nerat
es sy
stem
reset
at ter
mina
l cou
nt.�
Usefu
l to av
oid xh
angin
gy sy
stem.
AVR Microcontrollers Architecture
33
Usefu
l to av
oid xh
angin
gy sy
stem.
�To
be lo
aded
perio
dicall
y to a
void
syste
m res
et.
AVR Microcontrollers Architecture
Syste
m C
lock a
nd C
lock O
ption
sAVR Microcontrollers Architecture
34
AVR Microcontrollers Architecture
Syste
m C
lock a
nd C
lock O
ption
s
Cloc
k sou
rce ca
n be s
electe
d via
I/O re
gister
AVR Microcontrollers Architecture
35
•Cl
ock s
ource
can b
e sele
cted v
ia I/O
regis
ter•
Chan
ging c
lock s
ource
requ
ires t
ime t
o stab
ilize f
reque
ncy
•Ad
justin
g cloc
k freq
uenc
y mak
es tra
de-of
f betw
een p
rocess
ingpo
wer a
nd po
wer c
onsu
mptio
n
