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VLSI DESIGN STYLES
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VLSI Design Styles
Full Custom Design Semi Custom Design
Standard Cell basedDesign
Gate Array basedDesign
Channel less GateArray
Channeled GateArray
Structured GateArray
Programmable
Programmable LogicDevices(PLA,CPLD
etc)FPGA
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FIELD PROGRAMMABLE GATE ARRAY(FPGA)
Contain thousands or more no. of logic gate
with programmable interconnect
Fast prototyping and cost effective chip
design options specially for low volume
application
Not suitable for very high speed operations
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FPGA ARCHITECTURE
Typical FPGA Chip consists of:
i) Logic modules or configurable logic
block(CLB)
ii) Input output block/buffer
iii) Programmable Interconnects
Programming of interconnects performed byprogramming RAM cells whose o/p
connected to the gate of CMOS switch
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FPGA ARCHITECTURE
General Architecture of XILINX FPGA
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FPGA ARCHITECTURE
Detailed view of switch matrices &
Interconnection routing between CLBs
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FPGA MANUFACTURERS
SRAM based FPGA:
ALTERA (Example: CYCLONE-II)
Development tools: Quartus-II XILINX (Example: SPARTAN-III)
Development tools: Xilinx ISE
Anti-fuse based FPGA:ACTEL(one time programmable)
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FULL CUSTOM IC DESIGN
All Logic cells and mask layers are
customized.
It allows designers to include analog circuits,
memory cells or mechanical structure on an
IC.
Full custom Ics are most expensive to
manufacture and to design.
Manufacturing time is typically eight weeks
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FULL CUSTOM IC DESIGN FLOW
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FULL CUSTOM DESIGN FLOW
Steps:
Design Entry(Using Schematic Editor orHDL)
Logic Synthesis(Synthesis tools to create anetlist ,a description of logic cells & theirconnection)
System partitioning(Divide a large systeminto smaller parts)
Pre-layout simulation(check the design iscorrect or not)
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FULL CUSTOM DESIGN FLOW
Floor planning(Arrange the block of net list
on the chip)
Placement (Decide the location of cells in a
block)
Routing(Interconnection between blocks)
Parasitic Extraction
Post Layout Simulation
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STANDARD CELL BASED DESIGN
Predesigned logic cells (AND,OR,MUX,Flip
Flops) are available inside standard cell
library.
Mega functions , full custom blocks are
available inside library.
Chip designer defines only the placement of
cells and the interconnect
Every transistor in standard cell can be
chosen for max. speed & min area
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STANDARD CELL BASED DESIGN
Disadvantages:
Buying standard cell library
Time needed to fabricate all layers
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GATE ARRAY BASED DESIGN
Each logic cell in gate array library usesfixed size transistor known as base cell
Transistors are isolated from one array to
another by using oxide layer or by usingtransistor that is
permanently off.
Fig-> Gate array based
D flip flop module.
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Thank you