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Transistor MOS
Gilson Wirth Eng Elétrica - UFRGS
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2/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
Conteúdo
o Semicondutor o Junção PN o Capacitor MOS o Transistor MOS o Modelos Elétricos
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3 Gilson Wirth
Níveis de Abstração
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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4 Gilson Wirth
Elétrons e Lacunas
Banda de Valência
Banda de Condução
p.n = ni2
pi = ni = 1.45*1010/cm3 @ 27 C
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5 Gilson Wirth
Condutor, Semicondutor e Isolante
Al Si
SiO2
Eg=1.2eV Eg=8eV
~ 10-5 Ω *cm ~105 Ω *cm ~1015 Ω *cm
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6 Gilson Wirth
Material tipo n
Banda de Valência
Banda de Condução
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7 Gilson Wirth
Material tipo p
Banda de Valência
Banda de Condução
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8 Gilson Wirth
Elétrons e Lacunas: Condutividade do Material
Condutividade: σ = q * (mn*n + mp*p) (S/cm)
Resistividade: ρ = 1/ σ (Ω*cm) Onde q = carga do elétron mn = mobilidade do elétron (~ 1500 cm2/V para Si) mn = mobilidade da lacuna (~ 500 cm2/V para Si) n = concentração de elétrons p = concentração de lacunas
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9 Gilson Wirth
Dopagem
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10 Gilson Wirth
Elétrons e Lacunas, Campo Elétrico, Drift Current
Campo Elétrico E
F ≈ E -> I ≈ µ*V
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11 Gilson Wirth
Diffusion
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12 Gilson Wirth
PN-Junction
n
p
p
n
B A SiO 2 Al
A
B
Al
A
B
Cross-section of pn -junction in an IC process
One-dimensional representation diode symbol
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13 Gilson Wirth
PN-Junction
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14 Gilson Wirth
Creation of Depletion Regions in Unbiased Junction
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15 Gilson Wirth
Diode
hole diffusionelectron diffusion
p n
hole driftelectron drift
ChargeDensity
Distancex+
-
ElectricalxField
x
PotentialV
ξ
ρ
W2-W1
ψ0
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostaticpotential.
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16 Gilson Wirth
PN-Junction: Forward Bias
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17 Gilson Wirth
Diode: Forward Bias
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18 Gilson Wirth
PN-Junction: Reverse Bias
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19 Gilson Wirth
PN-Junction: I x V
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20 Gilson Wirth
DC (Quasi Static, Large Signal) Models
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21 Gilson Wirth
AC (Small Signal, High-Frequency) Model
C R
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22 Gilson Wirth
Diode: Junction Capacitance
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23 Gilson Wirth
pn - Junction
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24/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
Capacitor MOS
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Capacitor MOS
Porta de Poly ou Metal
Isolante (SiO2)
Substrato (Silício-p)
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Capacitor MOS
Silicio p
+ + + +
Vg < 0
Silicio p
+ ++
0<Vg < Vt
Silicio p
Vg > Vt
+ - - -
+ + + + + +
- - -
+
_ _ _ _
_ _ _ _ _
Legenda: - Aceitador Ionizado - Elétron Livre + Lacuna (móvel)
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27/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
MOSFET
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MOSFET
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MOSFET
n+ n+
p
Valência
Condução
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MOSFET
VG > 0
n+ n+
+ + + +
- - - -
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MOSFET
VG > 0
n+ n+
+ + + +
- - - -
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VG = 0 VD = 0
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VD = 0 VG = VT
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VD = 0 VG > VT
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VD > 0 VG > VT
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VD = (VG-VT) VG > VT
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MOSFET
Fonte (S) Porta (G)
Dreno (D)
VS = 0 VD > (VG-VT) VG > VT
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MOSFET: Curva ID x VD
VD
ID
VG - VT
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MOSFET
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MOSFET
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MOSFET
VG > VT
VS = 0
n+
VD ≈ 0
n+
substrato tipo-pCarga de Inversão (Qi)
xx=0 x=L
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MOSFET – Threshold Voltage
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MOSFET
VG = 5 V
VS = 0 V
n+
VD = 4 V
n+
substrato tipo-pCarga de Inversão (Qi)
xV(x=0)=0 V V(x=L)=4V
∆V=1V∆V=5V
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• Carga de inversão (densidade)
( )Q x C V V V xi ox GS T( ) ( )≅ − −
Modelo I-V quadrático básico
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• Corrente total no canal
I WQ xdV x
dxDS i= µ ( )( )
( )I C W V V V xdV x
dxDS ox GS T= − −µ ( )( )
Modelo I-V quadrático básico
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• Corrente total no canal e “beta”
( )I dx C W V V V x dVDS
L
ox GS T
VDS
0 0∫ ∫= − −µ ( )
( )I V V VV
DS GS T DSDS= − −
β.
2
2
β µ≡ CWLox
Modelo I-V quadrático básico
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( )
−−=
2.
2DS
DSTGSDSVVVVI β
Zona Linear (Triodo)
Corrente ID MOSFET
( )[ ]DSTGSDS VVVI −= .β
Zona de Saturação ( )I V VDS GS T= −β2
2.
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Características Transistor MOS
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00
Saturação
IDS/β
Zona linear
VDS=VGS -VT
VGS < VT
real
ideal
interseção VDS= -1/ λ
VGS3
VGS2
VGS1
VGS1 < VGS2 < VGS3
VDS
Para VGS >= VT VDS >= VGS –VT
( )I V VDS GS T= −β2
2.
( )I V V VDS GS T DS= − +β
λ2
12
. .( )
• Parâmetro “lambda”
Zona de saturação
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Características Transistor MOS
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Características Transistor MOS: Saturação
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Características Transistor MOS: Saturação
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Características Transistor MOS: Saturação
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Características Transistor MOS: Saturação
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Características Transistor MOS: Pequenos Sinais
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Características Transistor MOS: Pequenos Sinais
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Características Transistor MOS: Pequenos Sinais
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Características Transistor MOS: Alta Freq
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Características Transistor MOS: Alta Freq
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Características Transistor MOS: Alta Freq
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Características Transistor MOS: Alta Freq
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Resistência Parasita
W
LD
Drain
Draincontact
Polysilicon gate
DS
G
RS RD
VGS,eff
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MOSFET: SPICE Simulation
Forma Geral:
Exemplo:
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MOSFET: SPICE Simulation
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MOSFET: SPICE Simulation
As Capacitâncias de Junção são Independentes da Tensão de Operação?
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Digital MOSFET Circuits
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Digital MOSFET Circuits
VGS ≥ VT
RonS D
A Switch!
|V GS |
An MOS Transistor
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Digital MOSFET Circuits
VDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
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Interconexão
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Interconexão: Capacitância
Dielectric
Substrate
L
W
H
tdi
Electrical-field lines
Current flow
WLt
cdi
diint
ε=
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Interconexão: Capacitância
fringing parallel
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Interconexão: Resistência
W
LH
R = ρH W
L
Sheet ResistanceRo
R1 R2
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Interconexão: Resistência
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Scaling
- W e L decrease by a factor α - Depletion Width decreases by a factor α
→ All capacitances decreases by a factor α Razavi, pp. 581
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Scaling
- tox decreases by a factor α → Cox decreases by a factor α
- W and L decrease by a factor α
- Supply voltage and VTH are decreased by a factor α
→ Transconductance remains constant Obs.: If doping scales, output resistance r0 is kept constant However, dynamic range decreases.
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76/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
Traditional Scaling
IDsat ≈ ½ Coxµ(W/Lg)(VG – VT)2
Fmax = IDSAT / (VDDCox) Power = (Vdd)2CoxFmax
=εoεs/Tox
Reduce Gate Oxide Thickness
Reduce Operating Voltage (Vdd)
Reduce Physical Gate Length (Lg) Reduce Threshold
Voltage (VT)
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77/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
MOS: Traditional Scaling Limitations
Mobility: Decreasing mobility due to higher channel doping (Lowers IDsat)
Floating body: Increasing body-factor due to charge build-up (VT instability) Parasitic: Increasing junction resistance and capacitance (decreases performance)
Leakage current: Increasing off-state leakage Ig, IPT, IJ (increases stand-by power)
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78/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013 Device 78
IDsat ≈ ½ Coxµ(W/Lg)(VG – VT)2
Equivalent Scaling
Reduce parasitic capacitance and resistance
New Dev. Topology
=εoεs/Tox
Increase Gate Dielectric Constant (K) New Material
Increase Mobility (µ) Strain
3D (FinFET) New Dev.
Topology
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79/xx SIM/EMICRO 2013 Porto Alegre, Brasil - Abril/2013
Perguntas?