TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Complete PWM Power Control
3.6-V to 40-V Operation
Internal Undervoltage-Lockout Circuit
Internal Short-Circuit Protection
Oscillator Frequency . . . 20 kHz to 500 kHz
Variable Dead Time Provides Control OverTotal Range
±3% Tolerance on Reference Voltage(TL5001A)
Available in Q-Temp Automotive HighRel Automotive ApplicationsConfiguration Control / Print SupportQualification to Automotive Standards
description
The TL5001 and TL5001A incorporate on a singlemonolithic chip all the functions required for apulse-width-modulation (PWM) control circuit. De-signed primarily for power-supply control, theTL5001/A contains an error amplifier, a regulator, anoscillator, a PWM comparator with a dead-time-con-trol input, undervoltage lockout(UVLO), short-circuit protection (SCP), and an open-collector output transistor. The TL5001A has a typicalreference voltage tolerance of ±3% compared to ±5% for the TL5001.
The error-amplifier common-mode voltage ranges from 0 V to 1.5 V. The noninverting input of the error amplifieris connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by connectingan external resistor between DTC and GND. The oscillator frequency is set by terminating RT with an externalresistor to GND. During low VCC conditions, the UVLO circuit turns the output off until VCC recovers to its normaloperating range.
The TL5001C and TL5001AC are characterized for operation from –20°C to 85°C. The TL5001I and TL5001AI arecharacterized for operation from –40°C to 85°C. The TL5001Q and TL5001AQ are characterized for operation from–40°C to 125°C. The TL5001M and TL5001AM are characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA SMALL OUTLINE(D)
PLASTIC DIP(P)
CERAMIC DIP(JG)
CHIP CARRIER(FK)
20°C to 85°CTL5001CD TL5001CP — —
–20°C to 85°CTL5001ACD TL5001ACP — —
40°C to 85°CTL5001ID TL5001IP — —
–40°C to 85°CTL5001AID TL5001AIP — —
40°C to 125°CTL5001QD — — —
–40°C to 125°CTL5001AQD — — —
55°C to 125°C— — TL5001MJG TL5001MFK
–55°C to 125°C— — TL5001AMJG TL5001AMFK
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL5001CDR).
Copyright 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
OUTVCC
COMPFB
GNDRTDTCSCP
D, JG OR P PACKAGE(TOP VIEW)
192013 2
17
18
16
15
14
1312119 10
5
4
6
7
8
NC
RT
NC
DTC
NC
NC
VCC
NC
COMP
NC
NC
OU
T
NC
GN
D
NC
FB
NC
SC
P
NC
NC
FK PACKAGE(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic for typical application
TL5001/A
FB
COMP
VO
DTC
RT
VI
+
SCP
VCC
+
TPS1101
GND8
7
6
5
2
1
3
4
VO
functional block diagram
GND8
OUT
SCP
COMP
FB
5
3
4 –
+
DTCRT67
Comparator 2SCP
PWM/DTCComparator
OSC
Comparator 1SCP
AmplifierError
UVLO
VCC2 1
1 V
1.5 V 1 VReference
Voltage
IDT
2.5 V
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
voltage reference
A 2.5-V regulator operating from VCC is used to power the internal circuitry of the TL5001 and TL5001A and as areference for the error amplifier and SCP circuits. A resistive divider provides a 1-V reference for the error amplifiernoninverting input which typically is within 2% of nominal over the operating temperature range.
error amplifier
The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and generatesan error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting the error-amplifiergain (see Figure 1), using the following expression:
VO = (1 + R1/R2) (1 V)
To PWMComparator
Vref = 1 V
4VI(FB)
3
+
–
R2
R1
COMP
FB
CompensationNetwork
TL5001/A
GND8
Figure 1. Error-Amplifier Gain Setting
The error-amplifier output is brought out as COMP for use in compensating the dc-to-dc converter control loop forstability. Because the amplifier can only source 45 µA, the total dc load resistance should be 100 kΩ or more.
oscillator/PWM
The oscillator frequency (fosc) can be set between 20 kHz and 500 kHz by connecting a resistor between RT andGND. Acceptable resistor values range from 15 kΩ to 250 kΩ. The oscillator frequency can be determined by usingthe graph shown in Figure 5.
The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value ofapproximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input voltageto the triangular wave and turns the output transistor off whenever the triangular wave is greater than the lesser ofthe two inputs.
dead-time control (DTC)
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for boostand flyback converters. A current source generates a reference current (IDT) at DTC that is nominally equal to thecurrent at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates a dead-timereference voltage (VDT), which the PWM/DTC comparator compares to the oscillator triangle wave as describedin the previous section. Nominally, the maximum duty cycle is 0% when VDT is 0.7 V or less and 100% when VDTis 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the source impedance ofRT is relatively high (1250 Ω), choosing RDT for a specific maximum duty cycle, D, is accomplished using thefollowing equation and the voltage limits for the frequency in question as found in Figure 11 (Voscmax and Voscminare the maximum and minimum oscillator levels):
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dead-time control (DTC) (continued)
RDT Rt 1250 DVoscmax – Voscmin Voscmin
Where
RDT and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (CDT) as shown in Figure 2. Duringsoft start, the voltage at DTC is derived by the following equation:
VDT IDTRDT 1–e– tRDTCDT
TL5001/ADTC
CDT RDT
6
Figure 2. Soft-Start Circuit
If the dc-to-dc converter must be in regulation within a specified period of time, the time constant, RDTCDT, shouldbe t0/3 to t0/5. The TL5001/A remains off until VDT ≈ 0.7 V, the minimum ramp value. CDT is discharged every timeUVLO or SCP becomes active.
undervoltage-lockout (UVLO) protection
The undervoltage-lockout circuit turns the output transistor off and resets the SCP latch whenever the supply voltagedrops too low (approximately 3 V at 25°C) for proper operation. A hysteresis voltage of 200 mV eliminates falsetriggering on noise and chattering.
short-circuit protection (SCP)
The TL5001/A includes short-circuit protection (see Figure 3), which turns the power switch off to prevent damagewhen the converter output is shorted. When activated, the SCP prevents the switch from being turned on until theinternal latching circuit is reset. The circuit is reset by reducing the input voltage until UVLO becomes active or untilthe SCP terminal is pulled to ground externally.
When a short circuit occurs, the error-amplifier output at COMP rises to increase the power-switch duty cycle in anattempt to maintain the output voltage. SCP comparator 1 starts an RC timing circuit when COMP exceeds 1.5 V.If the short is removed and the error-amplifier output drops below 1.5 V before time out, normal converter operationcontinues. If the fault is still present at the end of the time-out period, the timer sets the latching circuit and turnsoff the TL5001/A output transistor.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-circuit protection (SCP) (continued)
Q1
12 kΩ
185 kΩRSCP
Q2
SCPComparator 2
Vref = 1 VSCPComparator 11.5 V
From Error Amp
CSCP
To OutputDrive Logic
SCP5
2.5 V
Figure 3. SCP Circuit
The timer operates by charging an external capacitor (CSCP), connected between the SCP terminal and ground,towards 2.5 V through a 185-kΩ resistor (RSCP). The circuit begins charging from an initial voltage of approximately185 mV and times out when the capacitor voltage reaches 1 V. The output of SCP comparator 2 then goes high,turns on Q2, and latches the timer circuit. The expression for setting the SCP time period is derived from the followingequation:
VSCP (2.5 0.185)1 e–t 0.185
Where
τ = RSCPCSCP
The end of the time-out period, tSCP, occurs when VSCP = 1 V. Solving for CSCP yields:
CSCP 12.46 tSCP
Where
t is in seconds, C in µF.
tSCP must be much longer (generally 10 to 15 times) than the converter start-up period or the converter will not start.
output transistor
The output of the TL5001/A is an open-collector transistor with a maximum collector current rating of 21 mA anda voltage rating of 51 V. The output is turned on under the following conditions: the oscillator triangle wave is lowerthan both the DTC voltage and the error-amplifier output voltage, the UVLO circuit is inactive, and the short-circuitprotection circuit is inactive.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 41 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplifier input voltage, VI(FB) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage, VO, OUT 51 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO, OUT 21 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output peak current, IO(peak), OUT 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating ambient temperature range, TA: TL5001C, TL5001AC –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . .
TL5001I, TL5001AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . TL5001Q, TL5001AQ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . TL5001M, TL5001AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGETA ≤ 25°C
POWER RATINGDERATING FACTORABOVE TA = 25°C
TA = 70°CPOWER RATING
TA = 85°CPOWER RATING
TA = 125°CPOWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P 1000 mW 8.0 mW/°C 640 mW 520 mW 200 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VCC 3.6 40 V
Amplifier input voltage, VI(FB) 0 1.5 V
Output voltage, VO, OUT 50 V
Output current, IO, OUT 20 mA
COMP source current 45 µA
COMP dc load resistance 100 kΩ
Oscillator timing resistor, Rt 15 250 kΩ
Oscillator frequency, fosc 20 500 kHz
TL5001C, TL5001AC –20 85
Operating ambient temperature TATL5001I, TL5001AI –40 85
°COperating ambient temperature, TATL5001Q, TL5001AQ –40 125
°C
TL5001M, TL5001AM –55 125
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,fosc = 100 kHz (unless otherwise noted)
reference
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Output voltage COMP connected to FB 0.95 1 1.05 0.97 1 1.03 V
Input regulation VCC = 3.6 V to 40 V 2 12.5 2 12.5 mV
TA = –20°C to 25°C (C suffix) –10 –1 10 –10 –1 10
Output voltage change with temperature TA = –40°C to 25°C (I suffix) –10 –1 10 –10 –1 10 mV/V
TA = 25°C to 85°C –10 –2 10 –10 –2 10† All typical values are at TA = 25°C.
undervoltage lockout
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Upper threshold voltage TA = 25°C 3 3 V
Lower threshold voltage TA = 25°C 2.8 2.8 V
Hysteresis TA = 25°C 100 200 100 200 mV
Reset threshold voltage TA = 25°C 2.1 2.55 2.1 2.55 V
† All typical values are at TA = 25°C.
short-circuit protection
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
SCP threshold voltage TA = 25°C 0.95 1.00 1.05 0.97 1.00 1.03 V
SCP voltage, latched No pullup 140 185 230 140 185 230 mV
SCP voltage, UVLO standby No pullup 60 120 60 120 mV
Input source current TA = 25°C –10 –15 –20 –10 –15 –20 µA
SCP comparator 1 threshold voltage 1.5 1.5 V
† All typical values are at TA = 25°C.
oscillator
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Frequency Rt = 100 kΩ 100 100 kHz
Standard deviation of frequency 15 15 kHz
Frequency change with voltage VCC = 3.6 V to 40 V 1 1 kHz
TA = –40°C to 25°C –4 –0.4 4 –4 –0.4 4 kHz
Frequency change with temperature TA = –20°C to 25°C –4 –0.4 4 –4 –0.4 4 kHz
TA = 25°C to 85°C –4 –0.2 4 –4 –0.2 4 kHz
Voltage at RT 1 1 V
† All typical values are at TA = 25°C.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,fosc = 100 kHz (unless otherwise noted) (continued)
dead-time control
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Output (source) currentTL5001C V(DT) = 1.5 V 0.9 × IRT‡ 1.1 × IRT 0.9 × IRT‡ 1.1 × IRT µAOutput (source) currentTL5001I V(DT) = 1.5 V 0.9 × IRT‡ 1.2 × IRT 0.9 × IRT‡ 1.2 × IRT
µA
Input threshold voltageDuty cycle = 0% 0.5 0.7 0.5 0.7
VInput threshold voltageDuty cycle = 100% 1.3 1.5 1.3 1.5
V
† All typical values are at TA = 25°C.‡ Output source current at RT
error amplifier
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Input voltage VCC = 3.6 V to 40 V 0 1.5 0 1.5 V
Input bias current –160 –500 –160 –500 nA
Output voltage swingPositive 1.5 2.3 1.5 2.3 V
Output voltage swingNegative 0.3 0.4 0.3 0.4 V
Open-loop voltage amplification 80 80 dB
Unity-gain bandwidth 1.5 1.5 MHz
Output (sink) current VI(FB) = 1.2 V, COMP = 1 V 100 600 100 600 µA
Output (source) current VI(FB) = 0.8 V, COMP = 1 V –45 –70 –45 –70 µA
† All typical values are at TA = 25°C.
output
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Output saturation voltage IO = 10 mA 1.5 2 1.5 2 V
Off state currentVO = 50 V, VCC = 0 10 10
µAOff-state currentVO = 50 V 10 10
µA
Short-circuit output current VO = 6 V 40 40 mA
† All typical values are at TA = 25°C.
total device
PARAMETER TEST CONDITIONSTL5001C, TL5001I TL5001AC, TL5001AI
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Standby supply current Off state 1 1.5 1 1.5 mA
Average supply current Rt = 100 kΩ 1.4 2.1 1.4 2.1 mA
† All typical values are at TA = 25°C.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,fosc = 100 kHz (unless otherwise noted)
reference
PARAMETER TEST CONDITIONS
TL5001Q,TL5001M
TL5001AQ,TL5001AM UNIT
MIN TYP† MAX MIN TYP† MAX
Output voltageTA = 25°C
COMP connected to FB0.95 1.00 1.05 0.97 1.00 1.03
VOutput voltageTA = MIN to MAX
COMP connected to FB0.93 0.98 1.07 0.94 0.98 1.06
V
Input regulation TA = MIN to MAX VCC = 3.6 V to 40 V 2 12.5 2 12.5 mV
Output voltage change with temper-ature
TA = MIN to MAX *–6 2 *6 *–6 2 *6 %
† All typical values are at TA = 25°C.*Not production tested.
undervoltage lockout
PARAMETER TEST CONDITIONSTL5001Q,TL5001M
TL5001AQ,TL5001AM UNITPARAMETER TEST CONDITIONS
MIN TYP† MAX MIN TYP† MAXUNIT
Upper threshold voltageTA = MIN, 25°C 3.00 3.00
VUpper threshold voltageTA = MAX 2.55 2.55
V
Lower threshold voltageTA = MIN, 25°C 2.8 2.8
VLower threshold voltageTA = MAX 2.0 2.0
V
Hysteresis TA = MIN to MAX 100 200 100 200 mV
Reset threshold voltageTA = MIN, 25°C 2.10 2.55 2.10 2.55
VReset threshold voltageTA = MAX 0.35 0.63 0.35 0.63
V
† All typical values are at TA = 25°C.
short-circuit protection
PARAMETER TEST CONDITIONS
TL5001Q,TL5001M
TL5001AQ,TL5001AM UNIT
MIN TYP† MAX MIN TYP† MAX
SCP threshold voltageTA = MIN, 25°C 0.95 1.00 1.05 0.97 1.00 1.03
VSCP threshold voltageTA = MAX 0.93 0.98 1.07 0.94 0.98 1.06
V
SCP voltage, latched TA = MIN to MAX No pullup 140 185 230 140 185 230 mV
SCP voltage, UVLO standby TA = MIN to MAX No pullup 60 120 60 120 mV
Equivalent timing resistance TA = MIN to MAX 185 185 kΩ
SCP comparator 1 threshold voltage TA = MIN to MAX 1.5 1.5 V
† All typical values are at TA = 25°C.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,fosc = 100 kHz (unless otherwise noted) (continued)
oscillator
PARAMETER TEST CONDITIONS
TL5001Q,TL5001M
TL5001AQ,TL5001AM UNIT
MIN TYP† MAX MIN TYP† MAX
Frequency TA = MIN to MAX Rt = 100 kΩ 100 100 kHz
Standard deviation of frequency TA = MIN to MAX 2 2 kHz
Frequency change with voltage TA = MIN to MAX VCC = 3.6 V to 40 V 1 1 kHz
Frequency change with TA = MIN to MAXQ suffix *–6 3 *6 *–6 3 *6
kHzFrequency change with temperature TA = MIN to MAX
M suffix *–9 5 *9 *–9 5 *9kHz
Voltage at RT TA = MIN to MAX 1 1 V
† All typical values are at TA = 25°C.*Not production tested.
dead-time control
PARAMETER TEST CONDITIONSTL5001Q, TL5001M TL5001AQ, TL5001AM
UNITPARAMETER TEST CONDITIONSMIN TYP† MAX MIN TYP† MAX
UNIT
Output (source) current TA = MIN to MAX V(DT) = 1.5 V 0.9 × IRT‡ 1.1 × IRT 0.9 × IRT‡ 1.1 × IRT µA
TA = 25°CDuty cycle = 0% 0.5 0.7 0.5 0.7
Input threshold TA = 25°C
Duty cycle = 100% 1.3 1.5 1.3 1.5Vvoltage
TA = MIN to MAXDuty cycle = 0% 0.4 0.7 0.4 0.7
V
TA = MIN to MAXDuty cycle = 100% 1.3 1.7 1.3 1.7
† All typical values are at TA = 25°C.‡ Output source current at RT
error amplifier
PARAMETER TEST CONDITIONSTL5001Q,TL5001M
TL5001AQ,TL5001AM UNITPARAMETER TEST CONDITIONS
MIN TYP† MAX MIN TYP† MAXUNIT
Input bias current TA = MIN to MAX –160 –500 –160 –500 nA
Output voltage PositiveTA = MIN to MAX
1.5 2.3 1.5 2.3 VOut ut voltageswing Negative
TA = MIN to MAX0.3 0.4 0.3 0.4 V
Open-loop voltage amplification TA = MIN to MAX 80 80 dB
Unity-gain bandwidth TA = MIN to MAX 1.5 1.5 MHz
Output (sink) current TA = MIN to MAX VI(FB) = 1.2 V, COMP = 1 V 100 600 100 600 µA
Output (source) currentTA = MIN, 25°C
VI(FB) = 0 8 V COMP = 1 V–45 –70 –45 –70
µAOutput (source) currentTA = MAX
VI(FB) = 0.8 V, COMP = 1 V–30 –45 –30 –45
µA
† All typical values are at TA = 25°C.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,fosc = 100 kHz (unless otherwise noted) (continued)
output
PARAMETER TEST CONDITIONS
TL5001Q,TL5001M
TL5001AQ,TL5001AM UNIT
MIN TYP† MAX MIN TYP† MAX
Output saturation voltage TA = MIN to MAX IO = 10 mA 1.5 2 1.5 2 V
Off state current TA = MIN to MAXVO = 50 V, VCC = 0 10 10
µAOff-state current TA = MIN to MAXVO = 50 V 10 10
µA
Short-circuit output current TA = MIN to MAX VO = 6 V 40 40 mA
† All typical values are at TA = 25°C.
total device
PARAMETER TEST CONDITIONSTL5001Q,TL5001M
TL5001AQ,TL5001AM UNITPARAMETER TEST CONDITIONS
MIN TYP† MAX MIN TYP† MAXUNIT
Standby supply current Off state TA = MIN to MAX 1 1.5 1 1.5 mA
Average supply current TA = MIN to MAX Rt = 100 kΩ 1.4 2.1 1.4 2.1 mA
† All typical values are at TA = 25°C.
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
2.3 V
SCP Timing Period
3 V
DTCOSC
COMP
1 V
0 V
PWM/DTCComparator
OUT
SCPComparator 1
SCP
SCPComparator 2
VCC
1.5 V
NOTE A: The waveforms show timing characteristics for an intermittent short circuit and a longer short circuit that is sufficient to activate SCP.
Figure 4. PWM Timing Diagram
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
100 k
10 k
1 M
10 k 100 k 1 M
f
VCC = 6 VDT Resistance = RtTA = 25°C
Rt – Timing Resistance – Ω
OSCILLATOR FREQUENCYvs
TIMING RESISTANCE
– O
scill
ato
r F
req
uen
cy –
Hz
osc
Figure 6
94
92
90
88– 50 – 25 0
96
98
100
25 50 75 100
TA – Ambient Temperature – °C
OSCILLATION FREQUENCYvs
AMBIENT TEMPERATURE
f –
Osc
illat
ion
Fre
qu
ency
– k
Hz
osc
VCC = 6 VRt = 100 kΩDT Resistance = 100 kΩ
Figure 7
REFERENCE OUTPUT VOLTAGEvs
POWER-SUPPLY VOLTAGE
– R
efer
ence
Ou
tpu
t V
olt
age
– V
Vre
f
VCC – Power-Supply Voltage – V
1
0.8
0.4
0.2
0
1.8
0.6
0 1 2 3 4 5 6
1.4
1.2
1.6
2
7 8 9 10
TA = 25°CFB and COMPConnected Together
Figure 8
– R
efer
ence
Ou
tpu
t V
olt
age
Flu
ctu
atio
n –
%
TA – Ambient Temperature – °C
∆V
ref
REFERENCE OUTPUT VOLTAGE FLUCTUATIONvs
AMBIENT TEMPERATURE
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
– 0.2
– 0.4
– 0.8– 50 – 25 0
0.2
0.4
0.6
25 50 75 100
0
VCC = 6 VFB and COMP Connected Together
– 0.6
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
1
0.5
0
2
1.5
0 10 20 30 40
– A
vera
ge
Su
pp
ly C
urr
ent
– m
A
VCC – Power-Supply Voltage – V
Rt = 100 kΩTA = 25 °C
AVERAGE SUPPLY CURRENTvs
POWER-SUPPLY VOLTAGE
I CC
Figure 10
1
0.9
0.8
0– 50 – 25 0
– A
vera
ge
Su
pp
ly C
urr
ent
– m
A
1.1
1.2
1.3
25 50 75 100
TA – Ambient Temperature – °C
VCC = 6 VRt = 100 kΩDT Resistance = 100 kΩ
I CC
AVERAGE SUPPLY CURRENTvs
AMBIENT TEMPERATURE
Figure 11
1.5
1.2
0.6
0.3
0
1.8
0.9
10 k 100 k 1 M 10 M
PW
M T
rian
gle
Wav
e A
mp
litu
de
Vo
ltag
e –
V
fosc – Oscillator Frequency – Hz
Voscmin (zero duty cycle)
VCC = 6 VTA = 25 °C
PWM TRIANGLE WAVE AMPLITUDE VOLTAGEvs
OSCILLATOR FREQUENCY
Voscmax (100% duty cycle)
Figure 12
ERROR AMPLIFIER OUTPUT VOLTAGEvs
OUTPUT (SINK) CURRENT
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
VV
O
IO – Output (Sink) Current – mA
1.5
1
0.5
00 0.2 0.4
2
2.5
3
0.6
VCC = 6 VVI(FB) = 1.2 VTA = 25 °C
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
1.5
1
0.5
00 20 40
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
V
2
2.5
3
60 80 100 120
VO
IO – Output (Source) Current – µA
VCC = 6 VVI(FB) = 0.8 VTA = 25 °C
ERROR AMPLIFIER OUTPUT VOLTAGEvs
OUTPUT (SOURCE) CURRENT
Figure 14
2.43
2.42
2.41
2.40– 50 – 25 0
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
V
2.44
2.45
2.46
25 50 75 100
VO
TA – Ambient Temperature – °C
VCC = 6 VVI(FB) = 0.8 VNo Load
ERROR AMPLIFIER OUTPUT VOLTAGEvs
AMBIENT TEMPERATURE
Figure 15
180
160
140
120– 50 – 25 0
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
mV
200
220
240
25 50 75 100
VO
TA – Ambient Temperature – °C
VCC = 6 VVI(FB) = 1.2 VNo Load
ERROR AMPLIFIER OUTPUT VOLTAGEvs
AMBIENT TEMPERATURE
Figure 16
30
20
0
– 10
– 20
40
10
10 k 100 k 1 M 10 M
– E
rro
r A
mp
lifie
r O
pen
-Lo
op
Gai
n –
dB
f – Frequency – Hz
VCC = 6 VTA = 25 °C
AV
Err
or
Am
plif
ier
Op
en-L
oo
p P
has
e S
hif
t
φ
AV
ERROR AMPLIFIER OPEN-LOOP GAIN ANDPHASE SHIFT
vsFREQUENCY
–180°
–210°
–240°
–270°
–300°
–330°
–360°
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
60
40
20
00 0.5 1
80
100
120
1.5 2DTC Voltage – V
OUTPUT DUTY CYCLEvs
DTC VOLTAGE
Ou
tpu
t D
uty
Cyc
le –
%
VCC = 6 VRt = 100 kΩTA = 25 °C
Figure 18
6
4
2
00 20 40
– S
CP
Tim
e-O
ut
Per
iod
– m
s
8
10
12
60 80 100 120
VCC = 6 VRt = 100 kΩDT Resistance = 200 kΩTA = 25 °C
CSCP – SCP Capacitance – nF
t SC
P
SCP TIME-OUT PERIODvs
SCP CAPACITANCE
Figure 19
– 30
– 20
– 10
00 – 10 – 20
– D
TC
Ou
tpu
t C
urr
ent
–
– 40
– 50
– 60
– 30 – 40 – 50 – 60
DT Voltage = 1.3 VTA = 25 °C
IO – RT Output Current – µA
Aµ
I O(D
T)
DTC OUTPUT CURRENTvs
RT OUTPUT CURRENT
Figure 20
1
0.5
0
2
1.5
0 5 10 15 20
– O
utp
ut
Sat
ura
tio
n V
olt
age
– V
IO – Output (Sink) Current – mA
VC
E
VCC = 6 VTA = 25 °C
OUTPUT SATURATION VOLTAGEvs
OUTPUT (SINK) CURRENT
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
U1TL5001/A
FB
COMP
VO
DTC
RT
GND
C1100 µF
10 V
VI5 V
+ R1470 Ω
SCP
VCC
L120 µH
C2100 µF
10 V
3.3 V
GND
+
CR1MBRS140T3
Q1TPS1101
C60.012 µF
R45.1 kΩ
R57.50 kΩ1%
R256 kΩ
R343 kΩ
R63.24 kΩ1%
C50.1 µF
C41 µF
C30.1 µF
GND
8
7
6
5
2
1
3
4
Partial Bill of Materials:U1 TL5001/A Texas InstrumentsQ1 TPS1101 Texas InstrumentsLI CTX20-1 or Coiltronics
23 turns of #28 wire onMicrometals No. T50-26B core
C1 TPSD107M010R0100 AVXC2 TPSD107M010R0100 AVXCR1 MBRS140T3 Motorola
R72.0 kΩ
C70.0047 µF
+
NOTES: A. Frequency = 200 kHzB. Duty cycle = 90% maxC. Soft-start time constant (TC) = 5.6 msD. SCP TC = 70 msA
Figure 21. Step-Down Converter
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATAD (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)0.244 (6,20)
0.069 (1,75) MAX0.010 (0,25)0.004 (0,10)
1
14
0.014 (0,35)0.020 (0,51)
A
0.157 (4,00)0.150 (3,81)
7
8
0.044 (1,12)0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189(4,80)
(5,00)0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394(10,00)
0.386
0.004 (0,10)
M0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: B. All linear dimensions are in inches (millimeters).C. This drawing is subject to change without notice.D. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).E. Falls within JEDEC MS-012
TL5001, TL5001APULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084F – APRIL 1994 – REVISED JANUARY 2002
19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATAFK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/C 11/95
28 TERMINALS SHOWN
B
0.358(9,09)
MAX
(11,63)
0.560(14,22)
0.560
0.458
0.858(21,8)
1.063(27,0)
(14,22)
ANO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342(8,69)
MIN
(11,23)
(16,26)0.640
0.740
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)0.938
(28,99)1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)0.064 (1,63)
(7,80)0.307
(10,31)0.406
(12,58)0.495
(12,58)0.495
(21,6)0.850
(26,6)1.047
0.045 (1,14)
0.045 (1,14)0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
121314151618 17
11
10
8
9
7
5
432
0.020 (0,51)0.010 (0,25)
6
12826 27
19
21B SQ
A SQ22
23
24
25
20
0.055 (1,40)0.045 (1,14)
0.028 (0,71)0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a metal lid.D. The terminals are gold-plated.E. Falls within JEDEC MS-004
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
5962-9958301QPA ACTIVE CDIP JG 8 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 9958301QPATL5001M
5962-9958302Q2A ACTIVE LCCC FK 20 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 5962-9958302Q2ATL5001AMFKB
5962-9958302QPA ACTIVE CDIP JG 8 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 9958302QPATL5001AM
TL5001ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -20 to 85 5001AC
TL5001AID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001AI
TL5001AIP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL5001AIP
TL5001AMFKB ACTIVE LCCC FK 20 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 5962-9958302Q2ATL5001AMFKB
TL5001AMJGB ACTIVE CDIP JG 8 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 9958302QPATL5001AM
TL5001AQD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ
TL5001AQDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 5001AQ
TL5001AQDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5001AQ
TL5001AQDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 5001AQ
TL5001CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
PACKAGE OPTION ADDENDUM
www.ti.com 5-Dec-2021
Addendum-Page 2
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
TL5001CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 5001C
TL5001CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 TL5001CP
TL5001CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM T5001
TL5001CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 T5001
TL5001ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 5001I
TL5001IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL5001IP
TL5001IPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL5001IP
TL5001IPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM Z5001
TL5001MJG ACTIVE CDIP JG 8 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 TL5001MJG
TL5001MJGB ACTIVE CDIP JG 8 1 Non-RoHS& Green
SNPB N / A for Pkg Type -55 to 125 9958301QPATL5001M
TL5001QD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q
TL5001QDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 5001Q
TL5001QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5001Q
TL5001QDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 5001Q
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Dec-2021
Addendum-Page 3
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL5001, TL5001A, TL5001AM, TL5001M :
• Catalog : TL5001A, TL5001
• Automotive : TL5001A-Q1, TL5001A-Q1
• Military : TL5001M, TL5001AM
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 5-Dec-2021
Addendum-Page 4
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
TL5001ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AQDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001AQDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1
TL5001IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001IPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.5 12.0 16.0 Q1
TL5001QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TL5001QDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL5001ACDR SOIC D 8 2500 340.5 336.1 25.0
TL5001AIDR SOIC D 8 2500 340.5 336.1 25.0
TL5001AQDR SOIC D 8 2500 350.0 350.0 43.0
TL5001AQDRG4 SOIC D 8 2500 350.0 350.0 43.0
TL5001CDR SOIC D 8 2500 340.5 336.1 25.0
TL5001CPSR SO PS 8 2000 853.0 449.0 35.0
TL5001IDR SOIC D 8 2500 340.5 336.1 25.0
TL5001IPSR SO PS 8 2000 853.0 449.0 35.0
TL5001QDR SOIC D 8 2500 350.0 350.0 43.0
TL5001QDRG4 SOIC D 8 2500 350.0 350.0 43.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
TUBE
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9958302Q2A FK LCCC 20 1 506.98 12.06 2030 NA
TL5001ACD D SOIC 8 75 507 8 3940 4.32
TL5001AID D SOIC 8 75 507 8 3940 4.32
TL5001AIDG4 D SOIC 8 75 507 8 3940 4.32
TL5001AIP P PDIP 8 50 506 13.97 11230 4.32
TL5001AMFKB FK LCCC 20 1 506.98 12.06 2030 NA
TL5001AQD D SOIC 8 75 505.46 6.76 3810 4
TL5001AQDG4 D SOIC 8 75 505.46 6.76 3810 4
TL5001CD D SOIC 8 75 507 8 3940 4.32
TL5001CDG4 D SOIC 8 75 507 8 3940 4.32
TL5001CP P PDIP 8 50 506 13.97 11230 4.32
TL5001CPS PS SOP 8 80 530 10.5 4000 4.1
TL5001ID D SOIC 8 75 507 8 3940 4.32
TL5001IP P PDIP 8 50 506 13.97 11230 4.32
TL5001IPE4 P PDIP 8 50 506 13.97 11230 4.32
TL5001QD D SOIC 8 75 505.46 6.76 3810 4
TL5001QDG4 D SOIC 8 75 505.46 6.76 3810 4
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 3
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP[5.80-6.19]
.069 MAX[1.75]
6X .050[1.27]
8X .012-.020 [0.31-0.51]
2X.150[3.81]
.005-.010 TYP[0.13-0.25]
0 - 8 .004-.010[0.11-0.25]
.010[0.25]
.016-.050[0.41-1.27]
4X (0 -15 )
A
.189-.197[4.81-5.00]
NOTE 3
B .150-.157[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)[1.04]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
54
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX[0.07]ALL AROUND
.0028 MIN[0.07]ALL AROUND
(.213)[5.4]
6X (.050 )[1.27]
8X (.061 )[1.55]
8X (.024)[0.6]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILS
EXPOSEDMETAL
OPENINGSOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASKDEFINED
EXPOSEDMETAL
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
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1
45
8
SEEDETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )[1.55]
8X (.024)[0.6]
6X (.050 )[1.27]
(.213)[5.4]
(R.002 ) TYP[0.05]
SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL
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1
45
8
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)0.290 (7,37)
0.014 (0,36)0.008 (0,20)
Seating Plane
4040107/C 08/96
5
40.065 (1,65)0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)0.355 (9,00)
0.015 (0,38)0.023 (0,58)
0.063 (1,60)0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification.E. Falls within MIL STD 1835 GDIP1-T8
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