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TestabilityL t 7Lecture 7: Fault Simulation
Shaahin HessabiShaahin HessabiDepartment of Computer Engineering
Sharif University of TechnologyAdapted from the presentation prepared by book authors
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O tliOutline
Problem and motivation Fault simulation algorithms
Serial Parallel Parallel Deductive Concurrent
Random Fault Sampling Summary
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Problem and Motivation Fault simulation Problem:
Given: A circuit A sequence of test vectors A fault model A fault model
Determine: Fault coverage: fraction (or percentage) of modeled faults detected
by test vectors Set of undetected faults (for test generation)
Motivation Determine test quality and in turn, product quality Find undetected fault targets to improve tests Construct fault dictionary for diagnosis Construct fault dictionary for diagnosis
– Use a fault simulator to compute & store the response for every fault– If the output response of the circuit under test matches any of the
response in the fault dictionary the fault location is identified
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response in the fault dictionary, the fault location is identified
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Yield and Defect Level Let:
Y (yield): probability that a manufactured circuit is defect-free Y (yield): probability that a manufactured circuit is defect free DL (defect level): probability of shipping a defective product d (defect coverage): the defect coverage of the test used to check for
manufacturing defectsmanufacturing defects
D = 1 Y1-d
Defec
DL = 1- Y1 d
approximate defect coverage with fault coverage
ct Level
with fault coverage
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Defect Coverage %
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High Fault Coverage: Why?g g y
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Fault Coverage vs. Defect Coverage
High fault coverage (measured for SSFs) is:g g ( )necessarybut not sufficient
for high defect coverage. Also need:
Parametric testing Delay-fault testing Bridging fault testing Bridging-fault testing Technology-specific-fault testing (e.g., CMOS stuck-open faults)
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Fault simulator in a VLSI Design gProcess
Verified designnetlist
Verificationinput stimuli
Fault simulator Test vectors
Modeledfault list
Testcompactor
Remove tested faults
Deletevectors
TestFault Lowgeneratorcoverage
? Add vectors
Adequate
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qStop
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Fault Simulation Scenarioau t S u at o Sce a o Circuit model: mixed-level
Mostly logic with some switch level for high impedance (Z) and Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults
Signal states: logic Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits
Timing: Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
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Fault Simulation Scenario (cont’d)Fault Simulation Scenario (cont d) Faults:
Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog
i it f lt i l t t t icircuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping: a fault once detected is dropped from consideration Fault dropping: a fault once detected is dropped from consideration
as more vectors are simulated; fault-dropping may be suppressed for diagnosisF lt li d l f f lt i i l t d h th Fault sampling: a random sample of faults is simulated when the circuit is large
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F lt Si l ti Al ithFault Simulation Algorithms
SerialP ll l Parallel
DeductiveC t Concurrent
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Serial Algorithm Algorithm: Simulate fault-free circuit and save responses.
Repeat following steps for each fault in the fault list:Repeat following steps for each fault in the fault list: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses y p g p
with saved responses If response differs, report fault detection and suspend simulation of
remaining vectorsremaining vectors
Advantages: Easy to implement; needs only a true-value simulator less memory Easy to implement; needs only a true value simulator, less memory Most faults, including analog faults, can be simulated
Disadvantage: Much repeated computation; CPU time g p p ;prohibitive for VLSI circuits
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Alternative to Serial Algorithm
Simulate many faults togethery g
Test vectors Fault-free circuit Comparator f1 detected?
Circuit with fault f1
Ci it ith f lt f2
Comparator f2 detected?
Circuit with fault f2
Comparator fn detected?
Circuit with fault fn
Comparator fn detected?
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Parallel Fault Simulation Compiled-code method; best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on
computer words Storage: one word per line for two-state simulation; i.e.,
fixed low memory requirementM lti i l ti E h i l t 1 Multi-pass simulation: Each pass simulates w -1 new faults, where w is the machine word lengthSpeed up over serial method w 1 Speed up over serial method ~ w -1
Not suitable for circuits with timing-critical and non-Boolean logicBoolean logic
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Parallel Fault Simulation ExampleParallel Fault Simulation ExampleBit 0: fault-free circuit
Bit 1: circuit with c s-a-0Bit 2: circuit with f s-a-1
a1 1 1
1 0 1c s-a-0 detected
bc
eg
1 1 1 1 0 11 0 1
s-a-0
d f
g0 0 0
s-a-1 0 0 1d f s a 1 0 0 1
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Parallel Fault Simulation- Multiple Values
Three signal values : { 0 1 u } A A1 A0 Three signal values : { 0, 1, u } Two bits per signal encoding:
A A1 A0
0 0 0
1 1 1
U 1 0
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Deductive Fault SimulationDeductive Fault Simulation One-pass simulationp Each line k contains a list Lk of faults detectable on k;
i.e., fault F in list Lk F causes signal k be sensitizedk
Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists
PO fault lists provide detection data Limitations:
Set-theoretic rules difficult to derive for non-Boolean gatesG t d l diffi lt t Gate delays are difficult to use
Only binary (0,1) values are easy to implement
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Deductive Fault Simulation (cont’d) AND gate
Any fault that causes an error at A or B (change A or B from 1 to 0) will cause Z to be erroneously 0. LZ = LA LB {Z s-a-0}Z A B { }
Any fault that causes A to be 1 without changing B, will cause Z to be in error ; i e Z 1will cause Z to be in error ; i.e, Z = 1 LZ = (LA L’B) {Z s-a-1} = (LA LB) {Z s-a-1}
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Deductive Fault Simulation (cont’d) Gate Z:
I f i I: set of inputs c: controlling value i: inversion i: inversion S: set of inputs with values c
The fault list of Z:
If no input has value c, any fault effect on any input propagates to the output.p
If some inputs have value c, only a fault effect that affects all the inputs at S (with value c) without affecting any of the inputs at S’ (with value c’) propagates to the outputc ) propagates to the output.
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Deductive Fault Simulation (Example)( p )
Notation: Lk is fault list for line kkn is s-a-n fault on line k
a 1 {a0} Le = La U Lc U {e0}
= {a0 , b0 , c0 , e0}
b c
e g
1 11
{b0 , c0}
{b0}
d f g
0
{b0 , d0}Lg = (Le Lf ) U {g0}
{ }
U
{b0 , d0} = {a0 , c0 , e0 , g0}{b0 , d0 , f1}Faults detected by
the input vector
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the input vector
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Concurrent Fault Simulation Event-driven simulation of fault-free circuit and only those
parts of the faulty circuit that differ in signal states from theparts of the faulty circuit that differ in signal states from the fault-free circuit.
A list per gate containing copies of the gate from all faulty A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any., g p p , y
All events of fault-free and all faulty circuits are implicitly simulated.
Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility).
Faster than other methods, but uses most memory.
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Concurrent Fault Simulation (Cont’d)
An element contains: Fault index
F lt t t Fault state• Input values• Output values• Output values
Event-driven: events include value changes in both fault-free and faulty circuits.y
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Concurrent Fault Simulation ExampleConcurrent Fault Simulation Examplea0 b0 c0 e0
1
0
10
10
01
00
1
10
a0 b0 c0 e0
a
b ce
1
11
1
1
11
1c
d f
g 0
10
1
1 00
a0 b0 c0 e0d f 00
001
1 00
000
00 0 0 0
10
011
1 11
1
0 1 0 1 1 1b0 d0
d0 g0 f1f1
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Concurrent Fault Simulation -Convergence
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Concurrent Fault Simulation -Divergence
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Comparing Fault Simulating Methods
Criteria: ability to handle : (A) Multiple signal values (B) Different levels of abstraction (C) Accurate timing (C) Accurate timing
Rank order by criteria
Parallel Deductive Concurrent
(A) ٢ ٣ ١(A)
(B) ٢ ٢ ١
(C) ٢ ٢ ١(C) ٢ ٢ ١
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Disadvantages of Deductive &gConcurrent Algorithms
Large memory to record the status of all machines Dynamic memory, (linked lists)y y, ( )
Evaluation overhead on the linked lists Performance overhead in memory managementy g
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Fault Samplingp g
A randomly selected subset (sample) of faults is simulated.y ( p ) Measured coverage in the sample is used to estimate fault
coverage in the entire circuit. Advantage: Saving in computing resources (CPU time and
memory.) Disadvantage: Limited data on undetected faults.
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Motivation for Samplingp g
Complexity of fault simulation depends on: Number of gates Number of faults Number of faults Number of vectors
Complexity of fault simulation with fault sampling depends Complexity of fault simulation with fault sampling depends on: Number of gates Number of vectors
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Random Sampling Modelp g
Detected Undetected
All faults with
fault fault
a fixed butunknowncoverage
Randompicking
coverage
Np = total number of faults(population size)
Ns = sample sizeN << N(population size)
C = fault coverage (unknown)
Ns << Npc = sample coverage
(a random variable)( )
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Probability Density of Sample CCoverage, c
(x--C )2(x C )-- ------------
1 2 2
p (x ) = Prob(x < c < x +dx ) = -------------- ep (x ) Prob(x < c < x dx ) e2 1/2
cf: page 122 of the text
)
C (1 - C)Variance2 = ------------
N Sampling
p (x
Ns
Mean = C
Samplingerror
C C +3C -3 1.0xx
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Sample coverage
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Sampling Error Boundsp gVariance of C:
C (1 - C ) | x C | = 3 1/2Sampling error: | x - C | = 3 --------------
NsSolving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate:
Sampling error:
confidence) estimate:4.5
C 3 = x ------- [1 + 0.44 Ns x (1 - x )]1/23 s
NsWhere Ns is sample size, x is the measured fault coverage in the sample.
f f f %Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample
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simulation was about 10% of that for all faults.