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Pipelining
Jin-Soo Kim([email protected])
Systems Software &Architecture Lab.
Seoul National University
Fall 2020
Chap. 4.5
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 2
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 3
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 4
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 5
▪ Sequential processing: Wash-Dry-Fold-Store
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 6
▪ Overlapping execution
▪ Parallelism improves performance
▪ Four loads:• Speedup = 8 / 3.5 = 2.3
▪ Non-stop:• Speedup = 2n / (0.5n + 1.5) ≃ 4
= number of stages
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 7
▪ Five stages, one step per stage
▪ IF: Instruction fetch from memory
▪ ID: Instruction decode & register read
▪ EX: Execute operation or calculate address
▪ MEM: Access memory operand
▪ WB: Write result back to register
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 8
▪ Sequential execution
▪ Pipelined execution
IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
IF ID EX MEM WB
add x10, x11, x12
sub x13, x14, x15
and x5, x6, x7
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 9
▪ Assume time for stages is
• 100ps for register read or write
• 200ps for other stages
▪ Compare piplined datapath with single-cycle datapath
Inst.Inst.fetch
Registerread
ALU op.Memory
accessRegister
writeTotaltime
ld 200ps 100ps 200ps 200ps 100ps 800ps
sd 200ps 100ps 200ps 200ps 700ps
R-type 200ps 100ps 200ps 100ps 600ps
beq 200ps 100ps 200ps 500ps
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 10
Single-cycle(Tc = 800ps)
Pipelined(Tc = 200ps)
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 11
▪ If all stages are balanced
• i.e., all take the same time
▪ If not balanced, speedup is less
▪ Speedup due to increased throughput
▪ Latency (time for each instruction) does not decrease
𝑻𝒊𝒎𝒆 𝒃𝒆𝒕𝒘𝒆𝒆𝒏 𝒊𝒏𝒔𝒕𝒓𝒖𝒄𝒕𝒊𝒐𝒏𝒔𝒑𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒅 =𝑻𝒊𝒎𝒆 𝒃𝒆𝒕𝒘𝒆𝒆𝒏 𝒊𝒏𝒔𝒕𝒓𝒖𝒄𝒕𝒊𝒐𝒏𝒔𝒏𝒐𝒏𝒑𝒊𝒑𝒆𝒍𝒊𝒏𝒆𝒅
𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒔𝒕𝒂𝒈𝒆𝒔
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 12
▪ RISC-V ISA designed for pipelining
▪ All instructions are 32-bits
• Easier to fetch and decode in one cycle
• (cf.) x86: 1- to 17-byte instructions
▪ Few and regular instruction formats
• Source and destination register fields located in the same place
• Can decode and read registers in one step
▪ Load/store addressing
• Can calculate address in 3rd EX stage, access memory in 4th MEM stage
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Pipelined Datapath and Control
Chap. 4.6
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WB
MEM
Right-to-left flow leads to hazards
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▪ Need registers between stages
• To hold information produced in previous cycle
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4190.308: Computer Architecture | Fall 2020 | Jin-Soo Kim ([email protected]) 16
▪ Cycle-by-cycle flow of instructions through the pipelined datapath
▪ “Single-clock-cycle” pipeline diagram
• Shows pipeline usage in a single cycle
• Highlight resource used
• (cf.) “multi-clock-cycle” diagram: graph of operation over time
▪ We’ll look at “single-clock-cycle” diagrams for load & store
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Wrongregisternumber
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▪ Form showing resource usage
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▪ State of pipeline in a given cycle
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▪ Control signals derived from instruction
• As in single-cycle implementation
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